[PATCH v2] board: starfive: visionfive2: Order board detection logic to match config

Fixup previous merge resolution of this series. Intent is to ease code readability and logic to match ordering in CONFIG_OF_LIST - Remove "starfive/" string math - Remove redundant local cache of calls to get_*_from_eeprom() - Match name before EEPROM product_id in board_fit_config_name_match() -

Re: Build for RISC-V with LLVM

On Sat, Apr 26, 2025 at 06:25:50PM -0500, Nathaniel wrote: > On Apr 26 2025, at 1:30 am, Yao Zi wrote: > > On Fri, Apr 25, 2025 at 12:43:08PM -0500, Nathaniel Hourt wrote: > > > Hi, all > > > > > > I am trying to build u-boot and SPL for my Mars board (riscv, variant of > > > the > > > starfive v

Re: Build for RISC-V with LLVM

On Apr 26 2025, at 1:30 am, Yao Zi wrote: > On Fri, Apr 25, 2025 at 12:43:08PM -0500, Nathaniel Hourt wrote: > > Hi, all > > > > I am trying to build u-boot and SPL for my Mars board (riscv, variant of the > > starfive visionfive2) following the board-specific docs [1], using > > LLVM/clang as my

Re: [PATCH 5/5] sunxi: h6/h616: Reuse common DRAM infrastructure

Dne četrtek, 17. april 2025 ob 02:18:25 Srednjeevropski poletni čas je Andre Przywara napisal(a): > On Wed, 16 Apr 2025 18:30:43 +0200 > Jernej Škrabec wrote: > > > Dne sreda, 16. april 2025 ob 01:40:04 Srednjeevropski poletni čas je Andre > > Przywara napisal(a): > > > On Fri, 11 Apr 2025 18:1

Re: [PATCH] sunxi: enable MMU_PGPROT proper page table protection

Dne sobota, 26. april 2025 ob 14:09:13 Srednjeevropski poletni čas je Andre Przywara napisal(a): > Select the new MMU_PGPROT Kconfig symbol for all Allwinner board builds, > to use a write-protected .rodata, non-executable .data and .rodata > sections, and non-writable .text sections. > > This mi

[PATCH 05/10] riscv: dts: th1520: Preserve necessary devices for SPL

SPL for TH1520 requires CPU and boot UART nodes to function. Preserve them in SPL devicetree blob with bootph-pre-ram property. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 6 ++ 1 file changed, 6 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi i

[PATCH 06/10] riscv: dts: lichee-module-4a: Preserve memory node for SPL

Memory node is necessary for TH1520 SPL to configure size and base address of DRAM. Let's preserve it in SPL devicetree blob. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520-lichee-module-4a.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts/th1520-lichee-module-4a.dtsi b/a

[PATCH] riscv: dts: binman.dtsi: Drop filename property for proper U-Boot

Drop filename property for proper U-Boot entry since binman takes "u-boot-nodtb.bin" as the default filename for u-boot-nodtb entries. This follows efe9c12322b ("riscv: dts: binman.dtsi: Switch to u-boot-nodtb entry for proper U-Boot") to clean binman.dtsi up. Signed-off-by: Yao Zi --- Here's t

Re: [PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

On Sat, Apr 26, 2025 at 04:56:58PM +, Yao Zi wrote: > This patch cleans the vendor code of DDR initialization up, converts the > driver to fit in DM framework and use a firmware[1] packaged by binman to > ship PHY configuration. > > Currently the driver is only capable of initializing the cont

[PATCH 08/10] riscv: dts: th1520: Add binman configuration

Add binman configuration for TH1520 SoC, whose BROM loads the image combined into SRAM and directly jumps to it. The configuration creates u-boot-with-spl.bin where the SPL code locates at the start and the DDR firmware is shipped. Signed-off-by: Yao Zi --- arch/riscv/dts/thead-th1520-binman.dts

[PATCH 07/10] riscv: dts: th1520: Add DRAM controller

Describe DRAM controller integrated in TH1520 SoC and preserve it in SPL devicetree blob. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 10 ++ 1 file changed, 10 insertions(+) diff --git a/arch/riscv/dts/th1520.dtsi b/arch/riscv/dts/th1520.dtsi index ef84d8cc265..b908eb37e41 10

[PATCH 10/10] doc: thead: lpi4a: Update documentation

Support for eMMC, SD card, GPIO and SPL have been available in LPi4A port. Update the documentation of support status and build instructions. Signed-off-by: Yao Zi --- doc/board/thead/lpi4a.rst | 58 +-- 1 file changed, 55 insertions(+), 3 deletions(-) diff -

[PATCH 09/10] board: thead: licheepi4a: Enable SPL support

Adjust Kconfig and defconfig and add SPL initialization code for Lichee Pi 4A. Then enable SPL support which we've added for TH1520 SoC earlier. The board devicetree is changed to use TH1520 binman configuration to generate bootable images. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520-lichee-

[PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by

[PATCH 04/10] ram: thead: Add initial DDR controller support for TH1520

This patch cleans the vendor code of DDR initialization up, converts the driver to fit in DM framework and use a firmware[1] packaged by binman to ship PHY configuration. Currently the driver is only capable of initializing the controller to work with dual-rank 3733MHz LPDDR4, which is shipped by

[PATCH 01/10] riscv: lib: Split out support for T-Head cache management operations

Designed before a standard set of cache management operations defined in RISC-V, earlier T-Head cores like C906 and C910 provide CMO through the customized extension XTheadCMO, which has been used in the CV1800B port of U-Boot. This patch splits XTheadCMO-related code into a generic module, allowi

[PATCH 03/10] riscv: cpu: Add TH1520 CPU support

Introduce the SoC-specific code and corresponding Kconfig entries for TH1520 SoC. Following features are implemented for TH1520, - Cache enable/disable through customized CSR - Invalidation of customized PMP entries - DRAM driver probing for SPL Signed-off-by: Yao Zi --- arch/riscv/Kconfig

[PATCH 02/10] riscv: dts: th1520: Add clock-frequency for UART0

The BROM of TH1520 always initializes its clock and configure the baudrate to 115200. Add a clock-frequency property to provide such information without introducing CCF to SPL. Signed-off-by: Yao Zi --- arch/riscv/dts/th1520.dtsi | 1 + 1 file changed, 1 insertion(+) diff --git a/arch/riscv/dts

[PATCH 00/10] Initial SPL support for T-Head TH1520 SoC

This series adds initial SPL support for T-Head TH1520 SoC and Sipeed Lichee Pi 4A board. Key changes include, - Support for T-Head-specific cache management operations is split out of CV1800B port and adapted for usage in other ports. - A new CPU target, THEAD_TH1520, is added with SPL support

Re: [GIT PULL] u-boot-riscv/master

On Fri, Apr 25, 2025 at 06:13:38PM -0700, E Shattow wrote: > The outcome of that merge went a bit weird for > board/starfive/visionfive2/spl.c > > On 4/25/25 16:43, Tom Rini wrote: > > On Fri, 25 Apr 2025 18:07:54 +0800, Leo Liang wrote: > > > >> The following changes since commit > >> 10f483651

Re: [GIT PULL] u-boot-riscv/master

On Fri, Apr 25, 2025 at 10:35:30AM +, Yao Zi wrote: > Hi Leo, > > On Fri, Apr 25, 2025 at 06:07:54PM +0800, Leo Liang wrote: > > Hi Tom, > > > > The following changes since commit 10f48365112b164bee6564033ab682747efcb483: > > > > Merge patch series "Add PCIe support for TI AM64 SoC" (2025-

[PATCH] sunxi: enable MMU_PGPROT proper page table protection

Select the new MMU_PGPROT Kconfig symbol for all Allwinner board builds, to use a write-protected .rodata, non-executable .data and .rodata sections, and non-writable .text sections. This might trigger runtime exceptions in misbehaving drivers, which should then be fixed. Please report on the list

Question regarding arch-fs-layerscape in the context of DDR

Hi I've got a question regarding arch-fs-layerscape and would be grateful if somebody could help me to get a better understanding of a few things before I submit a patch with some changes so that I won't make a mess on the mailing list with unnecessary changes. 1) Looking at the ls1028a_common.h -