On 12/6/23 06:29, Tejas Bhumkar wrote:
A set of patches has been developed to resolve concerns regarding
data integrity failures in QSPI and OSPI for the Versal, Versal NET,
Zynq, and ZynqMP platforms.
The series has undergone testing with flashes on the default setup,
and comprehensive testi
On 05.12.23 21:00, Maxim Uvarov wrote:
On Wed, 6 Dec 2023 at 00:25, Soeren Moch wrote:
On 05.12.23 17:25, Maxim Uvarov wrote:
On Tue, 5 Dec 2023 at 21:49, Soeren Moch wrote:
On 05.12.23 14:15, Maxim Uvarov wrote:
I think I solved the size issue on all the boards.
On Wed, 6 Dec 2023 at 09:24, Simon Glass wrote:
>
> Hi Sumit,
>
> On Tue, 5 Dec 2023 at 00:44, Sumit Garg wrote:
> >
> > Hi Simon,
> >
> > On Tue, 5 Dec 2023 at 06:22, Simon Glass wrote:
> > >
> > > Hi Sumit,
> > >
> > > On Tue, 21 Nov 2023 at 23:21, Sumit Garg wrote:
> > > >
> > > > Hi Caleb,
From: Venkatesh Yadav Abbarapu
Spansion nor flashes provide block protection support using
BP0, BP1, BP2 bits in status register.
The top/bottom select is instead done via a bit in the configuration
register, which is OTP, so once set to use bottom protect, one cannot
use top. On top of that, re
From: Venkatesh Yadav Abbarapu
ISSI chips implements locking in (power-of-two multiple of) 64K
blocks, not as a fraction of the chip's size. Bit 5 in the status
register is not a top/bottom select bit, but instead a fourth value
bit, allowing locking between 2^0 and 2^14 64K blocks (so up to 1GiB
The Cadence driver must switch between SDR and DTR modes based
on commands from the SPI-NOR framework and the configuration
set by SPI_FLASH_DTR_ENABLE. If SPI_FLASH_DTR_ENABLE is enabled,
the driver should transition to DTR mode; if it is not defined,
the driver should avoid switching to DTR mode,
From: Venkatesh Yadav Abbarapu
GIGADEVICE nor flashes provide block protection support using
BP0, BP1, BP2, BP3 & TB bits in status register.
BP(Block Protection) bits defines memory to be software
protected against PROGRAM or ERASE operations. When one or more
block protect bits are set to 1, a
From: Venkatesh Yadav Abbarapu
Macronix chips implements locking in (power-of-two multiple of) 64K
blocks, not as a fraction of the chip's size. Bit 5 in the status
register is not a top/bottom select bit, but instead a fourth value
bit, allowing locking between 2^0 and 2^14 64K blocks (so up to
From: Ashok Reddy Soma
Incase of non-aligned length of flash data, ahbbase address is written
directly with byte count. This is causing AHB bus error's sometimes and
resulting in kernel crash while booting linux. To avoid this write 4 byte
aligned byte count to ahbbase address.
Also use a tempor
From: T Karthik Reddy
Micron nor flashes provide block protection support using
BP0, BP1, BP2, BP3 & TB bits in status register. This patch
supports for micron nor flashes with manufacturer id 0x20
and 0x2c.
Where BP(Block Protection) bits defines memory to be software
protected against PROGRAM
From: T Karthik Reddy
In DDR mode, current default spi_mem_dtr_supports_op() function does
not allow mixed DTR operation functionality. So implement cadence
specific cadence_spi_mem_dtr_supports_op() function to verifying only
the command buswidth and command opcode bytes which satisfies the DTR
Activate the xSPI Software Reset support, which will be
utilized to transition from octal DTR mode to legacy
mode during shutdown and boot (if enabled).
Signed-off-by: T Karthik Reddy
Signed-off-by: Tejas Bhumkar
---
configs/xilinx_versal_virt_defconfig | 2 ++
1 file changed, 2 insertions(+)
From: Ashok Reddy Soma
Enable ECO bit for Versal for frequencies above 120Mhz
for octal spi to work properly.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/spi/cadence_qspi.h | 1 +
drivers/spi/cadence_qspi_apb.c | 4
2 files changed, 5 insertions(+)
diff
From: Ashok Reddy Soma
Read and Write watermark registers are not initialized. Set read
watermark to half of the FIFO and write watermark to 1/8 of the
FIFO size.
Read watermark indicates if SRAM fill level is above this watermark,
interrupt will be generated and read or DMA can be performed.
W
From: Ashok Reddy Soma
This patch cleans up the cadence qspi registers in the init.
The register contents may be invalid if this controller is
used in previous boot and comes to uboot after a softreset
(no power on reset). This may cause issues in uboot.
Signed-off-by: Ashok Reddy Soma
Signed-o
From: T Karthik Reddy
Set cmd, address & data buswidth to octal. Handle dummy clock
cycles incase of reads & writes. Convert odd bytes to even
bytes lengths in ddr mode, as we cannot rx/tx odd data in
ddr mode.
Disable the DMA once the transfer is done to avoid disabling
it at other places.
Sig
To reduce the CPU load in waiting for the OSPI internal SRAM to
clear in indirect mode, it's better to use the
CQSPI_REG_IRQSTATUS register to check for indirect operation to complete.
Enabled interrupt for Indirect Complete and Transfer Watermark
Breach interrupt status register bits and using rea
From: Ashok Reddy Soma
tshsl_ns is the clock delay for chip select deassert. This is the delay in
master reference clocks for the length that the master mode chip select
outputs are de-asserted between transactions.
The minimum delay is always SCLK period to ensure the chip select is never
re-as
From: T Karthik Reddy
Cadence driver need to switch from SDR to DTR and vice versa based on
the commands from spi-nor framework and based on SPI_FLASH_DTR_ENABLE
config. If SPI_FLASH_DTR_ENABLE is not defined, do not switch to DTR
mode as it represents that controller does not support DTR. Also d
From: Ashok Reddy Soma
With 'commit bebdc237507c ("mtd: spi-nor: Parse SFDP SCCR Map")', support
for spi_nor_parse_sccr is added under SFDP. But the flag
SNOR_F_IO_MODE_EN_VOLATILE in spi_nor_octal_dtr_enable is always
checked. Check this flag only if SPI_FLASH_SFDP_SUPPORT enabled.
Signed-off-b
If the system is in a dual parallel configuration, it's necessary to
halve the erase size since the erase command operates on two flashes
simultaneously. When dealing with a dual-stacked configuration,
determine whether the erase offset refers to the top or bottom flash,
and subsequently, adjust th
From: T Karthik Reddy
To switch the OSPI controller from SDR to DDR mode, the
RX delay should be configured through flash tuning. Begin
by establishing a constant value for the TX delay and then
increase the RX delay by inspecting the flash IDs. To fine-tune
the RX delay, compare the flash IDs wi
From: Ashok Reddy Soma
Write enable(06h) command will be sent to a flash device to
set the write enable latch bit before every program, erase,
write command. After that write disable command (04h) needs
to be sent to clear the write enable latch.
This write_disable() is missing at the majority o
From: T Karthik Reddy
Added support to program quad enable bit for Winbond flash memory.
Previously, the quad enable function from Spansion was used for
this purpose. However, for Winbond flash memory, the quad
enable bit is configured by programming the Write Status Register-2
(SR-2) rather than
From: Algapally Santosh Sagar
Add support for Winbond 256MB flash W25Q02NW which supports 4byte
opcodes and also dual and quad read.
Signed-off-by: Algapally Santosh Sagar
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/spi-nor-ids.c | 6 ++
1 file change
From: Venkatesh Yadav Abbarapu
The block protection flags for Gigadevice, Spansion, and ISSI flash
memory have been modified. Additionally, new flags for
SPI_NOR_OCTAL_DTR_READ and octal DTR page programming have been
introduced for Micron OSPI flashes. Furthermore, the flashes mt35xu01g
and mt35
From: T Karthik Reddy
Some flash devices have multiple dies in it & has die cross over
issue. When SPI_NOR_MULTI_DIE flag is set in flash id table use
it to enable split reads to avoid above issue. Define SPI_NOR_MULTI_DIE
new flag to flash id flags. Remove SPI_FLASH_SPLIT_READ config and
related
From: Ashok Reddy Soma
Define a flag SPI_NOR_OCTAL_DTR_PP and if enabled in spi-nor-ids table,
enable octal DTR page program in the framework.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Tejas Bhumkar
---
drivers/mtd/spi/sf_internal.h | 1 +
drivers/mtd/spi/spi-nor-core.c | 3 ++-
2 files
From: Ashok Reddy Soma
In a dual parallel configuration, halve the read offset.
Determine whether the read offset points to the lower or
upper flash in a dual stacked configuration and set the
corresponding flags accordingly.
Include support for cases where the read involves an odd
number of byt
From: Ashok Reddy Soma
Enable mt35xu512aba_fixups for all mt35 series flashes to work
in DTR mode, and return after nor->fixups is updated, otherwise
it will get overwritten with macronix_octal_fixups.
This flash works in DTR mode only if CONFIG_SPI_FLASH_MT35XU
is enabled and SPI_NOR_OCTAL_DTR_R
The Micron MT35 series octal flashes can be activated
through the configuration option CONFIG_SPI_FLASH_MT35XU.
To ensure their detection, enable this option in the
default defconfig for octal flashes.
Signed-off-by: Tejas Bhumkar
---
configs/xilinx_versal_virt_defconfig | 1 +
1 file changed, 1
From: T Karthik Reddy
In current implementation dummy buswidth is set equal to address
buswidth. In case of quad spi (mode 1-1-4), where address width is 1
the dummy bytes will be calculated to 1(8 dummy cycles) and dummy
buswidth is set to 1. Due to this, the controller driver will introduce
8 d
From: T Karthik Reddy
The spi-nor framework will set up the flash parameters by
reading the flash id table flags, which include cmd opcodes,
address width, dummy bytes, and bus width. In case, flash
supports octal DTR mode and the controller does not support
the DTR. There is no process to switch
A set of patches has been developed to resolve concerns regarding
data integrity failures in QSPI and OSPI for the Versal, Versal NET,
Zynq, and ZynqMP platforms.
The series has undergone testing with flashes on the default setup,
and comprehensive testing is currently underway to test the seri
Le 5 déc. 2023 à 13:48, Daniel Thompson a écrit :
On Tue, Dec 05, 2023 at 10:36:28AM +, ff wrote:
Le 5 déc. 2023 à 10:46, Sumit Garg a écrit :
+ U-boot custodians list
On Tue, 5 Dec 2023 at 12:58, Krzysztof Kozlowski
wrote:
On 05/12/2023 08:13, Sumit Garg wrote:
@DT bindings maintaine
On Tue, 5 Dec 2023 at 15:39, Krzysztof Kozlowski
wrote:
>
> On 05/12/2023 10:45, Sumit Garg wrote:
> > + U-boot custodians list
> >
> > On Tue, 5 Dec 2023 at 12:58, Krzysztof Kozlowski
> > wrote:
> >>
> >> On 05/12/2023 08:13, Sumit Garg wrote:
> > @DT bindings maintainers,
> >
> > Gi
Hi Simon,
On 06/12/23 09:24, Simon Glass wrote:
On Tue, 5 Dec 2023 at 02:42, Neha Malcom Francis wrote:
K3 devices introduces the concept of centralized power, resource and
security management to System Firmware. This is to overcome challenges
by the traditional approach that implements syste
Hi Ilias,
On Mon, 4 Dec 2023 at 23:22, Ilias Apalodimas
wrote:
>
> Hi Simon,
>
> We did discuss this in OSFC but perhaps you forgot. The discussion
> was based on the mail here [0].
Perhaps I did? Or perhaps we had a different understanding of it?
>
> On Tue, 5 Dec 2023 at 02:52, Simon Glass
Hi Shantur,
On Tue, 5 Dec 2023 at 04:13, Shantur Rathore wrote:
>
> Hi Simon,
>
> On Tue, Dec 5, 2023 at 12:52 AM Simon Glass wrote:
> >
> > Hi Shantur,
> >
> > On Mon, 4 Dec 2023 at 05:38, Shantur Rathore wrote:
> > >
> > > Hi Simon,
> > >
> > > On Sun, Nov 19, 2023 at 4:56 PM Shantur Rathore
Hi Ahmad,
On Tue, 5 Dec 2023 at 04:48, Ahmad Fatoum wrote:
>
> Hello Simon,
>
> On 02.12.23 04:54, Simon Glass wrote:
> > Add a script which produces a Flat Image Tree (FIT), a single file
> > containing the built kernel and associated devicetree files.
> > Compression defaults to gzip which give
Hi Mattijs,
On Tue, 5 Dec 2023 at 02:16, Mattijs Korpershoek
wrote:
>
> Hi Simon,
>
> Thank you for your patch.
>
> On dim., déc. 03, 2023 at 17:31, Simon Glass wrote:
>
> > Given the name of this variable, it should be an address, not a
> > pointer. Update this, to make it easier to use with sa
On Tue, 5 Dec 2023 at 02:42, Neha Malcom Francis wrote:
>
> Move the DM entry in tispl.bin FIT image from default fetching an
> external blob entry to fetching using ti-dm entry type. This way, the
> DM entry will be populated by the TI_DM pathname if provided. Else it
> will resort to the ti-dm.b
On Tue, 5 Dec 2023 at 06:47, Caleb Connolly wrote:
>
> Qualcomm PMICs include a "pon" function which handles two buttons, the
> power button and "resin" button (usually volume down). Introduce a new
> driver following upstream Linux DT to enable these and map them to Enter
> and Down respectively
On Tue, 5 Dec 2023 at 06:47, Caleb Connolly wrote:
>
> priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
> with the upper bits being used for error codes. Do error checking before
> downcasting to u32 to prevent errors being silently ignored.
>
> Reviewed-by: Sumit Garg
> Re
On Tue, 5 Dec 2023 at 02:42, Neha Malcom Francis wrote:
>
> K3 devices introduces the concept of centralized power, resource and
> security management to System Firmware. This is to overcome challenges
> by the traditional approach that implements system control functions on
> each of the processi
Hi Caleb,
On Tue, 5 Dec 2023 at 06:48, Caleb Connolly wrote:
>
> Use the upstream gpio-ranges property instead of gpio-count, and drop
> the bank-name property for Qualcomm boards.
>
> Reviewed-by: Neil Armstrong
> Reviewed-by: Sumit Garg
> Tested-by: Sumit Garg
> Signed-off-by: Caleb Connolly
On Tue, 5 Dec 2023 at 06:48, Caleb Connolly wrote:
>
> Upstream uses the gpio-ranges property to define the number of GPIOs,
> support for parsing this when gpio-count is unspecified
>
> Additionally, drop the bank-name property as it isn't used in upstream,
> and we can just hardcode the bank nam
Hi,
I am replying to this email since it still has the context below.
On Mon, 4 Dec 2023 at 03:48, Mark Kettenis wrote:
>
> > From: Simon Glass
> > Date: Sun, 3 Dec 2023 17:26:17 -0700
>
> Hi Simon,
>
> There is a typo in first line of the commit message: s/netbds/netbsd/.
>
> > It isn't clear
Hi Sumit,
On Tue, 5 Dec 2023 at 00:44, Sumit Garg wrote:
>
> Hi Simon,
>
> On Tue, 5 Dec 2023 at 06:22, Simon Glass wrote:
> >
> > Hi Sumit,
> >
> > On Tue, 21 Nov 2023 at 23:21, Sumit Garg wrote:
> > >
> > > Hi Caleb,
> > >
> > > On Tue, 21 Nov 2023 at 22:39, Caleb Connolly
> > > wrote:
> >
Hi Caleb,
On Tue, 5 Dec 2023 at 03:55, Caleb Connolly wrote:
>
>
>
> On 05/12/2023 07:44, Sumit Garg wrote:
> > Hi Simon,
> >
> > On Tue, 5 Dec 2023 at 06:22, Simon Glass wrote:
> >>
> >> Hi Sumit,
> >>
> >> On Tue, 21 Nov 2023 at 23:21, Sumit Garg wrote:
> >>>
> >>> Hi Caleb,
> >>>
> >>> On Tu
It's possible for composite clocks to have a divider that does not
implement set_rate() operation. For example, sandbox_clk_composite()
registers composite clock with a divider that only has get_rate().
Currently clk_composite_set_rate() only checks thate rate_ops are
present, so for sandbox it wil
Add a simple test case which sets clock rate to its current value.
Signed-off-by: Igor Prusov
---
test/dm/clk_ccf.c | 9 +
1 file changed, 9 insertions(+)
diff --git a/test/dm/clk_ccf.c b/test/dm/clk_ccf.c
index e4ebb93cda..3b23982541 100644
--- a/test/dm/clk_ccf.c
+++ b/test/dm/clk_cc
On sandbox it's possible to trigger NULL dereference when setting rate
of a composite clock. It happens because sandbox composite divider does
not implement set_rate() operation. This series adds NULL check and a
test cases for clk_set_rate().
Igor Prusov (2):
clk: Check that composite clock's
Hi Chris,
On 2023-12-05 22:39, Chris Morgan wrote:
> From: Chris Morgan
>
> The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
> UART, ADC, eMMC, and SDMMC are tested to work.
>
> Signed-off-by: Chris Morgan
> ---
> arch/arm/dts/Makefile| 1 +
> arch
From: Chris Morgan
The Powkiddy X55 is a Rockchip RK3566 based handheld gaming device.
UART, ADC, eMMC, and SDMMC are tested to work.
Signed-off-by: Chris Morgan
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/rk3566-powkiddy-x55-u-boot.dtsi | 67 ++
arch/arm/dts/rk3566
Hi Dmitry,
> First of all, thank you for all your reviews. I hope I can answer all
> your questions here. If I forget something please let me know.
Absolutely.
> I don't have much experience with arm/arm64 and I don't have previous
> experience with u-boot and contributing to it. So please guide
Hi Dmitry,
> > I've given these a cursory look over, I have a system to test and will
> > give them a whirl in the next few days, I was planning to start
> > playing over the weekend so you've provided a great start :)
>
> Did you have any chance to test my patches?
Not yet, apologies, work has b
On Wed, 6 Dec 2023 at 00:25, Soeren Moch wrote:
>
>
> On 05.12.23 17:25, Maxim Uvarov wrote:
>
>
>
> On Tue, 5 Dec 2023 at 21:49, Soeren Moch wrote:
>
>> On 05.12.23 14:15, Maxim Uvarov wrote:
>>
>> I think I solved the size issue on all the boards.
>>
>> Key changes:
>> 1. remove compilation of
Hi Simon and Heinrich,
On Sun, Dec 3, 2023 at 8:38 PM Simon Glass wrote:
>
> Hi Heinrich,
>
> On Sun, 3 Dec 2023 at 13:00, Heinrich Schuchardt
> wrote:
> >
> > On 12/3/23 20:50, Simon Glass wrote:
> > > Hi Heinrich,
> > >
> > > On Sun, 3 Dec 2023 at 11:33, Heinrich Schuchardt
> > > wrote:
> > >
On Sun, 3 Dec 2023 21:57:51 -0800
Stephen Graf wrote:
Hi Stephen,
> I have tested a newly built u-boot with the patches you provided and it works
> well.
> It is the same configuration as what I have been testing with for the last
> few weeks.
>
> I loaded the U-boot to SPI flash and tested w
On 05.12.23 17:25, Maxim Uvarov wrote:
On Tue, 5 Dec 2023 at 21:49, Soeren Moch wrote:
On 05.12.23 14:15, Maxim Uvarov wrote:
I think I solved the size issue on all the boards.
Key changes:
1. remove compilation of original ping.c and tftp.c (tftp had
also server code
Hi,
On Tue, Dec 5, 2023 at 3:16 AM Ahmad Fatoum wrote:
>
> Hello,
>
> On 04.12.23 18:52, Doug Anderson wrote:> On Sat, Dec 2, 2023 at 8:37 AM Simon
> Glass wrote:
> >> On Thu, 30 Nov 2023 at 19:04, Ahmad Fatoum wrote:
> >>> On 30.11.23 21:30, Simon Glass wrote:
> On Wed, 29 Nov 2023 at 12
On 12/5/23 9:22 AM, Nishanth Menon wrote:
On 08:46-20231205, Andrew Davis wrote:
On 12/4/23 1:29 PM, Nishanth Menon wrote:
On 15:59-20231201, Dhruva Gole wrote:
Delete the flag CFG_WITH_SOFTWARE_PRNG as it's not necessary/ boot
requirement for this SoC
Signed-off-by: Dhruva Gole
---
On Tue, 5 Dec 2023 at 21:49, Soeren Moch wrote:
> On 05.12.23 14:15, Maxim Uvarov wrote:
>
> I think I solved the size issue on all the boards.
>
> Key changes:
> 1. remove compilation of original ping.c and tftp.c (tftp had also server
> code, so I will partially bring it back.)
>
> Interesting.
Add details regarding scheme which need to be followed in SPL and
further stages for those regions which need to be preserved across
bootstages.
Signed-off-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V1->V3:
No change.
V4:
Split this to separate patch and add more details regarding
memory
Add info regarding splash screen, video, bloblist and GPIO related
Kconfigs which were missing in the documentation.
Signed-off-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V2: No change
V3: No change
V4: Patch split from parent
V5: Add Reviewed-by
---
doc/develop/spl.rst | 9 +
1 f
Skip framebufer reservation if it was already reserved from previous
stage and whose information was passed using a bloblist.
Return error in case framebuffer information received from bloblist is
invalid i.e NULL or empty.
While at it, improve the debug message to make it more clear that
address
Fill video handoff fields in video_post_probe as at this point we have
full framebuffer-related information.
Also fill all the fields available in video hand-off struct as those
were missing earlier and U-boot framework expects them to be filled for
some of the functionalities.
While filling fram
Start reservations needed for init sequence only after catching
bloblists from previous stage.
This is to avoid catching bloblists in the middle causing gaps while
u-boot is reserving.
Adjust the relocaddr as per video hand-off information received from
previous stage so that further reservations
Remove video_setup from evm_init sequence since video memory is getting
called at an earlier place to make sure video memory is reserved at
the end of RAM.
Suggested-by: Simon Glass
Signed-off-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V2: No change
V3: No change
V4: Add Reviewed-by
V5: N
Setup video memory before page table reservation using
"spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
reserved from the end of RAM.
This is done to enable the next stage to directly skip the
pre-reserved area from previous stage right from the end of RAM without
having to m
Add an API which enforces framebuffer reservation from end of RAM.
This is done so that next stage can directly skip this region before
carrying out further reservations.
Signed-off-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V2:
No change.
V3:
Change spl_reserve_video to spl_reserve_video
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations
On 05.12.23 14:15, Maxim Uvarov wrote:
I think I solved the size issue on all the boards.
Key changes:
1. remove compilation of original ping.c and tftp.c (tftp had also
server code, so I will partially bring it back.)
Interesting.
@Tom: Is there other server code in u-boot, that is enabled by
On 08:46-20231205, Andrew Davis wrote:
> On 12/4/23 1:29 PM, Nishanth Menon wrote:
> > On 15:59-20231201, Dhruva Gole wrote:
> > > Delete the flag CFG_WITH_SOFTWARE_PRNG as it's not necessary/ boot
> > > requirement for this SoC
> > >
> > > Signe
On Wed, Nov 29, 2023 at 1:37 PM Etienne Carriere
wrote:
>
> Change optee driver service enumeration to not enumerate (and
> allocate a zero sized shared memory buffer) when OP-TEE
> reports that there is no service to enumerate.
>
> This change fixes an existing issue that occurs when the such zer
On Wed, Nov 29, 2023 at 1:37 PM Etienne Carriere
wrote:
>
> Change optee probe function to only warn when service enumeration
> sequence fails instead of reporting an optee driver probe failure.
> Indeed U-Boot can still use OP-TEE even if some OP-TEE services are
> not discovered.
>
> Fixes: 94cc
On 12/4/23 1:29 PM, Nishanth Menon wrote:
On 15:59-20231201, Dhruva Gole wrote:
Delete the flag CFG_WITH_SOFTWARE_PRNG as it's not necessary/ boot
requirement for this SoC
Signed-off-by: Dhruva Gole
---
doc/board/beagle/am62x_beagleplay.rst | 1 -
1 file changed, 1 deletion(-)
diff --git a
On 12/5/23 06:17, padmarao.beg...@microchip.com wrote:
On Mon, 2023-11-06 at 12:56 +0100, Michal Simek wrote:
EXTERNAL EMAIL: Do not click links or open attachments unless you
know the content is safe
MicroBlaze V is new AMD/Xilinx soft-core 32bit RISC-V processor IP.
It is hardware compatib
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't hav
The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Signed-off-by: Caleb Conno
This property is not part of the dt bindings and all boards use the new
gpio-ranges property instead. Drop support for this.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 -
Use the upstream gpio-ranges property instead of gpio-count, and drop
the bank-name property for Qualcomm boards.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 3 +--
arch/arm/dts/dragonboard820c.
Upstream uses the gpio-ranges property to define the number of GPIOs,
support for parsing this when gpio-count is unspecified
Additionally, drop the bank-name property as it isn't used in upstream,
and we can just hardcode the bank name instead.
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Sig
Remove the (now unused) GPIO driver for the power and resin buttons on
the PMIC.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
drivers/gpio/Kconfig | 5 +-
drivers/gpio/qcom_pmic_gpio.c | 104
The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Reviewed-by: Neil Armstrong
Reviewed-by: Sumit Garg
Tested-by: Sumit Garg
Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.
Reviewed-by: Neil Armstrong
Rev
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Reviewed-by: Sumit Garg
Reviewed-by: Neil Armstrong
Tested-by: Sumit Garg
Signed-off-by:
This series addresses some long-standing issues with the SPMI arb
driver, the PMIC, and the PMIC GPIO. It fixes compatibility with
upstream Linux devicetrees, and simplifies pwrkey/resin support by
rewriting the pon driver to be a button driver rather than a GPIO
driver.
Existing users are adjuste
I think I solved the size issue on all the boards.
Key changes:
1. remove compilation of original ping.c and tftp.c (tftp had also server
code, so I will partially bring it back.)
2. LTO=y
3. CONFIG_LOGLEVEL=3 instead of 4.
4. CONFIG_CMD_DATE is not set
5. CONFIG_CMD_LICENSE is not set
6. CONFIG_C
On Tue, Dec 05, 2023 at 10:36:28AM +, ff wrote:
> > Le 5 déc. 2023 à 10:46, Sumit Garg a écrit :
> >
> > + U-boot custodians list
> >
> >> On Tue, 5 Dec 2023 at 12:58, Krzysztof Kozlowski
> >> wrote:
> >>
> >> On 05/12/2023 08:13, Sumit Garg wrote:
> > @DT bindings maintainers,
> >
>
> Le 5 déc. 2023 à 10:46, Sumit Garg a écrit :
>
> + U-boot custodians list
>
>> On Tue, 5 Dec 2023 at 12:58, Krzysztof Kozlowski
>> wrote:
>>
>> On 05/12/2023 08:13, Sumit Garg wrote:
> @DT bindings maintainers,
>
> Given the ease of maintenance of DT bindings within Linux ker
Hi Devarsh,
On 25/11/23 21:56, Devarsh Thakkar wrote:
> Setup video memory before page table reservation using
> "spl_reserve_video_from_ram_top" which ensures framebuffer memory gets
> reserved from the end of RAM.
>
> This is done to enable the next stage to directly skip the
> pre-reserved area
Add below test cases for mii commands:
mii_info -To display MII PHY info
mii_list - To list MII devices
mii_set_device - To set MII device
mii_read - To reads register from MII PHY address
mii_dump - To display data from MII PHY address
Signed-off-by: Love Kumar
---
Changes in v2:
- Get MII dev
Hello Simon,
On 02.12.23 04:54, Simon Glass wrote:
> Add a script which produces a Flat Image Tree (FIT), a single file
> containing the built kernel and associated devicetree files.
> Compression defaults to gzip which gives a good balance of size and
> performance.
>
> The files compress from a
Hi Devarsh,
On 10/11/23 20:59, Devarsh Thakkar wrote:
> Add function spl_reserve_video which is a wrapper
> around video_reserve to setup video memory and update
> the relocation address pointer.
>
> Setup video memory before page table reservation so that
> framebuffer memory gets reserved from t
Hello,
On 04.12.23 18:52, Doug Anderson wrote:> On Sat, Dec 2, 2023 at 8:37 AM Simon
Glass wrote:
>> On Thu, 30 Nov 2023 at 19:04, Ahmad Fatoum wrote:
>>> On 30.11.23 21:30, Simon Glass wrote:
On Wed, 29 Nov 2023 at 12:54, Ahmad Fatoum wrote:
> On 29.11.23 20:44, Simon Glass wrote:
>>
Hi Simon,
On Tue, Dec 5, 2023 at 12:52 AM Simon Glass wrote:
>
> Hi Shantur,
>
> On Mon, 4 Dec 2023 at 05:38, Shantur Rathore wrote:
> >
> > Hi Simon,
> >
> > On Sun, Nov 19, 2023 at 4:56 PM Shantur Rathore wrote:
> > >
> > >
> > > Currently bootmeth_efi crashes while doing a network (dhcp) boo
Migrate to the new environment format and drop most of the config.h.
Signed-off-by: Yong-Xuan Wang
---
board/sifive/unmatched/unmatched.env | 19 ++
configs/sifive_unmatched_defconfig | 2 +-
include/configs/sifive-unmatched.h | 37
3 files changed,
On 05/12/2023 07:44, Sumit Garg wrote:
> Hi Simon,
>
> On Tue, 5 Dec 2023 at 06:22, Simon Glass wrote:
>>
>> Hi Sumit,
>>
>> On Tue, 21 Nov 2023 at 23:21, Sumit Garg wrote:
>>>
>>> Hi Caleb,
>>>
>>> On Tue, 21 Nov 2023 at 22:39, Caleb Connolly
>>> wrote:
[...]
== DT loading ==
>>>
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