On 11/27/23 02:05, Chanho Park wrote:
The wdt_start function takes timeout_ms as a parameter and starts the
watchdog with this value. However, when you output the message, it shows
the default timeout value for the watchdog device.
So this patch fixes that part to output the correct timeout value
MMIO region in the
range 0x4'' - 0x5''. The added regions cover all MMIO
annotated in Apple's device tree in this range.
Signed-off-by: Janne Grunau
---
Changes in v2:
- use SZ_1G as block size
- Link to v1:
https://lore.kernel.org/r/20231130-apple_t602
hi Simon,
On Thu, 30 Nov 2023 at 08:16, Simon Glass wrote:
>
> Hi Sughosh,
>
> On Wed, 22 Nov 2023 at 00:40, Sughosh Ganu wrote:
> >
> > hi Ilias,
> >
> > On Wed, 22 Nov 2023 at 13:06, Ilias Apalodimas
> > wrote:
> > >
> > > Hi all,
> > >
> > > On Wed, 22 Nov 2023 at 07:23, Sughosh Ganu
> > >
Hi Andrew,
On 09:11-20231130, Andrew Davis wrote:
> On 11/30/23 5:55 AM, Apurva Nandan wrote:
> > Introduce the base dts files needed for u-boot or to augment the linux
> > dtbs for use in the u-boot-spl and u-boot binaries.
> >
> > Signed-off-by: Hari Nagalla
&g
From: Ashok Reddy Soma
Read chipselect properties from DT which are populated using 'reg'
property and save it in plat->cs[] array for later use.
Also read multi chipselect capability which is used for
parallel-memories and return errors if they are passed on using DT but
driver is not capable o
Add support for parallel memories in zynqmp_gqspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those command
Add support for parallel memories in zynq_qspi.c driver. In case of
parallel memories STRIPE bit is set and sent to the qspi ip, which will
send data bits to both the flashes in parallel. However for few commands
we should not use stripe, instead send same data to both the flashes.
Those commands a
From: Ashok Reddy Soma
Add support for parallel memories and stacked memories configuration
in read_bar and write_bar functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 55 +-
1 file changed,
From: Ashok Reddy Soma
Add support for parallel memories flash configuration in read status
register and read flag status register functions.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Venkatesh Yadav Abbarapu
---
drivers/mtd/spi/spi-nor-core.c | 50 --
1 f
From: Ashok Reddy Soma
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode should be identical.
During each operation SPI-NOR
This series adds support for Xilinx qspi parallel and stacked memeories.
In parallel mode, the current implementation assumes that a maximum of
two flashes are connected. The QSPI controller splits the data evenly
between both the flashes so, both the flashes that are connected in
parallel mode sh
Hello Simon,
On 30.11.23 21:30, Simon Glass wrote:
> On Wed, 29 Nov 2023 at 12:54, Ahmad Fatoum wrote:
>> On 29.11.23 20:44, Simon Glass wrote:
>>> On Wed, 29 Nov 2023 at 12:33, Ahmad Fatoum wrote:
On 29.11.23 20:27, Simon Glass wrote:
> On Wed, 29 Nov 2023 at 12:15, Ahmad Fatoum
Required to fix the following compile error when building sandbox:
/tmp/cci9ibby.ltrans21.ltrans.o: In function `do_cedit_load':
:(.text+0x601d): undefined reference to `oftree_dispose'
Signed-off-by: Sean Edmond
Reviewed-by: Simon Glass
---
(no changes since v3)
Changes in v3:
- fix compile
There is a preference to use the "ofnode" API for FDT fixups
moving forward. The FDT fixup will usually be for the kernel FDT. To
fixup the kernel FDT with the ofnode API, it's required to set the
OFNODE_MULTI_TREE option.
To ensure existing users of kaslr fdt fixup are not impacted, Let's modif
This patch series creates a common API (fdt_fixup_kaslr_seed()) for
populating the kaslr seed in the DTB. Existing users (kaslrseed,
and ARMv8 sec firmware) have been updated to use this common API.
New functionality has been introduced to populate the kaslr using
the RNG. This can be enabled
Use the newly introduced common API fdt_fixup_kaslr_seed() in the
kaslrseed command.
Signed-off-by: Sean Edmond
Reviewed-by: Simon Glass
---
Changes in v6:
- root_ofnode_from_fdt()->ofnode_root_from_fdt()
- "goto CMD_RET_FAILURE" -> "return CMD_RET_FAILURE"
Changes in v5:
- cast buffer to (u8
From: Dhananjay Phadke
Add support for KASLR seed from the RNG device. Invokes dm_rng_read()
API to read 8-bytes of random bytes. Performs the FDT fixup using event
spy. To enable use CONFIG_KASLR_RNG_SEED
Signed-off-by: Dhananjay Phadke
Signed-off-by: Drew Kluemke
Signed-off-by: Sean Edmond
From: Dhananjay Phadke
fdt_fixup_kaslr_seed() will update given ofnode with random seed value.
Source for random seed can be TPM or RNG driver in u-boot or sec
firmware (ARM).
Signed-off-by: Dhananjay Phadke
Signed-off-by: Sean Edmond
Signed-off-by: Sean Edmond
---
Changes in v6:
- root_ofn
Hi Stephen,
On 30/11/2023 01:13, Stephen Graf wrote:
Is the attached patch file going in the right direction?
yes, thanks, the change itself looks alright, but it needs to be:
- in a separate email, with a descriptive subject, prefixed by [PATCH]
- have the diff inline, not as an attachment (t
> Date: Thu, 30 Nov 2023 23:04:36 +0100
> From: "Janne Grunau"
>
> Hej Mark,
>
> On Thu, Nov 30, 2023, at 21:45, Mark Kettenis wrote:
> >> From: Janne Grunau via B4 Relay
> >> Date: Thu, 30 Nov 2023 13:42:22 +0100
> >>
> >> From: Janne Grunau
> >>
> >> The memory maps for Apple's M2 Pro/Max/
Hi Shantur
I have a few remarks on the architecture.
Up to now, we are supporting
1. Variables on a file
2. Variables on an RPMB
The reason those two are in different files is that we generally
expect to use different bootime services and few differences in
efi_variables_boot_exit_notify() and ef
Hej Mark,
On Thu, Nov 30, 2023, at 21:45, Mark Kettenis wrote:
>> From: Janne Grunau via B4 Relay
>> Date: Thu, 30 Nov 2023 13:42:22 +0100
>>
>> From: Janne Grunau
>>
>> The memory maps for Apple's M2 Pro/Max/Ultra left MMIO space out which
>> was not used by any driver at the time. The displa
gt; + .size = SZ_1G,
> + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
> + PTE_BLOCK_NON_SHARE |
> + PTE_BLOCK_PXN | PTE_BLOCK_UXN
> }, {
> /* I/O */
> .virt = 0x258000,
>
> ---
> base-commit: 43f2873fa98b1da6eb56d756315c7bd7db63db27
> change-id: 20231130-apple_t602x_extend_memmap-c82c522ca8c0
>
> Best regards,
> --
> Janne Grunau
>
>
From: Jakub Klama
Introduce an ability to configure LED and Fiber LEDs found in RTL8211F
PHYs. This is achieved through two optional Device Tree properties:
* rtl,lcr for LED control
* rtl,flcr for Fiber LED control
Signed-off-by: Jakub Klama
Signed-off-by: Artur Rojek
---
drivers/net/phy/re
Add a script which produces a Flat Image Tree (FIT), a single file
containing the built kernel and associated devicetree files.
Compression defaults to gzip which gives a good balance of size and
performance.
The files compress from about 86MB to 24MB using this approach.
The FIT can be used by b
Add a new variable containing a list of possible targets. Mark them as
phony. This matches the approach taken for arch/arm
Signed-off-by: Simon Glass
---
(no changes since v7)
Changes in v7:
- Drop the kbuild tag
Changes in v6:
- Drop the unwanted .gz suffix
arch/arm64/Makefile | 6 +-
1
Flat Image Tree (FIT) is a widely used file format for packaging a
kernel and associated devicetree files[1]. It is not specific to any
one bootloader, as it is supported by U-Boot, coreboot, Linuxboot,
Tianocore and Barebox.
This series adds support for building a FIT as part of the kernel
build.
Hi Masahiro,
On Thu, 30 Nov 2023 at 08:39, Masahiro Yamada wrote:
>
> On Thu, Nov 30, 2023 at 2:22 AM Simon Glass wrote:
> >
> > Add a script which produces a Flat Image Tree (FIT), a single file
> > containing the built kernel and associated devicetree files.
> > Compression defaults to gzip wh
Hi Ahmad,
On Wed, 29 Nov 2023 at 12:54, Ahmad Fatoum wrote:
>
> Hello Simon,
>
> On 29.11.23 20:44, Simon Glass wrote:
> > Hi Ahmad,
> >
> > On Wed, 29 Nov 2023 at 12:33, Ahmad Fatoum wrote:
> >>
> >> On 29.11.23 20:27, Simon Glass wrote:
> >>> On Wed, 29 Nov 2023 at 12:15, Ahmad Fatoum
> >>>
Hi Ahmad,
On Wed, 29 Nov 2023 at 11:35, Ahmad Fatoum wrote:
>
> Hello Simon,
>
> On 29.11.23 18:21, Simon Glass wrote:
> > Add a script which produces a Flat Image Tree (FIT), a single file
> > containing the built kernel and associated devicetree files.
> > Compression defaults to gzip which giv
Linux DTs stuff a value indicating if the USID is a USID or a GSID in the
reg property, the Linux SPMI driver then reads the two address cells
separately. U-boot's dev_read_addr() doesn't know how to handle this, so
use ofnode_read_u32_index() to get just the USID.
The Qcom pmic driver doesn't hav
The core and chnl register ranges were swapped on SDM845. Fix it, and
fetch the register ranges by name instead of by index.
Drop the cosmetic "version" variable and clean up the debug logging.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/qcs404-evb.dts| 7 +++--
arch/arm/dts
Use the upstream gpio-ranges property instead of gpio-count, and drop
the bank-name property for Qualcomm boards.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c.dts | 3 +--
arch/arm/dts/dragonboard820c.dts | 3 +--
arch/arm/dts/qcs404-evb.dts | 2 +-
arch/arm/dts/sdm845.dts
This property is not part of the dt bindings and all boards use the new
gpio-ranges property instead. Drop support for this.
Signed-off-by: Caleb Connolly
---
doc/device-tree-bindings/gpio/pm8916_gpio.txt | 48 ---
drivers/gpio/qcom_pmic_gpio.c | 13 +++---
Upstream uses the gpio-ranges property to define the number of GPIOs,
support for parsing this when gpio-count is unspecified
Additionally, drop the bank-name property as it isn't used in upstream,
and we can just hardcode the bank name instead.
Signed-off-by: Caleb Connolly
---
drivers/gpio/qc
Remove the (now unused) GPIO driver for the power and resin buttons on
the PMIC.
Signed-off-by: Caleb Connolly
---
drivers/gpio/Kconfig | 3 +-
drivers/gpio/qcom_pmic_gpio.c | 104 --
2 files changed, 2 insertions(+), 105 deletions(-)
diff --gi
The PMIC button driver is a much better representation of the hardware
here, adjust the boards to use upstream DT and the PMIC button driver
instead of exposing the buttons as GPIOs and relying on the GPIO-button
driver.
Signed-off-by: Caleb Connolly
---
arch/arm/dts/dragonboard410c-uboot.dtsi
Qualcomm PMICs include a "pon" function which handles two buttons, the
power button and "resin" button (usually volume down). Introduce a new
driver following upstream Linux DT to enable these and map them to Enter
and Down respectively to enable use in boot menus.
Signed-off-by: Caleb Connolly
-
This series addresses some long-standing issues with the SPMI arb
driver, the PMIC, and the PMIC GPIO. It fixes compatibility with
upstream Linux devicetrees, and simplifies pwrkey/resin support by
rewriting the pon driver to be a button driver rather than a GPIO
driver.
Existing users are adjuste
priv->pid is uint32_t, but dev_read_addr() returns a uint64_t on arm64,
with the upper bits being used for error codes. Do error checking before
downcasting to u32 to prevent errors being silently ignored.
Reviewed-by: Sumit Garg
Signed-off-by: Caleb Connolly
---
drivers/gpio/qcom_pmic_gpio.c |
Use counterpart dev_read_* functions instead of fdt* ones. It fixes
checkpatch warnings like this:
WARNING: Use the livetree API (dev_read_...)
#54: FILE: drivers/pinctrl/exynos/pinctrl-exynos.c:137:
pinvals[idx] = fdtdec_get_int(fdt, node,
and also makes it possible to avoid usin
Pull some variables declared in exynos_pinctrl_set_state() into its
loop, to reduce their scope. Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/drivers/pinctrl
All pin related dt properties (pin-function, pin-pud and pin-drv) are
handled in a very similar way. Get rid of that code duplication by
extracting the corresponding data knowledge into an actual data
structure (array), and then just iterating over it.
No functional change, it's a refactoring comm
Get rid of hard-coded register offsets and widths. Instead provide a way
for pinctrl drivers to specify different pin bank register offsets and
widths. This in turn makes it possible to add support for new SoCs that
have registers with offset/width values different than generic ones
already availab
Rework pin_to_bank_base() function to obtain bank data structure by bank
name instead of getting bank base address by pin name, and rename it to
get_bank() to reflect this change. This in turn leads to the extraction
of parse_pin(), so the caller has to use it before calling get_bank().
No functio
Next commits are going to re-design the pin_to_bank_base() function and
its usage in a way that the pin parsing code will be called separately.
Extract it into a separate function first, as a refactoring commit.
No functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinct
Style commit, no functional change.
Signed-off-by: Sam Protsenko
---
drivers/pinctrl/exynos/pinctrl-exynos.c | 3 ++-
drivers/pinctrl/exynos/pinctrl-exynos.h | 2 +-
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/drivers/pinctrl/exynos/pinctrl-exynos.c
b/drivers/pinctrl/exynos/p
Some Exynos SoCs (not supported by pinctrl-exynos driver yet) have
different offsets and widths of pin bank registers (i.e. PIN_CON,
PIN_PUD and PIN_DRV registers). Rework pinctrl-exynos driver so it
allows for different offsets and widths of those registers by adding
the corresponding API. That ma
On 30.11.2023 16:35, Michael Walle wrote:
>> +static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
>> + char *const argv[])
>> +{
> ..
>
>> + printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
>
> Please note, that with current SPI-NOR flas
On Thu, Nov 30, 2023 at 09:50:36AM +0200, Svyatoslav Ryhel wrote:
> Dear Tom,
>
> The following changes since commit acae7eb5fe063dcfe2dbdb1e1804cf3e12cc2f3f:
>
> i2c: Bugfix in i2c_get_chip_by_phandle() (2023-11-27 18:54:56 -0500)
>
> are available in the Git repository at:
>
> https://so
On Thu, Nov 30, 2023 at 2:22 AM Simon Glass wrote:
>
> Add a script which produces a Flat Image Tree (FIT), a single file
> containing the built kernel and associated devicetree files.
> Compression defaults to gzip which gives a good balance of size and
> performance.
>
> The files compress from
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Add maintainership for new J784S4 files added.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/MAINTAINERS | 25 +
1 file changed, 25 insertions(+)
create mode 100644 board/ti/j784s4/MAINTAINERS
diff --git a/board/ti/j784s
On Thu, Nov 30, 2023 at 5:26 PM Nicolas Schier wrote:
>
> Simon,
>
> thanks for the patch! Below are some nitpicks and bike-shedding
> questions.
>
> On Wed 29 Nov 2023 10:21:53 GMT, Simon Glass wrote:
> > Add a script which produces a Flat Image Tree (FIT), a single file
> > containing the built
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Hari Nagalla
[ add binman and ddr dtsi files ]
Signed-off-by: Neha Malcom Francis
Signed-off-by: Dasnavis Sabiya
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Add board-cfg, rm-cfg, pm-cfg, sec-cfg, tifs-rm-cfg yaml for buidling
u-boot sysfw data.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/board-cfg.yaml | 37 +
board/ti/j784s4/pm-cfg.yaml | 13 +
board/ti/j784s4/rm-cfg.yaml | 3058 +
On 11/30/23 5:55 AM, Apurva Nandan wrote:
Add board files for J784S4 EVM.
Signed-off-by: Hari Nagalla
[ add env and board specific yaml files for binman ]
Signed-off-by: Neha Malcom Francis
[ cleaned up the env files ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off
The base address of extended DDR does not change across the K3 family.
Setting this per SoC is not needed. Remove this definition to help
remove the last bits from K3 include/configs/*.h files.
Signed-off-by: Andrew Davis
---
board/ti/am65x/evm.c | 4 ++--
board/ti/j721e/evm.c |
Hi Niek,
On 11/29/23 18:58, niek.nooij...@omron.com wrote:
Hi Fabio
I'm using the socfpga_cyclone5 with the designwire_spi driver.
I added the TPM to the devicetree as so:
&spi0 {
status = "okay";
num-cs = <2>;
mram0@0 {
compatible = "spi-dev";
reg = <0
Display the STMicroelectronics logo with features VIDEO_LOGO and
SPLASH_SCREEN on stm32f469-disco board.
Signed-off-by: Dario Binacchi
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag to patches 1, 2 and 3 of the series.
- Fix frame buffer allocation for stm32f469 discovery board.
c
Add support to Orise Tech OTM8009A display on stm32f469-disco board.
It was necessary to retrieve the framebuffer address from the device tree
because the address returned by the video-uclass driver pointed to a memory
area that was not usable.
Furthermore, unlike Linux, the DSI driver requires t
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle node
As described in [1], the "clocks" property contains "a phandle to the
clock device node, an index selecting between gated clocks (0) and other
clocks (1), and an index specifying the clock to use." The current version
of the clock driver, unlike the kernel, is currently able to properly
handle node
Sync the devicetree with linux 6.5 for stm32f746-disco board.
Signed-off-by: Dario Binacchi
Reviewed-by: Patrice Chotard
---
Changes in v2:
- Add Patrice Chotard's Reviewed-by tag.
arch/arm/dts/stm32f469-disco.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/a
The series adds support for the Orise Tech OTM8009A display on the
stm32f469-disco board. Substantial differences in the drivers for clock
management, LTDC and DSI compared to Linux, made it necessary to modify
the device tree. These changes were made in stm32f469-disco-uboot.dtsi to
avoid altering
On Thu, Nov 30, 2023 at 01:02:25PM +0530, Sumit Garg wrote:
> On Wed, 29 Nov 2023 at 22:06, Neil Armstrong
> wrote:
> >
> > On 29/11/2023 16:34, Caleb Connolly wrote:
> > >
> > >
> > > On 23/11/2023 07:04, Sumit Garg wrote:
> > >> On Wed, 22 Nov 2023 at 21:34, Caleb Connolly
> > >> wrote:
> > >
> Since with this change, we don't need to embed FDT blob in the u-boot
> binary, so I was thinking if we really need to import DTs from Linux
> for different platforms and then play a catchup game?
>
> For now, yes.
But why? Is there any value added by l
Simon,
thanks for the patch! Below are some nitpicks and bike-shedding
questions.
On Wed 29 Nov 2023 10:21:53 GMT, Simon Glass wrote:
> Add a script which produces a Flat Image Tree (FIT), a single file
> containing the built kernel and associated devicetree files.
> Compression defaults to gzi
Hi Fabio
I'm using the socfpga_cyclone5 with the designwire_spi driver.
I added the TPM to the devicetree as so:
&spi0 {
status = "okay";
num-cs = <2>;
mram0@0 {
compatible = "spi-dev";
reg = <0>;
spi-max-frequency = <100>;
};
t
Signed-off-by: Arseniy Krasnov
---
arch/arm/dts/meson-axg.dtsi | 35 +++
1 file changed, 35 insertions(+)
diff --git a/arch/arm/dts/meson-axg.dtsi b/arch/arm/dts/meson-axg.dtsi
index 3f5254eeb4..c01ace3ff1 100644
--- a/arch/arm/dts/meson-axg.dtsi
+++ b/arch/arm/dt
Introduce the basic j784s4 SoC dts from the v6.7-rc1 tag of the
linux kernel.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile |1 +
arch/arm/dts/k3-j784s4-evm.dts | 981 +++
arch/arm/dts/k3-j784s4-main.dtsi | 2068 ++
Add access to OTP region. It supports info, dump, write and lock
operations.
Signed-off-by: Arseniy Krasnov
---
cmd/Kconfig | 1 +
cmd/mtd.c | 224
2 files changed, 225 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 90e4ef93e0
Support for OTP area access on MX30LFxG18AC chip series.
Signed-off-by: Arseniy Krasnov
---
drivers/mtd/nand/raw/nand_macronix.c | 170 +++
1 file changed, 170 insertions(+)
diff --git a/drivers/mtd/nand/raw/nand_macronix.c
b/drivers/mtd/nand/raw/nand_macronix.c
index d
Basic support for Amlogic Meson NAND controller on AXG.
Signed-off-by: Arseniy Krasnov
---
drivers/mtd/nand/raw/Kconfig |9 +
drivers/mtd/nand/raw/Makefile |1 +
drivers/mtd/nand/raw/meson_nand.c | 1231 +
3 files changed, 1241 insertions(+)
create m
Hi,
We are using u-boot and until now we are using a single env storage on the eMMC.
We want to change to using a redundant environment, and the way to do that is
well documented (thanks for that).
The problem we are facing is transitioning from one single to redundant, as the
format of the
> On 13:40-20231128, Vishal Mahaveer wrote:
> > This patch series brings in the latest board configurations for
> > am62 and am62a device.
> >
> > Patch "board: ti: am62x/am62ax: Update virtual interrupt allocations
> > in board config" is needed for booting with the latest TIFS and DM
> > firmware
+static int do_mtd_otp_write(struct cmd_tbl *cmdtp, int flag, int argc,
+ char *const argv[])
+{
..
+ printf("Caution! OTP data bits can't be erased! Continue (y/n)?\n");
Please note, that with current SPI-NOR flashes this is not true and
there is usually some
On Thu, Nov 30, 2023 at 10:14 AM Maxim Uvarov wrote:
> I will test that. smsc95xx_eth included in some CI tests and it worked. So
> some differences on real hardware...
> Log says that a ping packet was sent, but no packet on rx.
> Might be the start function of smsc95xx_eth called wrongly
On Thu, 30 Nov 2023 at 19:00, Fabio Estevam wrote:
> Hi Maxim,
>
> On Thu, Nov 30, 2023 at 5:39 AM Maxim Uvarov
> wrote:
>
> > If networking for some reason doesn't work on that board (I tested only
> virtual board). Please try to compile with:
>
> Could you also try on a real board?
>
> Tom tes
On Thu, 30 Nov 2023 at 17:09, Peter Robinson wrote:
> Hi Maxim,
>
> > Please find updated version of lwip patches. Changes are in the
> > changelog bellow.
> >
> > Thank you,
> > Maxim.
> >
> > changelog:
> > v11: - v11 is mosly respin of v10 patches with CI error fixes.
> >
Hi Maxim,
On Thu, Nov 30, 2023 at 5:39 AM Maxim Uvarov wrote:
> If networking for some reason doesn't work on that board (I tested only
> virtual board). Please try to compile with:
Could you also try on a real board?
Tom tested on a Raspberry Pi3 and it failed too:
https://lore.kernel.org/u
d756315c7bd7db63db27
change-id: 20231130-apple_t602x_extend_memmap-c82c522ca8c0
Best regards,
--
Janne Grunau
Since we have boards using the driver model or not for i2c, use abstraction
function to probe the i2c, check the EEPROM and read from EEPROM.
Signed-off-by: Enrico Leto
---
board/siemens/common/board.c | 50 --
board/siemens/common/board.h | 3 ++
board/siemens
Move the I2C and EEPROM address definitions in common board header.
Reviewed-by: Alexander Sverdlin
Signed-off-by: Enrico Leto
---
board/siemens/capricorn/board.c | 5 ++---
board/siemens/common/board.c | 6 +++---
board/siemens/common/board.h | 21 +
board/sie
Adding the capricorn board family some parts diverge from draco family.
The switches used were not pertinent and need to be enhanced for each new
board of the capricorn family. Replace them through the SOC name 'AM33XX'
and 'IMX8'.
Signed-off-by: Enrico Leto
---
board/siemens/common/factoryset.c
Many includes were not removed when code parts were moved or removed.
Signed-off-by: Enrico Leto
---
board/siemens/common/board.c | 24 +++-
board/siemens/common/factoryset.c | 12 ++--
board/siemens/draco/board.c | 23 +--
board/siemens
The common folder was initialially created for the common parts of the
products based on draco-am355x board family. These are the product
lines 'pxm2', 'rut' and the base line named 'draco'!
Adding the new capricorn-imx8 board family, common was enhanced without
cleanup.
Move all am355x specifics
Add support for driver model where EEPROM data are read in draco board.
Reviewed-by: Alexander Sverdlin
Signed-off-by: Enrico Leto
---
configs/draco-etamin_defconfig | 4 +++-
configs/draco-rastaban_defconfig | 4 +++-
configs/draco-thuban_defconfig | 4 +++-
3 files changed, 9 insertions(+
This serie depends on the serie:
[PATCH 0/6] siemens,am335x: clean up the draco board family
The common folder was initialially created for the common parts of
the products based on draco-am355x board family. We have the
product lines 'pxm2', 'rut' and the base line unfortunate
It adds the ATCWDT200 support for Andes AE350 platform.
It also enables wdt command support.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
configs/ae350_rv32_defconfig | 4
configs/ae350_rv32_spl_defconfig | 4
configs/ae350_rv32_spl_xip_defconfig | 4
configs/ae
This patch adds an implementation of the Andes watchdog ATCWDT200 driver.
Signed-off-by: CL Wang
Signed-off-by: Randolph
---
drivers/watchdog/Kconfig | 6 +
drivers/watchdog/Makefile| 1 +
drivers/watchdog/atcwdt200_wdt.c | 220 +++
3 files change
Add maintainership for new J784S4 files added.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/MAINTAINERS | 25 +
1 file changed, 25 insertions(+)
create mode 100644 board/ti/j784s4/MAINTAINERS
diff --git a/board/ti/j784s4/MAINTAINERS b/board/ti/j784s4/MAINTAINERS
new
TI K3 J784S4 and AM69 are new additions to the K3 SoC family.
Add documentation about the J784S4 EVM and AM69 SK.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
doc/board/ti/j784s4_evm.rst | 303
doc/board/ti/k3.rst | 1 +
2 files
From: Dasnavis Sabiya
Add config fragments for am69_sk A72 and R5 configuration.
This applies on to:
j784s4_evm_a72_defconfig -> am69_sk_a72.config
j784s4_evm_r5_defconfig -> am69_sk_r5.config
The usage model (with the fragment) would be:
make j784s4_evm_a72_defconfig am69_sk_a72.config
make
O
Add defconfigs for building R5 U-Boot SPL and A72 U-Boot.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
configs/j784s4_evm_a72_defconfig | 180 +++
configs/j784s4_evm_r5_defconfig | 163
2 files changed, 343 insertions(+)
From: Dasnavis Sabiya
Introduce the base dts files needed for u-boot or to augment the linux
dtbs for use in the u-boot-spl and u-boot binaries.
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/k3-am69-r5-sk.dts | 1
Add env file with necessary boot variables.
Signed-off-by: Apurva Nandan
---
board/ti/j784s4/j784s4.env | 19 +++
1 file changed, 19 insertions(+)
create mode 100644 board/ti/j784s4/j784s4.env
diff --git a/board/ti/j784s4/j784s4.env b/board/ti/j784s4/j784s4.env
new file mode 10
Add board files for J784S4 EVM.
Signed-off-by: Hari Nagalla
[ add env and board specific yaml files for binman ]
Signed-off-by: Neha Malcom Francis
[ cleaned up the env files ]
Signed-off-by: Manorit Chawdhry
Signed-off-by: Dasnavis Sabiya
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/Kc
Add support for DMA in J784S4 SoC.
Signed-off-by: Jayesh Choudhary
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
drivers/dma/ti/Makefile | 1 +
drivers/dma/ti/k3-psil-j784s4.c | 166 ++
drivers/dma/ti/k3-psil-priv.h | 1 +
Add clk and device data which can be used by respective drivers
to configure clocks and PSC.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/r5/j784s4/Makefile| 7 +
arch/arm/mach-k3/r5/j784s4/clk-data.c | 428 +
arch/arm/mach-k3/r5/j
Add support for J784S4 SoC Identification.
Signed-off-by: Hari Nagalla
Signed-off-by: Apurva Nandan
---
arch/arm/mach-k3/include/mach/hardware.h | 1 +
drivers/soc/soc_ti_k3.c | 3 +++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/hardware.h
b/ar
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