> -Original Message-
> From: Fabio Estevam
> Sent: Wednesday, November 1, 2023 1:09 AM
> To: Marek Vasut
> Cc: u-boot@lists.denx.de; Jaehoon Chung ; Abdellatif
> El Khlifi
> ; Heinrich Schuchardt ;
> Ilias Apalodimas
> ; Ramon Fried ; Roger
> Knecht ; Sean
> Edmond ; Simon Glass ; T
> -Original Message-
> From: U-Boot On Behalf Of Jaehoon Chung
> Sent: Wednesday, November 1, 2023 10:09 AM
> To: 'Henrik Grimler' ; 'Sean Anderson'
>
> Cc: u-boot@lists.denx.de; 'Rayagonda Kokatanur'
> ; 'Bharat Kumar
> Reddy Gooty'
> Subject: RE: [PATCH] mmc: sdhci: Rework SDHCI_Q
> -Original Message-
> From: U-Boot On Behalf Of Jaehoon Chung
> Sent: Tuesday, October 31, 2023 3:09 PM
> To: Bin Meng ; Peng Fan
> Cc: u-boot@lists.denx.de
> Subject: Re: [PATCH] mmc: pci: Drop the superfluous cast
>
> On 10/11/23 20:00, Bin Meng wrote:
> > dm_pci_map_bar() return a
> -Original Message-
> From: U-Boot On Behalf Of Jaehoon Chung
> Sent: Tuesday, October 31, 2023 2:04 PM
> To: Oleksandr Suvorov ; u-boot@lists.denx.de
> Cc: Peng Fan
> Subject: Re: [PATCH] mmc: spl: select SPL_BLK for SPL_DM_MMC
>
> On 8/24/23 00:45, Oleksandr Suvorov wrote:
> > mmc_
On Tue, Oct 31, 2023 at 12:37:20AM -0500, Samuel Holland wrote:
> Some RISC-V CPUs, such as the T-HEAD XuanTie series, have a
> vendor-specific way to invalidate a portion of the instruction cache.
> Allow them to override invalidate_icache_range().
>
> Signed-off-by: Samuel Holland
> ---
>
> a
On Tue, Oct 31, 2023 at 12:35:41AM -0500, Samuel Holland wrote:
> This is required on CPUs which always operate in CLIC mode, such as the
> T-HEAD E906 and E907. Per the CLIC specification: "In this mode, the
> trap vector base address held in mtvec is constrained to be aligned on a
> 64-byte or la
On Tue, Oct 31, 2023 at 12:32:12AM -0500, Samuel Holland wrote:
> Clean things up for the next time somebody adds a target.
>
> Signed-off-by: Samuel Holland
> ---
>
> arch/riscv/Kconfig | 18 +-
> 1 file changed, 9 insertions(+), 9 deletions(-)
Reviewed-by: Leo Yu-Chi Liang
Enable the initial kria SOM specific configurations like pinctrl,
pinconf etc. Also add the environment file.
Signed-off-by: Venkatesh Yadav Abbarapu
---
Changes in v2:
- Updated the CONFIG_ENV_OFFSET_REDUND
- Updated the CONFIG_SF_DEFAULT_SPEED to 3000
- Enabled the CONFIG_VIDEO_ZYNQMP_DPSUB
Hi Simon:
Nice to meet you.
The u-boot I used is based on v2023.04 tagged version.
Layerscape LX2160A RDB board has four SATA controllers.
Based on LX2160A RDB board and two or more SATA disks connected.
I encounter one "scsi scan" problem.
After the first SATA disk is detected and probed properly
> -Original Message-
> From: Jaehoon Chung
> Sent: Wednesday, November 1, 2023 9:52 AM
> To: 'Chanho Park' ; 'Sughosh Ganu'
> ; 'Heinrich Schuchardt' ;
> 'Rick Chen' ; 'Leo' ; u-
> b...@lists.denx.de
> Subject: RE: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
>
>
>
> > -Origin
Hi,
> -Original Message-
> From: Henrik Grimler
> Sent: Sunday, October 29, 2023 5:31 AM
> To: Sean Anderson
> Cc: u-boot@lists.denx.de; Jaehoon Chung ; Rayagonda
> Kokatanur
> ; Bharat Kumar Reddy Gooty
>
> Subject: Re: [PATCH] mmc: sdhci: Rework SDHCI_QUIRK_BROKEN_R1B
>
> Hi Sean,
> -Original Message-
> From: U-Boot On Behalf Of Chanho Park
> Sent: Wednesday, November 1, 2023 8:55 AM
> To: Sughosh Ganu ; Heinrich Schuchardt
> ; Rick Chen
> ; Leo ; u-boot@lists.denx.de
> Cc: Chanho Park
> Subject: [PATCH v2 3/5] rng: Add StarFive JH7110 RNG driver
>
> Adds to s
Hi Simon,
On Tue, Oct 31, 2023 at 12:00 PM Tony Dinh wrote:
>
> Hi Simon,
>
> On Tue, Oct 31, 2023 at 11:50 AM Simon Glass wrote:
> >
> > Hi Tony,
> >
> > Sorry I cannot reply to the patch[1].
> >
> > Can you please send the console trace for this situation? I don't want
> > to ignore errors com
This imports mmio functions from Linux's arch/riscv/include/asm/mmio.h
to use read/write[b|w|l|q]_relaxed functions.
Signed-off-by: Chanho Park
---
arch/riscv/include/asm/io.h | 45 +
1 file changed, 45 insertions(+)
diff --git a/arch/riscv/include/asm/io.h b
Enables JH7110 RNG driver to visionfive2 board.
Signed-off-by: Chanho Park
Reviewed-by: Heinrich Schuchardt
---
configs/starfive_visionfive2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig
b/configs/starfive_visionfive2_defconfig
index b21
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park
---
drivers/rng/Kconfig | 6 +
drivers/rng/Makefile | 1 +
dr
Adds jh7110 trng device tree node.
Signed-off-by: Chanho Park
---
arch/riscv/dts/jh7110.dtsi | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/dts/jh7110.dtsi b/arch/riscv/dts/jh7110.dtsi
index ec237a46ffba..13c47f7caa36 100644
--- a/arch/riscv/dts/jh7110.dtsi
+++ b/arch
Add STGCLK_SEC_HCLK and STGCLK_SEC_MISCAHB clocks for JH7110 TRNG
device.
Signed-off-by: Chanho Park
---
drivers/clk/starfive/clk-jh7110.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/starfive/clk-jh7110.c
b/drivers/clk/starfive/clk-jh7110.c
index 31aaf3340f94..a8
This patchset adds to support StarFive JH7110 TRNG driver. Due to lack
of readl_relaxed API, the first patch tries to import the
APIs(read/write_relaxed) from Linux kernel's implementation. The second
patch adds the missing security clocks which are required by the trng
IP.
This IP can support 128
> -Original Message-
> From: Heinrich Schuchardt
> Sent: Wednesday, November 1, 2023 6:18 AM
> To: Chanho Park
> Cc: Sughosh Ganu ; Rick Chen ;
> Leo ; u-boot@lists.denx.de
> Subject: Re: [PATCH 3/5] rng: Add StarFive JH7110 RNG driver
>
> On 10/30/23 09:32, Chanho Park wrote:
> > Adds t
Hello ,
Can I know if I could generate uboot env file in binary format as part of my
build process ?
Currently it generate as a text file .
Regards
Simon
Sent from my iPhone
Hi,
> -Original Message-
> From: Tom Rini
> Sent: Tuesday, October 31, 2023 10:01 PM
> To: Jaehoon Chung
> Cc: u-boot@lists.denx.de; ycli...@andestech.com;
> yanhong.w...@starfivetech.com;
> minda.c...@starfivetech.com; xingyu...@starfivetech.com
> Subject: Re: [PATCH 1/2] riscv: dts: j
On Tue, Sep 26, 2023 at 11:23 AM Linus Walleij wrote:
> This adds support for the Inteno XG6846 board based on the
> Broadcom MIPS 6328 SoC.
>
> The default boot will read a uImage from flash and boot it.
>
> Reviewed-by: Daniel Schwierzeck
> Signed-off-by: Linus Walleij
> ---
> ChangeLog v1->v
On 10/30/23 09:32, Chanho Park wrote:
Enables JH7110 RNG driver to visionfive2 board.
Signed-off-by: Chanho Park
Reviewed-by: Heinrich Schuchardt
---
configs/starfive_visionfive2_defconfig | 2 ++
1 file changed, 2 insertions(+)
diff --git a/configs/starfive_visionfive2_defconfig
b/co
On 10/30/23 09:32, Chanho Park wrote:
Adds to support JH7110 TRNG driver which is based on linux kernel's
jh7110-trng.c. This can support to generate 256-bit random numbers and
128-bit but this makes 256-bit default for convenience.
Signed-off-by: Chanho Park
---
drivers/rng/Kconfig |
On Tue, Oct 31, 2023 at 12:26 PM Tony Dinh wrote:
>
> Hi Simon,
>
> On Mon, Oct 30, 2023 at 12:47 PM Tony Dinh wrote:
> >
> > During scanning for the next bootdev, if bootdev_next_prio() encounters
> > a device error (e.g. ENOSYS), let it continue scanning the next devices,
> > not stopping prema
Hi Simon,
On Mon, Oct 30, 2023 at 12:47 PM Tony Dinh wrote:
>
> During scanning for the next bootdev, if bootdev_next_prio() encounters
> a device error (e.g. ENOSYS), let it continue scanning the next devices,
> not stopping prematurely.
>
> Background:
>
> During scanning for bootflows, it's po
Hi Simon,
On Tue, Oct 31, 2023 at 11:50 AM Simon Glass wrote:
>
> Hi Tony,
>
> Sorry I cannot reply to the patch[1].
>
> Can you please send the console trace for this situation? I don't want
> to ignore errors completely, so wonder if there is a special error
> code which could be produced when
Hi Tony,
Sorry I cannot reply to the patch[1].
Can you please send the console trace for this situation? I don't want
to ignore errors completely, so wonder if there is a special error
code which could be produced when a device is missing?
Regards,
Simon
[1]
https://patchwork.ozlabs.org/projec
Update maintainers for Tegra SoC platform. Include device trees
and drivers which contain tegra in the name.
Signed-off-by: Svyatoslav Ryhel
---
MAINTAINERS | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index cde778bc4d..f07386dc77 100644
--
I would like to volunteer as Tegra SOC co-maintainer.
Svyatoslav Ryhel (1):
MAINTAINERS: Step up as co-maintainer of Tegra SOC platform
MAINTAINERS | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
--
2.39.2
On Thu, Oct 26, 2023 at 01:50:51PM +0100, abdellatif.elkhl...@arm.com wrote:
> From: Emekcan Aras
>
> enable PSCI reset used for the system reset
>
> Even though Corstone-1000 does not implement the entire PSCI APIs,
> it relies on PSCI reset interface for the system reset.
>
> Signed-off-by:
On Thu, Oct 26, 2023 at 01:50:50PM +0100, abdellatif.elkhl...@arm.com wrote:
> From: Abdellatif El Khlifi
>
> enable distro_bootcmd
>
> Signed-off-by: Abdellatif El Khlifi
> Signed-off-by: Rui Miguel Silva
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
On Thu, Oct 26, 2023 at 01:50:49PM +0100, abdellatif.elkhl...@arm.com wrote:
> From: Abdellatif El Khlifi
>
> unzip the kernel before executing it
>
> The Corstone-1000 kernel has become too large to fit in the available
> storage. Switching to a compressed kernel avoids the problem, but
> req
On Wed, Oct 25, 2023 at 03:51:03PM +0900, Masahisa Kojima wrote:
> Current documentation limits the firmware size to 1.5MB.
> When the fTPM and StandaloneMM-based RPMB secure storage is
> enabled, firmware size is bigger than that size.
> Let's specify the A/B update bank size(4MB) for flash
> raw
On Wed, Oct 25, 2023 at 03:51:02PM +0900, Masahisa Kojima wrote:
> v2023.07 is the last version supporting old NOR flash layout
> by default. The later versions of U-Boot, Developerbox is
> configured to enable A/B update and new NOR Flash layout
> by default.
> This commit updates the documentati
On Wed, Oct 25, 2023 at 03:51:01PM +0900, Masahisa Kojima wrote:
> There are two kinds of NOR flash layout for the Developerbox.
> Capsule update for the old layout is no longer available since
> it has small capacity for secure world images and can not
> house the TA such as fTPM.
> This commit r
On Mon, Oct 23, 2023 at 08:35:46AM -0500, Vishal Mahaveer wrote:
> PLL calibration needs to be enabled when operating in non fractional
> mode. Add the sequence to do a fast calibration when using PLL
> in this mode.
>
> Signed-off-by: Vishal Mahaveer
Applied to u-boot/master, thanks!
--
Tom
On Mon, Oct 23, 2023 at 03:02:25PM +0800, Jim Liu wrote:
> disable this config to improve flash program time
>
> Signed-off-by: Jim Liu
>
> Changes for v2:
>- add commit message
> Changes for v3:
>- no change
> Changes for v4:
>- no change
Applied to u-boot/master, thanks!
--
Tom
On Mon, Oct 23, 2023 at 03:02:24PM +0800, Jim Liu wrote:
> 1. Fix incorrect ram size of 4GB dram with ECC enabled
> 2. Fix wrong place to set dram bank size
>- The dram bank size should be set in dram_init_banksize
>- Dram_init should not access gd->bd because the board info
> struct
On Mon, Oct 23, 2023 at 03:02:23PM +0800, Jim Liu wrote:
> Add uart baud rate table to arbel(npcm8xx) and poleg(npcm7xx)
>
> Signed-off-by: Jim Liu
>
> Changes for v2:
>- Add commit message
> Changes for v3:
>- Modify CONFIG_SYS_BAUDRATE_TABLE
> Changes for v4:
>- No change
Applied
On Mon, Oct 23, 2023 at 03:02:22PM +0800, Jim Liu wrote:
> GPIO function name is needed in the debug log
>
> Signed-off-by: Jim Liu
>
> Changes for v2:
>- add commit message
> Changes for v3:
>- no change
> Changes for v4:
>- no change
Applied to u-boot/master, thanks!
--
Tom
s
On paź 31, 2023 17:49, Jonas Karlman wrote:
> On 2023-10-31 17:13, Slawomir Stepien wrote:
> > Flashing this image to the on-board flash is useful when you want to
> > start Linux from a medium (e.g. nvme) without flashing u-boot elements
> > to it.
> >
> > Signed-off-by: Slawomir Stepien
> > ---
Flashing this image to the on-board flash is useful when you want to
start Linux from a medium (e.g. nvme) without flashing u-boot elements
to it.
Signed-off-by: Slawomir Stepien
---
configs/orangepi-5-plus-rk3588_defconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/configs/orangepi-5-p
Mark the flash@0 as BROM_BOOTSOURCE_SPINAND.
Fixes use of same-as-spl in u-boot,spl-boot-order prop on Orange Pi 5
Plus.
Signed-off-by: Slawomir Stepien
---
arch/arm/mach-rockchip/rk3588/rk3588.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c
b/arch/a
On 2023-10-31 17:13, Slawomir Stepien wrote:
> Flashing this image to the on-board flash is useful when you want to
> start Linux from a medium (e.g. nvme) without flashing u-boot elements
> to it.
>
> Signed-off-by: Slawomir Stepien
> ---
> configs/orangepi-5-plus-rk3588_defconfig | 1 +
> 1 fi
On 2023-10-31 17:13, Slawomir Stepien wrote:
> Mark the flash@0 as BROM_BOOTSOURCE_SPINAND.
> Fixes use of same-as-spl in u-boot,spl-boot-order prop on Orange Pi 5
> Plus.
>
> Signed-off-by: Slawomir Stepien
> ---
> arch/arm/mach-rockchip/rk3588/rk3588.c | 1 +
> 1 file changed, 1 insertion(+)
>
On Tue, Oct 31, 2023 at 9:20 AM Marek Vasut wrote:
>
> Add extension to the 'mmc' command to read out the card registers.
> Currently, only the eMMC OCR/CID/CSD/EXTCSD/RCA/DSR register are
> supported. A register value can either be displayed or read into
> an environment variable.
>
> Tested-by:
On 31/10/2023 16:19, Caleb Connolly wrote:
As Ramon has been inactive for some time now, add myself and Neil
Armstrong to maintain Qualcomm efforts going forwards.
Signed-off-by: Caleb Connolly
---
I greatly appreciate the work done by Ramon Fried in keeping Qualcomm
support alive in U-Boot the
Hi Rob,
On Mon, 16 Oct 2023 at 15:54, Simon Glass wrote:
>
> Hi Rob,
>
> On Mon, 16 Oct 2023 at 10:50, Rob Herring wrote:
> >
> > On Fri, Oct 13, 2023 at 4:09 PM Simon Glass wrote:
> > >
> > > Hi Rob,
> > >
> > > On Fri, 13 Oct 2023 at 13:42, Rob Herring wrote:
> > > >
> > > > On Fri, Oct 6, 2
Thank you, I understand.
Regards,
Xiang W
Heinrich Schuchardt 于2023年10月31日周二 20:09写道：
>
> On 10/31/23 09:53, Xiang W wrote:
> > setjmp can be called in set_resume.
>
> Unfortunately this is not possible. A longjmp buffer only stores
> register values and not the stack content.
>
> Let's assume t
As Ramon has been inactive for some time now, add myself and Neil
Armstrong to maintain Qualcomm efforts going forwards.
Signed-off-by: Caleb Connolly
---
I greatly appreciate the work done by Ramon Fried in keeping Qualcomm
support alive in U-Boot the last few years. However it's clear that
he h
On Wed, Oct 25, 2023 at 6:13 PM Adam Ford wrote:
>
> The ENV size and offset were changed to different
> values in Beacon's downstream release. Change them to the
> same values as the downstream for consistent behavior.
>
> Signed-off-by: Adam Ford
Marek,
I know you had some feedback on other
Hi,
On Mon, 20 Jun 2022 20:13:54 +0900, Jaehoon Chung wrote:
> Add CONFIG_DFU_NAME_MAX_SIZE to change the proper size.
> If name is longer than default size, it can do wrong behavior during updating
> image. So it need to change the proper maximum size.
>
> This patch is proviced the solution to
Hi Jaehoon,
Thank you for your patch.
On lun., juin 20, 2022 at 20:13, Jaehoon Chung wrote:
> Add CONFIG_DFU_NAME_MAX_SIZE to change the proper size.
> If name is longer than default size, it can do wrong behavior during updating
> image. So it need to change the proper maximum size.
>
> This p
SMMU is disabled by default and not all masters can be enabled at the same
time because of limited number of entries. That's why comment all iommu
properties but keep them for reference in DT. In XEN case they should be
added back and Xen should have SMMU enabled by default.
Signed-off-by: Michal
The "MSM" naming hasn't been correct for quite a while now, in line
with Linux lets rename all these msm_* functions to qcom_* as well as
ensure namespacing is consistent across the pinctrl and GPIO drivers.
Signed-off-by: Caleb Connolly
---
configs/dragonboard410c_defconfig| 2 +-
conf
Drop the duplicated pinctrl-snapdragon driver from mach-ipq40xx and add
it to drivers/pinctrl/qcom.
Signed-off-by: Caleb Connolly
---
arch/arm/Kconfig | 1 +
arch/arm/mach-ipq40xx/Makefile | 8 -
arch/arm/mach-ipq40xx/pinctrl-snapdragon.c
Replaces the uses of "unsigned" with "unsigned int".
Signed-off-by: Caleb Connolly
---
drivers/gpio/msm_gpio.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c
index 7a09abdafb2e..7d01fecf46f2 100644
--- a/drivers/gpio/
Some Qualcomm boards feature reserved ranges of pins which are protected
by firmware. Attempting to read or write any registers associated with
these pins results the board resetting.
Add support for parsing these ranges from devicetree and ensure that the
pinctrl and GPIO drivers don't try to int
Move the Qualcomm pinctrl drivers out of mach-snapdragon and over to the
rest of the pinctrl drivers, adjust the drivers so that support for each
platform can be enabled/disabled individually and introduce platform
specific configuration options.
Signed-off-by: Caleb Connolly
---
arch/arm/mach-s
The pinctrl and GPIO drivers are currently heavily incompatible with
upstream. Most Qualcomm pinctrl blocks feature "tiles" of pins, each at
it's own address. Introduce support for these by allowing the soc driver
to specify per-pin register offsets similarly to the Linux driver.
Adjust the GPIO d
This series moves the Qualcomm pinctrl drivers from mach-snapdragon and
mach-ipq40xx to drivers/pinctrl/qcom. It then makes the necessary changes
to enable compatibility with Linux DTs.
The pinctrl hardware on most Qualcomm platforms is made up of "tiles",
these are just banks of pins at different
Hi Tom,
> > > > >
> > > > > *** CID 464361: Control flow issues (DEADCODE)
> > > > > /drivers/firmware/arm-ffa/arm-ffa-uclass.c: 148 in
> > > > > ffa_print_error_log()
> > > > > 142
> > > >
Hi,
On Sun, 29 Oct 2023 23:37:22 +0100, Marek Vasut wrote:
> Add support for exposing the whole mmc device by setting the 'size'
> parameter to 0. This can be useful in case it is not clear what the
> total device size is up front. Update the documentation accordingly.
>
>
Thanks, Applied to ht
On Tue, Oct 31, 2023 at 06:58:06PM +0530, Nitin Yadav wrote:
> AM62 SIP has 512MB RAM. But the top of the RAM is reserved for
> TF-A and OPTEE. U-Boot relocating there would cause overwriting
> of these reserved regions. Fix this by limit U-Boot to first
> 64MB of RAM for all boards with 512MB.
>
Hi,
On Mon, 25 Sep 2023 12:37:15 +0200, Wojciech Nizinski wrote:
> genimage create android-sparse file with CRC32 chunk at end. When
> U-Boot's fastboot receives this chunk it returns error message:
> `Fail Bogus chunk size for chunk type Dont Care`
>
> According to reference implementation of An
Add documentation for PHYTEC phyCORE-AM62x SoM.
Signed-off-by: Wadim Egorov
---
doc/board/phytec/index.rst | 1 +
doc/board/phytec/phycore-am62x.rst | 125 +
doc/board/ti/k3.rst| 1 +
3 files changed, 127 insertions(+)
create mode 100644 d
Add link for AM62SIP SK in platform information. AM62SIP SK
has config fragment for R5 SPL to build U-boot, Adding
information to update UBOOT_CFG_CORTEXR with am62sip fragment
over am62x defconfig.
Signed-off-by: Nitin Yadav
---
doc/board/ti/am62x_sk.rst | 7 +++
1 file changed, 7 insertion
Add config fragments am62xsip_sk_r5.config for R5 configuration.
Signed-off-by: Nitin Yadav
---
board/ti/am62x/am62xsip_sk_r5.config | 5 +
1 file changed, 5 insertions(+)
create mode 100644 board/ti/am62x/am62xsip_sk_r5.config
diff --git a/board/ti/am62x/am62xsip_sk_r5.config
b/board/ti/
When DDR ECC is off (ecc_reserved_space = 0) k3_ddrss_ddr_fdt_fixup()
doesn't update the DDR size in the memory node of DT. Fix this by
dropping check for ecc_reserved_space to be non zero.
This allows R5 SPL to fixup A53 SPL DT with right DDR size as discovered
during DDR init or based on R5 SPL
AM62x SIP SKEVM has DDR type LPDDR4. Add DDR configuration
for AM62x SK EVM in k3-am62x-sip-ddr-lp4-50-800.dtsi
Signed-off-by: Bryan Brattlof
Signed-off-by: Nitin Yadav
---
arch/arm/dts/k3-am62x-sip-ddr-lp4-50-800.dtsi | 2191 +
1 file changed, 2191 insertions(+)
create mode 10
The AM62x SIP SKEVM board has different type of DDR than
AM62x SK board. This requires different r5 SPL device tree.
These dt changes add support for AM62x SIP SKEVM at R5 SPL.
SK-AM62-SIP: https://www.ti.com/tool/download/SPRR482
Signed-off-by: Nitin Yadav
---
arch/arm/dts/Makefile
AM62 SIP has 512MB RAM. But the top of the RAM is reserved for
TF-A and OPTEE. U-Boot relocating there would cause overwriting
of these reserved regions. Fix this by limit U-Boot to first
64MB of RAM for all boards with 512MB.
Signed-off-by: Vignesh Raghavendra
Signed-off-by: Nitin Yadav
---
bo
This series adds support of AM62SIP SK board. The AM62SIP SK
is different from AM62x SK in terms of DDR Memory size which
is reduced to 512 M and embedded as part of SoC.
Note:
- Please apply this series after applying AM62x LP SK support series.
(https://lore.kernel.org/all/20231030110138.134
Hi,
On Oct 30, 2023 at 16:31:38 +0530, Nitin Yadav wrote:
> Add link for AM62x LP SK in platform information. AM62x LP SK
> has config fragments to build U-boot, Adding information to
> update UBOOT_CFG_CORTEXR with lpsk fragments over am62x defconfig.
>
> Signed-off-by: Nitin Yadav
> ---
> doc
Fill video handoff fields in video_post_probe
as at this point we have full framebuffer related
information.
Also fill all the fields available in video hand-off
struct as those were missing earlier and u-boot
framework expects them to be filled for some of the
functionalities.
Reported-by: Simon
Skip framebufer reservation if it was already reserved
from previous stage and whose information was passed
using a bloblist.
Signed-off-by: Devarsh Thakkar
Reviewed-by: Simon Glass
---
V2:
- Add debug prints
- Fix commenting style
---
drivers/video/video-uclass.c | 12
1 file chan
Start reservations needed for init sequence only after catching
bloblists from previous stage.
This is to avoid catching bloblists in the middle causing
gaps while u-boot is reserving.
Adjust the relocaddr as per video hand-off information
received from previous stage so that further reservations
Remove video_setup from evm_init sequence since video memory
is getting called at an earlier place to make sure
video memory is reserved at the end of RAM.
Suggested-by: Simon Glass
Signed-off-by: Devarsh Thakkar
---
V2: No change
---
board/ti/am62x/evm.c | 18 --
1 file change
Add function spl_reserve_video which is a wrapper
around video_reserve to setup video memory and update
the relocation address pointer.
Setup video memory before page table reservation so that
framebuffer memory gets reserved from the end of RAM.
This is as per the new policy being discussed for
Move video memory reservation for SPL at end of RAM so that it does
not interefere with reservations for next stage so that the next stage
need not have holes in between for passed regions and instead it can
maintain continuity in reservations.
Also catch the bloblist before starting reservations
On Tue, Oct 31, 2023 at 06:22:29PM +0530, Love Kumar wrote:
> Execute tftpput command for uploading files to a server and validate its
> size & CRC32.
>
> Signed-off-by: Love Kumar
> ---
> Changes in v2:
> - Add marking for cmd_tftpput config
> ---
> test/py/tests/test_net.py | 72 +
On Tue, Oct 31, 2023 at 05:24:38PM +0900, Jaehoon Chung wrote:
> Add gpio-restart node to do reset.
>
> Before applied this patch, System Reset Extension doesn't appear with
> sbi command.
>
> OpenSBI 1.3
> Machine:
> Vendor ID 489
> Architecture ID 8007
> Implementation ID 421
Abort the dhcp request in the middle by pressing ctrl + c on u-boot
prompt and validate the abort status.
Signed-off-by: Love Kumar
---
Changes in v2:
- Mark CMD_MII command dependency
---
test/py/tests/test_net.py | 45 +++
1 file changed, 45 insertions(+)
d
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.
A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.
Signed-off-by: Heinrich Schuchardt
Reviewed-by: Leo Yu-Chi Liang
-
If CSRs like seed are readable by S-mode, may not be determinable by
S-mode. For safe driver probing allow to resume via a longjmp after an
exception.
Signed-off-by: Heinrich Schuchardt
---
v3:
Add API documentation
v2:
New patch
---
arch/riscv/lib/interrupts.c | 13 +++
The Zkr ISA extension (ratified Nov 2021) introduced the seed CSR. It
provides an interface to a physical entropy source.
A RNG driver based on the seed CSR is provided. It depends on
mseccfg.sseed being set in the SBI firmware.
If the seed CSR readable, is not determinable by S-mode without risk
Execute tftpput command for uploading files to a server and validate its
size & CRC32.
Signed-off-by: Love Kumar
---
Changes in v2:
- Add marking for cmd_tftpput config
---
test/py/tests/test_net.py | 72 +++
1 file changed, 72 insertions(+)
diff --git a/test
On 10/31/23 13:06, Fabio Estevam wrote:
Hi Marek,
On Tue, Oct 31, 2023 at 7:16 AM Marek Vasut wrote:
+config CMD_MMC_REG
+ bool "Enable support for reading card registers in the mmc command"
+ depends on CMD_MMC
+ default n
"default n" could be dropped, since it is already
Add extension to the 'mmc' command to read out the card registers.
Currently, only the eMMC OCR/CID/CSD/EXTCSD/RCA/DSR register are
supported. A register value can either be displayed or read into
an environment variable.
Tested-by: Jaehoon Chung
Reviewed-by: Jaehoon Chung
Signed-off-by: Marek V
On 10/31/23 09:53, Xiang W wrote:
setjmp can be called in set_resume.
Unfortunately this is not possible. A longjmp buffer only stores
register values and not the stack content.
Let's assume that setjmp() is moved into set_resume():
Let a function call set_resume(). The caller's address wil
$subject missing am62x_sk
On 16:31-20231030, Nitin Yadav wrote:
> Add link for AM62x LP SK in platform information. AM62x LP SK
> has config fragments to build U-boot, Adding information to
> update UBOOT_CFG_CORTEXR with lpsk fragments over am62x defconfig.
>
> Signed-off-by: Nitin Yadav
> ---
Hi Marek,
On Tue, Oct 31, 2023 at 7:16 AM Marek Vasut wrote:
> +config CMD_MMC_REG
> + bool "Enable support for reading card registers in the mmc command"
> + depends on CMD_MMC
> + default n
"default n" could be dropped, since it is already the default.
On 16:31-20231030, Nitin Yadav wrote:
> The AM62x LP SK board is similar to the AM62x SK board,
> but has some significant changes that requires different
> device tree.
>
> The differences are mainly:
> - AM62x SoC in the AMC package that meets AECQ100 automotive standard.
> - LPDDR4 versus DDR4
On Tue, 31 Oct 2023 15:42:54 +0900
"Jaehoon Chung" wrote:
Hi Jaehoon,
> Hi,
>
> > -Original Message-
> > From: Andre Przywara
> > Sent: Sunday, October 22, 2023 6:19 AM
> > To: Jernej Škrabec
> > Cc: Jagan Teki ; Jaehoon Chung
> > ; Samuel Holland
> > ; SASANO Takayoshi ; Mikhail
>
On Tue, Oct 31, 2023 at 03:56:45PM +0800, Yong-Xuan Wang wrote:
> Hi Tom,
>
> 0x8020 comes from the result of the relocated_addr in booti_setup()
> on HiFive Unmatched board. If we load the Kernel Image to this address,
> it will not be moved. Currently one of the first two 8-byte of RISC-V
>
On 16:31-20231030, Nitin Yadav wrote:
[...]
> ---
> diff --git a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
> b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
> index c1685bc9ca..1a5238fb11 100644
> --- a/arch/arm/dts/k3-am625-sk-u-boot.dtsi
> +++ b/arch/arm/dts/k3-am625-sk-u-boot.dtsi
> @@ -1,102 +1,12 @@
> //
On Tue, Oct 31, 2023 at 04:03:18PM +0900, Masahiro Yamada wrote:
> On Tue, Oct 31, 2023 at 1:12 AM Tom Rini wrote:
> >
> > On Mon, Oct 30, 2023 at 03:35:34PM +, Russell King (Oracle) wrote:
> > > On Sun, Oct 29, 2023 at 05:46:12AM +1300, Simon Glass wrote:
> > > > Hi Masahiro,
> > > >
> > > >
On 10/31/23 09:26, Lothar Waßmann wrote:
Hi,
On Tue, 10 Oct 2023 14:47:28 +0200 Marek Vasut wrote:
Add extension to the 'mmc' command to read out the card registers.
Currently, only the eMMC OCR/CID/CSD/EXTCSD/RCA/DSR register are
supported. A register value can either be displayed or read into
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