On 2023/7/12 20:22, Jonas Karlman wrote:
The commit fd6e425be243 ("rockchip: rk3588-rock-5b: Enable boot from SPI
NOR flash") enabled SPI flash support by adding a spi0 alias.
Correct this by adding spi0-spi5 aliases in rk3588s-u-boot.dtsi and
SF_DEFAULT_BUS=5 and SPL_DM_SEQ_ALIAS=y in defconf
On 2023/7/12 20:22, Jonas Karlman wrote:
The commit 64f79f88a751 ("rockchip: rk3568-rock-3a: Enable boot from SPI
NOR flash") enabled SPI flash support by overriding the spi0 alias.
Correct this by adding a new spi4 alias in rk356x-u-boot.dtsi and
SF_DEFAULT_BUS=4 and SPL_DM_SEQ_ALIAS=y in def
Hi Jan,
On 08:42-20230726, Jan Kiszka wrote:
> On 14.07.23 07:52, Manorit Chawdhry wrote:
> > The series focuses on fixes for various boards along with moving to
> > standards and enabling the FIT_SIGNATURE for K3 Platforms towards the
> > end.
> >
> > Dependencies:
> > https://lore.kernel.org/u-
> From: Heinrich Schuchardt
> Sent: Wednesday, July 26, 2023 2:05 PM
> To: Rick Jian-Zhi Chen(陳建志)
> Cc: Leo Yu-Chi Liang(梁育齊) ; u-boot@lists.denx.de;
> Heinrich Schuchardt
> Subject: [PATCH v2 1/1] acpi: Add missing RISC-V acpi_table header
>
> The pci_mmc.c driver can generate ACPI info and t
On Wed, Jul 26, 2023 at 08:05:13AM +0200, Heinrich Schuchardt wrote:
> The pci_mmc.c driver can generate ACPI info and therefore includes
> asm/acpi_table.h. This file does not exist for the RISC-V architecture
> and thus code compilation fails when using this driver on RISC-V
>
> Create an empty
On 14.07.23 07:52, Manorit Chawdhry wrote:
> The series focuses on fixes for various boards along with moving to
> standards and enabling the FIT_SIGNATURE for K3 Platforms towards the
> end.
>
> Dependencies:
> https://lore.kernel.org/u-boot/20230712183453.7623-1-n-fran...@ti.com/
>
> Signed-off
Hi Tom,
On 2023-07-26 03:47, Kever Yang wrote:
> Hi Jonas,
>
> Could you split this patchset into two patch set?
>
> I can take the patch 3, but the patch 1~2 is suppose to go to other
> maintainer's tree, unless those patches got ACK from maintainer.
No one is listed as maintainer f
On 2023/7/26 12:56, Yifan Zhao wrote:
In [1] Sam points out an assertion does not hold true for 32-bit
platforms, which only impacts Large File Support (LFS) API usage
in erofs-utils according to Xiang [2]. We don't think these APIs
are used in u-boot and this restriction could be safely remov
The pci_mmc.c driver can generate ACPI info and therefore includes
asm/acpi_table.h. This file does not exist for the RISC-V architecture
and thus code compilation fails when using this driver on RISC-V
Create an empty include file.
Signed-off-by: Heinrich Schuchardt
---
v2:
Add include
On 7/25/23 18:46, Du Huanpeng wrote:
- watchdog driver for ls1c300 with devicetree support
Signed-off-by: Du Huanpeng
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/watchdog/Kconfig | 8 +++
drivers/watchdog/Makefile | 1 +
drivers/watchdog/lsmips_wdt.c | 127 ++
On 7/25/23 11:47 PM, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 09:09:34AM -0500, Nishanth Menon wrote:
>> On 15:56-20230725, Maxime Ripard wrote:
>>> Hi,
>>>
>>> On Tue, Jul 25, 2023 at 07:58:56AM -0500, Nishanth Menon wrote:
>>>> Update the am62
Hi Tom,
Thanks for the patch!
On 25/07/23 22:14, Tom Rini wrote:
Now that we are using binman in all cases on these platforms, reword
things to be clearer that for filesystem booting we need to use a
specific name for each component.
Signed-off-by: Tom Rini
---
Cc: Neha Malcom Francis
Cc: He
Hi
> -Original Message-
> From: Marek Vasut
> Sent: Saturday, 22 July, 2023 4:31 AM
> To: Lim, Jit Loon ; u-boot@lists.denx.de
> Cc: Jagan Teki ; Simon
> ; Chee, Tien Fong
> ; Hea, Kok Kiang ;
> Maniyam, Dinesh ; Ng, Boon Khai
> ; Yuslaimi, Alif Zakuan
> ; Chong, Teik Heng
> ; Zamri, Muha
Hi Heinrich,
On Tue, Jul 25, 2023 at 09:44:00AM +0200, Heinrich Schuchardt wrote:
> On 7/25/23 04:26, Bin Meng wrote:
> > +Simon,
> >
> > On Tue, Jul 25, 2023 at 9:30 AM Heinrich Schuchardt
> > wrote:
> > >
> > > The pci_mmc.c driver can generate ACPI info and therefore includes
> > > asm/acpi_
On Tue, Jul 25, 2023 at 05:46:47PM +0800, Minda Chen wrote:
> As the Designware_i2c_pci.c uses ACPI APIs, If some SoCs (StarFive
> JH7110) contain Designware i2c and PCI but do not use ACPI,
> This file will be can't be compiled. So add a new Kconfig for
> designware_i2c_pci.c, which depends on ACP
When raspberrpi-4b platform boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" vid
From: Meng Li
There are 2 patches as bleow:
0001-bcm2835-Add-simiple-framebuffer-for-use-with-fkms.patch
0002-rpi-set-the-correct-parameter-for-simple-framebuffer.patch
The first one is used to enable u-boot video driver.
The second one is used to fix the wired display status on monitor.
Jason W
From: Jason Wessel
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.
Signed-off-by: Jason Wessel
Signed-off-by: Meng Li
---
drivers/video/bcm2835.c | 3 +++
1 file chang
On 2023/7/17 00:53, Pegorer Massimo wrote:
DEBUG_UART_SKIP_INIT feature is implemented only by s5p (DEBUG_UART_S5P)
and pl01x (DEBUG_UART_PL010 or DEBUG_UART_PL011) serial drivers, but all
ARCH_ROCKCHIP configs rely on default DEBUG_UART_NS16550. The ns16550
serial driver does not depends on DE
On 2023/7/20 00:33, Christopher Obbard wrote:
Add board-specific devicetree/config for the RK3399T-based Radxa ROCK 4SE
board. This board offers similar peripherals in a similar form-factor to
the existing ROCK Pi 4B but uses the cost-optimised RK3399T processor
(which has different OPP table t
On 2023/7/20 00:33, Christopher Obbard wrote:
To prepare for ROCK 4 SE support, changes are needed to the common ROCK
Pi 4 devicetree to move the OPP from the common devicetree to individual
board devicetrees. Sync the Rockchip RK3399 ROCK Pi 4-related DTs from
Linux to gain from these changes.
Hi Tom,
On 2023/7/20 02:43, Tom Rini wrote:
On Wed, Jul 19, 2023 at 05:33:55PM +0100, Christopher Obbard wrote:
Add support for the RK3399T-based Radxa ROCK 4SE board. This board offers
similar peripherals and form-factor to the ROCK Pi 4B but uses the
cost-optimised RK3399T processor (which h
On 2023/7/25 20:58, Paul Kocialkowski wrote:
The standard boot path expects the kernel_comp_addr_r and kernel_comp_size
variables for booting compressed kernel images. Define them using the previous
kernel_addr_c value (likely initially meant for this purpose) and usual size.
This was tested o
On 2023/7/25 20:05, Jonas Karlman wrote:
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD, nano SIM card slot and a 26-pin GPIO header.
Features tested on a Radxa E25 v1.4:
- SD-card
On 2023/7/24 06:25, Jonas Karlman wrote:
Radxa E25 is a network application carrier board for the Radxa CM3I SoM
with a RK3568 SoC. It features dual 2.5G ethernet, mini PCIe, M.2 B Key,
USB3, eMMC, SD and nano sim card slot.
Features tested on a Radxa E25 v1.4:
- SD-card boot
- eMMC boot
- USB
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz compute module is mostly pin-compatible with the RPi
CM4 form factor. Therefore, it can slot into the official Raspberry Pi
CM4 IO carrier board. Add this configuration to U-Boot.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Blade board is a carrier board for the SOQuartz
CM4-compatible compute module. It features PoE, an M.2 slot, an SD card
slot, HDMI, USB, serial and ethernet.
Features tested with a SOQuartz 4GB v1.1 2022-07-11:
- SD-card boot
- eMMC
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 SOQuartz Model A board is a carrier board for the SOQuartz
CM4-compatible compute module. It exposes PCIe, ethernet, USB, HDMI,
CSI, DSI, eDP and a 40 pin GPIO header, and is powered by 12V DC.
Features tested with a SOQuartz 4GB v1.1 2022-07
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model B is a credit-card sized single-board
computer based on the Rockchip RK3566 SoC. The board features an M.2
PCIe slot, USB3, USB2, eMMC, SD, ethernet, HDMI, analog audio out, a
40 pin GPIO header and a DSI and CSI port, as well a
On 2023/7/23 22:55, Jonas Karlman wrote:
The Pine64 Quartz64 Model A is a single-board computer based on the
Rockchip RK3566 SoC. The board features USB3, SATA, PCIe, HDMI, USB2.0,
CSI, DSI, eDP, eMMC, SD, and an e-paper parallel port, as well as a
20 pin GPIO header.
Features tested on a Quar
On 2023/7/21 16:46, Alper Nebi Yasak wrote:
Some veyron boards seem to have Winbond SPI flash chips instead of
GigaDevice ones. At the very least, coreboot builds for veyron boards
have them enabled [1]. Enable support for them here as well.
[1] https://review.coreboot.org/c/coreboot/+/9719
S
Hi Jonas,
Could you split this patchset into two patch set?
I can take the patch 3, but the patch 1~2 is suppose to go to other
maintainer's tree, unless those patches got ACK from maintainer.
Thanks,
- Kever
On 2023/7/22 22:02, Jonas Karlman wrote:
This series add support for Ha
On 2023/7/22 22:02, Jonas Karlman wrote:
Hardkernel ODROID-M1 is a single board computer with a RK3568B2 SoC,
a slightly modified version of the RK3568 SoC.
Features tested on a ODROID-M1 8GB v1.0 2022-06-13:
- SD-card boot
- eMMC boot
- SPI Flash boot
- PCIe/NVMe/AHCI
- SATA port
- USB host
On 2023/7/22 21:30, Jonas Karlman wrote:
Add missing pinctrl and defconfig options to enable PCIe and NVMe
support on Radxa ROCK 3 Model A.
Use of pcie20m1_pins and pcie30x2m1_pins ensure IO mux selection M1.
The following pcie_reset_h and pcie3x2_reset_h ensure GPIO func is
restored to the pe
On 2023/7/22 21:30, Jonas Karlman wrote:
From: Jon Lin
The Root Complex BARs default to claim the full 1 GiB memory region on
RK3568, leaving no space for any attached device.
Fix this by disable the unused BAR 0 and BAR 1 of the RC.
Signed-off-by: Jon Lin
[jo...@kwiboo.se: Move to rk_pcie
Hi Simon,
These pending patches are on my todo list and suppose to be
handled in this week.
Will check the u-boot-rockchip.bin for rk3588.
Thanks,
- Kever
On 2023/7/26 02:02, Simon Glass wrote:
Hi,
What is the mainline status of this board? I see a lot of pending
patches, for exam
Hi Sam,
On 2023/7/26 05:40, Sam Edwards wrote:
Hi folks,
On 7/7/23 09:52, Yifan Zhao wrote:
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 4af7c91560..433a3c6c1e 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
+/* make sure that any user of the erofs headers has at lea
> From: Heinrich Schuchardt
> Sent: Tuesday, July 25, 2023 6:42 PM
> To: Rick Jian-Zhi Chen(陳建志) ; Leo Yu-Chi Liang(梁育齊)
>
> Cc: Paul Walmsley ; Green Wan
> ; u-boot@lists.denx.de; Heinrich Schuchardt
>
> Subject: [PATCH 1/1] riscv: sifive: initialize PCI on Unmatched
>
> The Unmatched board
On 7/26/23 00:31, Tom Rini wrote:
A few platforms have been added without a MAINTAINERS file. Create
these based on the initial commits.
Signed-off-by: Tom Rini
---
I wasn't 100% sure on how to best handle these boards, especially the
v3hsk so I've made my best guess.
Cc: Hai Pham
Cc: Marek
From: Sean Edmond
Allow dhcp server pass pxe config file full path by using option 209
Signed-off-by: Sean Edmond
---
cmd/Kconfig | 4
cmd/pxe.c | 8
net/bootp.c | 21 +
3 files changed, 33 insertions(+)
diff --git a/cmd/Kconfig b/cmd/Kconfig
index 2d6e5f
There is an Errata with the built-in I2C controller where various I2C
hardware errors cause a complete lockup of the CPU (which eventually
results in an watchdog reset).
Put the I2C MPP pins into GPIO mode and use the i2c-gpio driver instead.
This uses a bit-banged implementation of an I2C control
gpio_request_list_by_name() returns the number of gpios requested.
Notably it swallows the underlying -ENOENT when the "gpios" property
does not exist.
Update the i2c-gpio driver to check for ret == 0 before trying the new
sda-gpios/scl-gpios properties.
Signed-off-by: Chris Packham
---
This was
On Tue, Jul 25, 2023 at 11:26:40PM +0200, Angelo Dureghello wrote:
> The following changes since commit ff296acc3549c18aaf95dcb1052c9fe4f1a98552:
>
> Prepare v2023.10-rc1 (2023-07-25 17:19:54 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-coldfire.git master
From: Sean Edmond
RFC 5970 states that OPT_BOOTFILE_PARAM (option 60) can be
multiple parameters that start with a 16-bit length field followed
by the parameter. For example:
[ param-len 1 (16-bits) ] [ parameter 1 (variable length) ]
This fix ensure we're considering "param-len 1" in the parsin
On Tue, Jul 25, 2023 at 04:52:38PM -0600, Simon Glass wrote:
> On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
> >
> > Support has being added through earlier commits to build capsules
> > and embed the public key needed for capsule authentication as part of
> > u-boot build.
> >
> > From the te
On Tue, 25 Jul 2023 at 15:09, Tom Rini wrote:
>
> Rather than invoking the script that will write to the mounted directory
> as a binary, source it as a script so that it has access to more than
> just two parameters. This will allow us to have the same flexibility in
> our writers that other fla
On Tue, 25 Jul 2023 at 15:09, Tom Rini wrote:
>
> The TI K3 platforms require a number of things in order to boot. We must
> have built both the Cortex-R and Cortex-A configurations (following
> their board documents and requirements as these need additional tooling
> and binaries). Further, depen
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> Add support to build a tool from source with a list of commands. This
> is useful when a tool can be built with multiple commands instead of a
> single command.
>
> Signed-off-by: Sughosh Ganu
> ---
> Changes since V4:
> * Pass the single comm
Hi,
On Tue, 25 Jul 2023 at 10:18, Heinrich Schuchardt wrote:
>
> On 25.07.23 10:57, Sughosh Ganu wrote:
> > The UEFI capsule can now be generate by specifying the capsule
> > parameters through a config file. Additionally, the capsules can be
> > generated as part of u-boot build, through binman.
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> The embedding of the public key EFI Signature List(ESL) file into the
> platform's DTB is now done at the time of u-boot build. Remove this
> logic from the capsule update test' configuration.
>
> Include the public key for the sandbox and sand
Hi Tom,
On Tue, 25 Jul 2023 at 15:39, Tom Rini wrote:
>
> On Tue, Jul 25, 2023 at 03:28:37PM -0600, Simon Glass wrote:
> > Hi Tom,
> >
> > On Tue, 25 Jul 2023 at 10:37, Tom Rini wrote:
> > >
> > > On Tue, Jul 25, 2023 at 08:51:55AM -0600, Simon Glass wrote:
> > > > On Mon, 24 Jul 2023 at 14:19,
Hi Sughosh,
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> The EFI capsule files can now be generated as part of u-boot
> build. This is done through binman. Add capsule entry nodes in the
> u-boot.dtsi for the sandbox architecture for generating the
> capsules. Remove the corresponding ge
Hi Sughosh,
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> Support has been added to the mkeficapsule tool to generate capsules
> by parsing the capsule parameters through a config file. Add a config
> file for generating capsules. These capsules will be used for testing
> the capsule upda
On Tue, 25 Jul 2023 at 15:09, Tom Rini wrote:
>
> In the case of TI OMAP (and similar) platforms, the SD card needs MLO
> and u-boot.img to boot, always. Copy these files over.
>
> Signed-off-by: Tom Rini
> ---
> bin/writer.ti-omap_mount | 29 +
> 1 file changed, 29
On Tue, 25 Jul 2023 at 15:08, Tom Rini wrote:
>
> Now that we have access to more variables in our "mount" writer scripts,
> we can have a single one that covers all Pi variants.
>
> Signed-off-by: Tom Rini
> ---
> I use this locally to test a Pi 3 in both 32, 64 and "arm64" mode.
>
> Cc: Simon G
On Tue, 25 Jul 2023 at 16:32, Tom Rini wrote:
>
> As the defconfig files here have been removed we can also remove the
> entries.
>
> Signed-off-by: Tom Rini
> ---
> board/freescale/t104xrdb/MAINTAINERS | 5 -
> board/freescale/t208xrdb/MAINTAINERS | 5 -
> 2 files changed, 10 deletions(
Hi Sughosh,
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> Support has being added through earlier commits to build capsules and
> embed the public key needed for capsule authentication as part of
> u-boot build.
>
> From the testing point-of-view, this means the input files needed for
> t
Hi Sughosh,
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> Add support in binman for generating capsules. The capsule parameters
> can be specified either through a config file or through the capsule
> binman entry. Also add test cases in binman for capsule generation,
> and enable this te
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> Support has being added through earlier commits to build capsules
> and embed the public key needed for capsule authentication as part of
> u-boot build.
>
> From the testing point-of-view, this means the input files needed for
> generating the
Hi Sughosh,
On Tue, 25 Jul 2023 at 02:58, Sughosh Ganu wrote:
>
> The EFI capsule authentication logic in u-boot expects the public key
> in the form of an EFI Signature List(ESL) to be provided as part of
> the platform's dtb. Currently, the embedding of the ESL file into the
> dtb needs to be d
On Tue, Jul 25, 2023 at 05:00:15PM -0500, Nishanth Menon wrote:
> On 17:35-20230725, Tom Rini wrote:
> > On Tue, Jul 25, 2023 at 01:52:53PM -0500, Nishanth Menon wrote:
> >
> [...]
>
> > > +
> > > +Build procedure:
> > > +
>
Hi Sughosh,
On Thu, 20 Jul 2023 at 03:20, Sughosh Ganu wrote:
>
> hi Simon,
>
> On Thu, 20 Jul 2023 at 00:41, Simon Glass wrote:
> >
> > Hi Sughosh,
> >
> > On Wed, 19 Jul 2023 at 02:42, Sughosh Ganu wrote:
> > >
> > > hi Simon,
> > >
> > > On Wed, 19 Jul 2023 at 06:41, Simon Glass wrote:
> >
On Wed, Jul 26, 2023 at 12:16:21AM +0200, Francesco Dolcini wrote:
> On Tue, Jul 25, 2023 at 05:03:28PM -0500, Nishanth Menon wrote:
> > On 17:42-20230725, Tom Rini wrote:
> > > On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote:
> > > > On 17:25-20230725
This should have been included when the platform was added, make one
now.
Signed-off-by: Tom Rini
---
Cc: Ralph Siemsen
---
board/schneider/rzn1-snarc/MAINTAINERS | 9 +
1 file changed, 9 insertions(+)
create mode 100644 board/schneider/rzn1-snarc/MAINTAINERS
diff --git a/board/schnei
A few platforms have been added without a MAINTAINERS file. Create
these based on the initial commits.
Signed-off-by: Tom Rini
---
I wasn't 100% sure on how to best handle these boards, especially the
v3hsk so I've made my best guess.
Cc: Hai Pham
Cc: Marek Vasut
---
board/renesas/spider/MAI
Given that we no longer have a configs/vexpress_aemv8a_defconfig file,
drop that and then include at least the aarch64-specific config.h file
here. Also move Linus and Peter up to the main entry as well so that
they'll get tagged for the board code too and not literally only the
defconfig.
Signed
As the defconfig files here have been removed we can also remove the
entries.
Signed-off-by: Tom Rini
---
board/freescale/t104xrdb/MAINTAINERS | 5 -
board/freescale/t208xrdb/MAINTAINERS | 5 -
2 files changed, 10 deletions(-)
diff --git a/board/freescale/t104xrdb/MAINTAINERS
b/board/f
On Tue, Jul 25, 2023 at 05:03:28PM -0500, Nishanth Menon wrote:
> On 17:42-20230725, Tom Rini wrote:
> > On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote:
> > > On 17:25-20230725, Tom Rini wrote:
> > > > On Tue, Jul 25, 2023 at 01:52:50
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" s
>
> Can you please add a doc/usage/cmd/fastboot.rst as well? Can be a
> separate patch.
Added in the v3 version of this patch. Since we already have detailed
`doc/android/fastboot.rst`, I created a short version here
`doc/usage/cmd/fastboot.rst` which refers to android documentation.
On Sun, Jul
>
> Can you use if() here?
Yes, fixed
On Sun, Jul 23, 2023 at 4:48 AM Simon Glass wrote:
> Hi Dmitrii,
>
> On Wed, 10 May 2023 at 11:00, Dmitrii Merkurev
> wrote:
> >
> > fastboot tcp command remains the same, but started
> > listening IP6 in case it's enabled.
> >
> > Signed-off-by: Dmitrii
>
> Is there anything that can be done to get rid of these, at least in
> the source code?
Got rid of all macro conditions across the whole patch stack. Tested it on
different configurations. Should be ok.
Please add a full comment
Added
On Sun, Jul 23, 2023 at 4:49 AM Simon Glass wrote:
>
On 17:42-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote:
> > On 17:25-20230725, Tom Rini wrote:
> > > On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote:
> > [..]
> >
> > > > +
>
> While you are here, or in a follow-up patch, can you please add full
> comments to net_set_ip_header(), e,g. what is the pkt param exactly?
> The whole packet, before any headers?
It's an IP header. Added comment and renamed the argument on this one and
net_set_udp_header.
On Sun, Jul 23, 2
On 17:35-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 01:52:53PM -0500, Nishanth Menon wrote:
>
[...]
> > +
> > +Build procedure:
> > +
> > +1. Trusted Firmware-A:
> > +
> > +.. code-block:: bash
> > +
> > + $ make CROS
Current active eth device may be changed (due to ethprime), so make
sure current net_ip6 is updated as a reaction.
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
Reviewed-by: Ying-Chun Liu (PaulLiu)
Reviewed-by: Simon Glass
--
Command to start IPv6 only TCP fastboot:
fastboot tcp -ipv6
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
Reviewed-by: Ying-Chun Liu (PaulLiu)
Reviewed-by: Simon Glass
---
cmd/fastboot.c | 29
fastboot tcp command remains the same, but started
listening IP6 in case it's enabled
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
Reviewed-by: Ying-Chun Liu (PaulLiu)
Reviewed-by: Simon Glass
---
include/net/fastboot_tcp.h
Add TCP/IP6 related headers and reuse refactored TCP/IP
implementation
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
Reviewed-by: Ying-Chun Liu (PaulLiu)
Reviewed-by: Simon Glass
---
include/net/tcp6.h | 103
Changes:
1. Separate reusable part from net_set_tcp_header to
net_set_tcp_header_common
2. Make TCP signatures reusable by receiving particular
IP agnostic TCP headers
3. Extract net_send_ip_packet6 from net_send_udp_packet6
to reuse the code
4. Expose TCP state machine related functions
This allo
This allows us to reuse TCP logic between IP and IP6 stack.
Signed-off-by: Dmitrii Merkurev
Cc: Ying-Chun Liu (PaulLiu)
Cc: Simon Glass
Сс: Joe Hershberger
Сс: Ramon Fried
Reviewed-by: Ying-Chun Liu (PaulLiu)
Reviewed-by: Simon Glass
---
include/net/tcp.h | 54 -
On Tue, Jul 25, 2023 at 04:37:55PM -0500, Nishanth Menon wrote:
> On 17:25-20230725, Tom Rini wrote:
> > On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote:
> [..]
>
> > > + /* Set USB0 PHY core voltage to 0.85V */
> > > + val = readl(CT
Hi folks,
On 7/7/23 09:52, Yifan Zhao wrote:
diff --git a/fs/erofs/internal.h b/fs/erofs/internal.h
index 4af7c91560..433a3c6c1e 100644
--- a/fs/erofs/internal.h
+++ b/fs/erofs/internal.h
+/* make sure that any user of the erofs headers has at least 64bit off_t type
*/
+extern int erofs_assert_
On Tue, Jul 25, 2023 at 03:28:37PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On Tue, 25 Jul 2023 at 10:37, Tom Rini wrote:
> >
> > On Tue, Jul 25, 2023 at 08:51:55AM -0600, Simon Glass wrote:
> > > On Mon, 24 Jul 2023 at 14:19, Heinrich Schuchardt
> > > wrote:
> > > >
> > > > MMC, SATA, and USB ma
On 17:25-20230725, Tom Rini wrote:
> On Tue, Jul 25, 2023 at 01:52:50PM -0500, Nishanth Menon wrote:
[..]
> > + /* Set USB0 PHY core voltage to 0.85V */
> > + val = readl(CTRLMMR_USB0_PHY_CTRL);
> > + val &= ~(CORE_VOLTAGE);
> > + writel(val, CTRLMMR_USB0_
Show the number of records in the table and the total table size in
bytes.
Signed-off-by: Simon Glass
---
arch/x86/include/asm/cb_sysinfo.h | 4
arch/x86/lib/coreboot/cb_sysinfo.c | 4
cmd/x86/cbsysinfo.c| 5 +++--
3 files changed, 11 insertions(+), 2 deletions(-)
di
Align the documentation with the v0.9 spec.
Signed-off-by: Simon Glass
---
doc/develop/bloblist.rst | 4 +++-
include/bloblist.h | 1 +
2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/doc/develop/bloblist.rst b/doc/develop/bloblist.rst
index 81643c7674b..28431039adc 100644
-
Allow the alignment to be specified when creating a bloblist.
Signed-off-by: Simon Glass
---
common/bloblist.c | 5 +++--
include/bloblist.h | 3 ++-
test/bloblist.c| 40 ++--
3 files changed, 27 insertions(+), 21 deletions(-)
diff --git a/common/blob
Use a sinple 8-bit checksum for bloblist, as specified by the spec
version 0.9
Signed-off-by: Simon Glass
---
common/bloblist.c | 14 --
include/bloblist.h | 5 ++---
2 files changed, 10 insertions(+), 9 deletions(-)
diff --git a/common/bloblist.c b/common/bloblist.c
index 96b82f
The v0.9 spec provides for a 16-byte header with fewer fields. Update
the implementation to match this.
This also adds an alignment field.
Signed-off-by: Simon Glass
---
include/bloblist.h | 26 +-
test/bloblist.c| 6 +++---
2 files changed, 16 insertions(+), 16 de
There are no spare values in spec v0.9 so drop them.
For now they are still present in the headers, with an underscore, so that
tests continue to pass.
Signed-off-by: Simon Glass
---
common/bloblist.c | 1 -
include/bloblist.h | 6 ++
test/bloblist.c| 4
3 files changed, 2 insert
The v0.9 spec provides for an 8-byte header for each blob, with fewer
fields. Update the implementation to match this.
Signed-off-by: Simon Glass
---
common/bloblist.c | 17 +
include/bloblist.h | 33 ++---
test/bloblist.c| 16
3
There is no flags value in spec v0.9 so drop it.
For now it is still present in the header, with an underscore, so that
tests continue to pass.
Signed-off-by: Simon Glass
---
common/bloblist.c | 5 ++---
include/bloblist.h | 6 ++
test/bloblist.c| 45 +++-
Rather than setting the alignment using the header size, add an entirely
new entry to cover the gap left by the alignment.
Signed-off-by: Simon Glass
---
common/bloblist.c | 23 +++
1 file changed, 19 insertions(+), 4 deletions(-)
diff --git a/common/bloblist.c b/common/blo
Spec v0.9 specifies that the entire bloblist area is checksummed,
including unused portions. Update the code to follow this.
Signed-off-by: Simon Glass
---
common/bloblist.c | 9 +
test/bloblist.c | 10 --
2 files changed, 9 insertions(+), 10 deletions(-)
diff --git a/common
The new bloblist for v0.9 has version 1 so update this value.
Signed-off-by: Simon Glass
---
include/bloblist.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/bloblist.h b/include/bloblist.h
index 6ef3e9466e8..74932dcae6f 100644
--- a/include/bloblist.h
+++ b/includ
These values currently use a simple field. With spec v0.9 they have moved
to a packed format. Convert most accesses to use functions, so this change
can be accomodated.
Signed-off-by: Simon Glass
---
common/bloblist.c | 38 +-
1 file changed, 25 insertions(+)
This uses a new value with spec v0.9 so change it.
Signed-off-by: Simon Glass
---
include/bloblist.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/bloblist.h b/include/bloblist.h
index e6ce98334d3..6ef3e9466e8 100644
--- a/include/bloblist.h
+++ b/include/bloblist.
The updated bloblist structure stores the alignment as a power-of-two
value in its structures. Adjust the API to use this, to avoid needing to
calling ilog2().
Drop a stale comment while we are here.
Signed-off-by: Simon Glass
---
arch/x86/lib/tables.c | 3 ++-
common/bloblist.c | 24
Align this with the new v0.9 spec. It only has a single area for all
non-standard tags.
Signed-off-by: Simon Glass
---
common/bloblist.c | 2 +-
include/bloblist.h | 37 +
test/bloblist.c| 2 +-
3 files changed, 15 insertions(+), 26 deletions(-)
diff
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