On Fri, Sep 16, 2022 at 09:46:49PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> On 16.09.22 21:22, Tom Rini wrote:
> > On Fri, Sep 16, 2022 at 09:12:54PM +0200, Stefan Roese wrote:
> > > Hi Tom,
> > >
> > > On 16.09.22 16:37, Stefan Roese wrote:
> > > > Hi Tom,
> > > >
> > > > On 16.09.22 16:21, Tom
Hi Simon,
[...]
> > Signed-off-by: Ilias Apalodimas
> > ---
> > lib/smbios.c | 17 +++--
> > 1 file changed, 3 insertions(+), 14 deletions(-)
>
> Perhaps a better fix is to drop the smbios info?
Unfortunately there's a ton of userspace tools still using it. So I think
we still ne
Hi Heinrich,
On Fri, 16 Sept 2022 at 00:41, Heinrich Schuchardt
wrote:
>
>
>
> On 9/16/22 03:30, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Thu, 15 Sept 2022 at 14:02, Heinrich Schuchardt
> > wrote:
> >>
> >> Currently block devices are only identified by uclass_id and device number.
> >> Wh
Hi Simon,
> > > > > >
> > > > > > Late versions of OP-TEE support a pseudo bus. TAs that behave as
> > > > > > hardware blocks (e.g TPM, RNG etc) present themselves on a bus
> > > > > > which we can
> > > > > > scan. Unfortunately U-Boot doesn't support that yet. It's worth
> > > > > > noting
Hi Tom,
On 16.09.22 21:22, Tom Rini wrote:
On Fri, Sep 16, 2022 at 09:12:54PM +0200, Stefan Roese wrote:
Hi Tom,
On 16.09.22 16:37, Stefan Roese wrote:
Hi Tom,
On 16.09.22 16:21, Tom Rini wrote:
On Fri, Sep 16, 2022 at 10:08:51AM -0400, Tom Rini wrote:
On Fri, Sep 16, 2022 at 09:22:16AM +0
On Thu, Aug 11, 2022 at 07:34:40PM -0600, Simon Glass wrote:
> Fix a few typos in this help text. Fix a typo in SPL_PARTITIONS while
> we are here.
>
> Signed-off-by: Simon Glass
For patches 1 through 22, applied to u-boot/next, thanks!
--
Tom
signature.asc
Description: PGP signature
On Fri, Sep 16, 2022 at 09:12:54PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> On 16.09.22 16:37, Stefan Roese wrote:
> > Hi Tom,
> >
> > On 16.09.22 16:21, Tom Rini wrote:
> > > On Fri, Sep 16, 2022 at 10:08:51AM -0400, Tom Rini wrote:
> > > > On Fri, Sep 16, 2022 at 09:22:16AM +0200, Stefan Roese
Hi Tom,
On 16.09.22 16:37, Stefan Roese wrote:
Hi Tom,
On 16.09.22 16:21, Tom Rini wrote:
On Fri, Sep 16, 2022 at 10:08:51AM -0400, Tom Rini wrote:
On Fri, Sep 16, 2022 at 09:22:16AM +0200, Stefan Roese wrote:
Hi Tom,
please pull the following watchdog related patches:
---
Greetings,
I'm wondering if anyone has done any work to get dual-role USB working
for the IMX8MP (or any other dwc3 host based board) and how they went
about it if so.
The imx8mp-venice-gw74xx has dual-role support through a USB Type-C
connector with a TPS25821 (driverless) that monitors the CC s
On Wed, 14 Sep 2022 13:37:46 +0200
Pali Rohár wrote:
> When MMU is already enabled then dcache_enable() does not call mmu_setup()
> and so setup_all_pgtables() is also never called.
>
> In this situation when some driver calls mmu_set_region_dcache_behaviour()
> function then U-Boot crashes with
On Wed, 14 Sep 2022 15:06:14 +0200
Pali Rohár wrote:
> Currently CONFIG_BOARD_SIZE_LIMIT check is ignored for u-boot-spl.kwb
> target. Fix it by adding missing $(BOARD_SIZE_CHECK) macro.
>
> Signed-off-by: Pali Rohár
> ---
> Makefile | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/Ma
On Wed, 14 Sep 2022 15:06:46 +0200
Pali Rohár wrote:
> Maximal size of u-boot kwb image binary is $CONFIG_ENV_OFFSET which is
> 0xF = 983040 bytes. So add missing CONFIG_BOARD_SIZE_LIMIT definition
> to ensure that u-boot binary does not overflow to the u-boot env storage.
>
> Signed-off-by:
On Wed, 14 Sep 2022 18:48:16 +0200
Pali Rohár wrote:
> 32-bit Marvell Armada BootROMs limit maximal size of SPL image to 192 kB.
> So define 192 kB (= 0x3) limit as default value for SPL_SIZE_LIMIT.
>
> Signed-off-by: Pali Rohár
Reviewed-by: Marek Behún
On Mon, 12 Sep 2022 15:37:25 +0800
Peng Fan wrote:
> On 9/12/2022 3:33 PM, Peng Fan wrote:
> >
> >
> > On 9/9/2022 12:29 AM, Marek Behún wrote:
> >> On Thu, 8 Sep 2022 17:05:53 +0200
> >> Pali Rohár wrote:
> >>
> >>> On Thursday 08 September 2022 07:21:03 Peng Fan wrote:
> On 9/8/20
On Friday 16 September 2022 17:32:04 Marek Behún wrote:
> Commit d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig") converted
> SYS_EXTRA_OPTIONS=SDCARD or SPIFLASH to config options CONFIG_SDCARD and
> CONFIG_SPIFLASH, but left one occurance unchanged.
>
> Fix this.
>
> Fixes: d433c74eecdc
Commit d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig") converted
SYS_EXTRA_OPTIONS=SDCARD or SPIFLASH to config options CONFIG_SDCARD and
CONFIG_SPIFLASH, but left one occurance unchanged.
Fix this.
Fixes: d433c74eecdc ("Convert CONFIG_SDCARD et al to Kconfig")
Signed-off-by: Marek Behún
For the RPi CM4 (Compute Module 4), we currently try to load the dtb
file bcm2711-rpi-cm4.dtb, which is not built by the upstream kernel.
Instead, the only CM4 dtb file provided by linux upstream is the
bcm2711-rpi-cm4-io.dtb, so let's use that.
Signed-off-by: Ariel D'Alessandro
---
board/raspb
Remove the unnecessary comment after the CONFIG_SYS_BOOTM_LEN
migration to Kconfig.
Fixes: c45568cc4e51 ("Convert CONFIG_SYS_BOOTM_LEN to Kconfig")
Signed-off-by: Patrick Delaunay
---
include/configs/stm32mp13_common.h | 2 --
include/configs/stm32mp15_common.h | 2 --
2 files changed, 4 deleti
From: Ley Foon Tan
Commit 407b01b3b3f5 ("mtd: rawnand: denali_dt: use UCLASS_MTD instead of
UCLASS_MISC") change to use UCLASS_MTD instead of UCLASS_MISC. Update
spl_boot_device() to use UCLASS_MTD.
Signed-off-by: Ley Foon Tan
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/spl_soc64.c
Hi Tom,
On 16.09.22 16:21, Tom Rini wrote:
On Fri, Sep 16, 2022 at 10:08:51AM -0400, Tom Rini wrote:
On Fri, Sep 16, 2022 at 09:22:16AM +0200, Stefan Roese wrote:
Hi Tom,
please pull the following watchdog related patches:
- M
On Fri, Sep 16, 2022 at 09:11:11AM -0400, Sean Anderson wrote:
> Hi Pali,
>
> On 9/16/22 05:12, Pali Rohár wrote:
> > That is strange because I'm not aware of the fact that I'm riscv maintainer.
>
> get_maintainer will pick up anyone who has touched a file recently, even in
> unrelated areas. A q
From: "Ooi, Joyce"
Since Stratix10 and Agilex are using ARM64, there are some common codes
in the SPL. Hence, spl_soc64.c is created to place the common codes.
Signed-off-by: Ooi, Joyce
Signed-off-by: Jit Loon Lim
---
arch/arm/mach-socfpga/spl_s10.c | 63 ---
arch/ar
From: Tien Fong Chee
Current SPL boot device is harcoded with MMC1, this implementation
would inhibit the support of other boot device. So, this patch is
created to get the boot device from DT, user should define the boot
device in property "u-boot,boot0". Default MMC1 would be boot device if
no
On Fri, Sep 16, 2022 at 10:08:51AM -0400, Tom Rini wrote:
> On Fri, Sep 16, 2022 at 09:22:16AM +0200, Stefan Roese wrote:
>
> > Hi Tom,
> >
> > please pull the following watchdog related patches:
> >
> >
> > - Migrate watchdog rese
On Fri, Sep 16, 2022 at 09:22:16AM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
>
> - Migrate watchdog reset to cyclic infrastructure (Stefan)
>
From: Tien Fong Chee
This field allows the FPGA ports to directly access the extra data bits
that are normally used to hold the ECC code, so this field must be clear
when it's used for ECC data.
Signed-off-by: Tien Fong Chee
Signed-off-by: Teik Heng Chong
---
drivers/ddr/altera/sdram_gen5.c |
Hi Pali,
On 9/16/22 05:12, Pali Rohár wrote:
That is strange because I'm not aware of the fact that I'm riscv maintainer.
get_maintainer will pick up anyone who has touched a file recently, even in
unrelated areas. A quick git log shows that the following commits have
overlapping files with th
Hi Stefano
I have more patches on m2 and I need to know if you are going to
request the merge to Tom soon or later. Alternative you can drop
this one and keep the new one
Michael
On Fri, Jul 29, 2022 at 12:10 PM wrote:
>
> > Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
>
On Friday 16 September 2022 22:34:52 Chris Packham wrote:
> I do wonder if the boot seqence and xmodem stuff could be abstracted out to
> something that could be reused by other tools.
In the past I was thinking about it... but I come to the conclusion that
it is easier to write specific tools whi
Sorry about that!
I ran get_maintainer.pl on my patchset and got your name
along with several others so I also sent to you.
On Fri, Sep 16, 2022 at 2:38 PM Pali Rohár wrote:
>
> Hello! I'm not riscv maintainer and therefore I'm not going to review
> this patch series. Please do not spam me with u
Semihosting is a mechanism that enables code running on
a target to communicate and use the Input/Output
facilities on a host computer that is running a debugger.
This patchset adds support for semihosting in u-boot
for RISCV64 targets.
CHANGES since v1:
- Moved the identical smh_* and semihosti
To enable semihosting we also need to enable the following
configs in defconfigs:
CONFIG_SEMIHOSTING
CONFIG_SPL_SEMIHOSTING
CONFIG_SEMIHOSTING_SERIAL
CONFIG_SERIAL_PROBE_ALL
CONFIG_SPL_FS_EXT4
CONFIG_SPL_FS_FAT
Signed-off-by: Kautuk Consul
---
configs/qemu-riscv32_defconfig | 4
confi
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel
Signed-off-by: Kautuk Consul
---
arch/riscv/Kconf
We factor out the arch-independent parts of the ARM semihosting
implementation as a common library so that it can be shared
with RISC-V.
Signed-off-by: Kautuk Consul
---
arch/arm/Kconfig | 2 +
arch/arm/lib/semihosting.c | 179 +--
include/semihosting.
Semihosting is a mechanism that enables code running on
a target to communicate and use the Input/Output
facilities on a host computer that is running a debugger.
This patchset adds support for semihosting in u-boot
for RISCV64 targets.
CHANGES since v1:
- Moved the identical smh_* and semihosti
Hi Sean,
Will address your comment in v2 by moving the ARM and RISCV code to generic
lib/semihosting.c.
On Thu, Sep 15, 2022 at 8:55 PM Sean Anderson wrote:
>
> Hi Kautuk,
>
> On 9/15/22 8:45 AM, Kautuk Consul wrote:
> > [You don't often get email from kcon...@ventanamicro.com. Learn why this i
Hi Sean,
Don't know about the DCSR.EBREAK option but it will be better for
us to extend the existing trap vector functionality as you mentioned.
Will handle this in v2. This also removes the need for us to implement
our semihosting_enabled() in inline assembly as it will become a
generic lib/semih
Hi Sean,
Thanks for the comments. Will address them in v2.
On Thu, Sep 15, 2022 at 9:35 PM Sean Anderson wrote:
>
>
>
> On 9/15/22 8:45 AM, Kautuk Consul wrote:
> > [You don't often get email from kcon...@ventanamicro.com. Learn why this is
> > important at https://aka.ms/LearnAboutSenderIdenti
These patches are based on Marvell's bootloader for the AlleyCat5/5X
which was based on u-boot 2018.03. I've split that code into consumable
chunks and dropped as much unnecessary stuff as I can. I've also tried
to sync the device trees as much as possible with the support that will
land in Linux 6
On Wed, 2022-09-07 at 15:10 -0600, Simon Glass wrote:
> Hi Ivan,
>
> Section data comes from the BuildSectionData() method, so you could
> try calling that.
>
> See also collect_contents_to_file()
>
> Regards,
> Simon
Simon, I've tried both these ways and they both don't work to me. What
I've g
We add RISC-V semihosting based serial console for JTAG based early
debugging.
The RISC-V semihosting specification is available at:
https://github.com/riscv/riscv-semihosting-spec/blob/main/riscv-semihosting-spec.adoc
Signed-off-by: Anup Patel
Signed-off-by: Kautuk Consul
---
arch/riscv/Kconf
To use semihosting on qemu RISCV virt machine, we need the
CONFIG_SPL_FS_LOAD_PAYLOAD_NAME define in qemu-riscv.h.
We also need to enable the following configs in defconfigs:
CONFIG_SEMIHOSTING
CONFIG_SPL_SEMIHOSTING
CONFIG_SEMIHOSTING_SERIAL
CONFIG_SERIAL_PROBE_ALL
Signed-off-by: Kautuk Consul
Semihosting is a mechanism that enables code running on
a target to communicate and use the Input/Output
facilities on a host computer that is running a debugger.
This patchset adds support for semihosting in u-boot
for RISCV64 targets.
Compilation and test commands for SPL and S-mode configuratio
Hi,
I am using a clearfog pro with emmc as router.
while upgrading from openwrt 21.02.3 to 22.03.0 I discovered, that the
provided u-boot binary gets rejected by the BootROM:
-> BootROM - 1.73
-> Booting from MMC
-> BootROM: Bad header at offset
-> BootROM: Bad header at offset 002000
On Friday 16 September 2022 16:54:22 Chris Packham wrote:
> +&spi0 {
> + status = "okay";
> +
> + spiflash0: flash@0 {
> + compatible = "jedec,spi-nor";
> + spi-max-frequency = <5000>;
> + spi-tx-bus-width = <1>; /* 1-single, 2-dual, 4-quad */
> +
hi Takahiro,
On Fri, 16 Sept 2022 at 12:20, Takahiro Akashi
wrote:
>
> On Fri, Sep 16, 2022 at 10:52:11AM +0530, Sughosh Ganu wrote:
> > () hi Takahiro,
> >
> > On Fri, 16 Sept 2022 at 07:17, Takahiro Akashi
> > wrote:
> > >
> > > Hi Sughosh,
> > >
> > > On Thu, Sep 15, 2022 at 01:44:46PM +0530,
On Friday 16 September 2022 22:34:52 Chris Packham wrote:
> On Fri, 16 Sep 2022, 8:12 PM Pali Rohár, wrote:
>
> > Hello! I think it does not make sense to hack kwboot to skip validation
> > of kwbimage format when ad-hoc TIM header is detected. kwboot has now
> > lot of features which requires an
On Fri, 16 Sep 2022, 8:12 PM Pali Rohár, wrote:
> Hello! I think it does not make sense to hack kwboot to skip validation
> of kwbimage format when ad-hoc TIM header is detected. kwboot has now
> lot of features which requires and expects valid kwbimage format and is
> now written to work special
From: Martyn Welch
Add support for the MSC SM2S-IMX8PLUS SMARC Module. Tested in conjunction
with the MSC SM2-MB-EP1 Mini-ITX Carrier Board.
Signed-off-by: Martyn Welch
---
Changes in v2:
- Renamed FDT to closer match kernel
- Sync with kernel FDT
- Update for changes made in U-Boot
Change
From: Martyn Welch
The i.MX8MP SoC contains 2 more i2c buses. Add support for the
configuration of these buses.
Signed-off-by: Martyn Welch
---
Changes in v2:
- None
Changes in v3:
- None
arch/arm/include/asm/arch-imx8m/imx-regs.h | 4
arch/arm/mach-imx/i2c-mxv7.c | 6
From: Martyn Welch
Add support for the rn5t568 PMIC to the rn5t567 driver.
Signed-off-by: Martyn Welch
---
Changes in v2:
- None
Changes in v3:
- None
drivers/power/pmic/rn5t567.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/power/pmic/rn5t567.c b/drivers/power/pmic/rn5t567
The support added later in this series tweaks the PMIC voltages in the
SPL. Enable support for the rn5t567 in SPL builds to allow this to be done
cleanly.
Signed-off-by: Martyn Welch
---
Changes in v3:
- New patch (replaces addition of legacy support for rn5t567)
drivers/power/pmic/Kconfig |
From: Martyn Welch
The i.MX8MP also has USDHC3, allow access to the relvant base address
definition.
Signed-off-by: Martyn Welch
---
Changes in v2:
- None
Changes in v3:
- None
arch/arm/include/asm/arch-imx8m/imx-regs.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/a
On 15/09/2022 21:06, Rafał Miłecki wrote:
From: Rafał Miłecki
DT binding allows specifying NVMEM cells as NVMEM device (provider)
subnodes. Looks for such subnodes when building NVMEM cells.
This allows NVMEM consumers to use U-Boot environment variables.
Signed-off-by: Rafał Miłecki
Ap
That is strange because I'm not aware of the fact that I'm riscv maintainer.
On Friday 16 September 2022 14:40:46 Kautuk Consul wrote:
> Sorry about that!
> I ran get_maintainer.pl on my patchset and got your name
> along with several others so I also sent to you.
>
> On Fri, Sep 16, 2022 at 2:38
Hello! I'm not riscv maintainer and therefore I'm not going to review
this patch series. Please do not spam me with unrelated emails and
patches as I would loose track of patches and emails which are import
and which I should review. Thanks.
On Friday 16 September 2022 13:42:30 Kautuk Consul wrote
Hello! I'm not maintainer of xilinx and I'm getting tons of emails. So
please do not send and spam me with unrelated emails/patches as I would
not have time to process those emails/patches which are important and
which I should review. Thanks.
On Friday 16 September 2022 10:53:11 Michal Simek wrot
Versal NET mini configuration is designed for running memory test. Current
output is on DCC but changing serial0 alias to pl011 will move console to
serial port.
Signed-off-by: Michal Simek
---
arch/arm/dts/Makefile| 1 +
arch/arm/dts/versal-net-mini.dts | 67 ++
Use one defconfig for supporting multiple different platforms. DTB
reselection is enabled to choose DT based on SOC detection.
Signed-off-by: Michal Simek
---
configs/xilinx_versal_net_virt_defconfig | 118 +++
1 file changed, 118 insertions(+)
create mode 100644 configs/xi
From: Jay Buddhabhatti
Enable zynqmp reset driver for Versal NET.
Signed-off-by: Jay Buddhabhatti
Signed-off-by: Michal Simek
---
drivers/reset/reset-zynqmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/reset/reset-zynqmp.c b/drivers/reset/reset-zynqmp.c
index 52c08c4722da..8
From: Jay Buddhabhatti
Enable mailbox configs for Versal NET.
Signed-off-by: Jay Buddhabhatti
Signed-off-by: Michal Simek
---
drivers/mailbox/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index acbdce11b7c7..47f2
From: Jay Buddhabhatti
Add compatible string for Versal NET.
Signed-off-by: Jay Buddhabhatti
Signed-off-by: Michal Simek
---
drivers/firmware/firmware-zynqmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/firmware/firmware-zynqmp.c
b/drivers/firmware/firmware-zynqmp.c
index 7
From: Jay Buddhabhatti
Add support for Versal NET compatible string in clock driver.
Signed-off-by: Jay Buddhabhatti
Signed-off-by: Michal Simek
---
drivers/clk/Kconfig | 2 +-
drivers/clk/clk_versal.c | 1 +
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/Kcon
Add support for Versal NET platform.
Signed-off-by: Michal Simek
---
drivers/spi/zynqmp_gqspi.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/zynqmp_gqspi.c b/drivers/spi/zynqmp_gqspi.c
index 4e718c545c64..d3cc8554b8fb 100644
--- a/drivers/spi/zynqmp_gqspi.c
Trivial changes to support cadence ospi driver for Versal NET platform.
Also avoid ospi flash reset for now.
Signed-off-by: Michal Simek
---
arch/arm/mach-versal-net/include/mach/hardware.h | 4
drivers/spi/Kconfig | 2 +-
drivers/spi/cadence_ospi_versal.c
Versal NET platform is based on Versal chip which is reusing a lot of IPs.
For more information about new IPs please take a look at DT which describe
currently supported devices.
The patch is adding architecture and board support with soc detection
algorithm. Generic setting should be very similar
Hi,
I am sending support for new Xilinx/AMD SoC called Versal NET.
Versal NET is very similar to origin Versal SOC. There is different
register layout, some IPs have been upgraded like i3c and some other
changes in different location.
Thanks,
Michal
Jay Buddhabhatti (4):
clk: versal: Enable c
On 9/15/22 19:56, John Keeping wrote:
> Unconditionally clearing DTO when RXDR is set leads to spurious timeouts
> in FIFO mode transfers if events occur in the following order:
>
> mask = dwmci_readl(host, DWMCI_RINTSTS);
>
> // Hardware asserts DWMCI_INTMSK_DTO here
>
> dw
Hello! I think it does not make sense to hack kwboot to skip validation
of kwbimage format when ad-hoc TIM header is detected. kwboot has now
lot of features which requires and expects valid kwbimage format and is
now written to work specially with 32-bit mvebu ARM BootROMs.
TIM and kwbimage are t
Hi Tom,
please pull the following watchdog related patches:
- Migrate watchdog reset to cyclic infrastructure (Stefan)
Here the Azure build, without any issues:
htt
On 02.09.22 14:10, Stefan Roese wrote:
This patchset migrates the watchdog triggering (WATCHDOG_RESET calls)
to the newly introduced cyclic execution framework. For this, the
watchdog driver now registers a cyclic execution function for each
WDT device that needs to get serviced. Additionally the
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