On 27.07.22 15:00, Marek Behún wrote:
There is a bug in Turris Omnia's schematics, whereupon the MPP[26] pin,
which is routed to CN11 pin header, is documented as SPI CS1, but
MPP[26] pin does not support this function. Instead it controls chip
select 2 if in "spi0" mode.
Fix the name of the pin
On 27.07.22 14:47, Pali Rohár wrote:
* Add SPDX-License-Identifier
* Add SFP and LED nodes
* Fix PHY nad NOR nodes
* Remove duplicates from u-boot.dtsi file
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
.../dts/armada-385-turris-omnia-u-boot.dtsi | 5 +-
ar
On 27.07.22 14:47, Pali Rohár wrote:
* Define PCIe interrupts
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-385.dtsi | 52 ++--
1 file changed, 44 insertions(+), 8 deletions(-)
diff --git a/arch/arm/dts/armad
On 27.07.22 14:47, Pali Rohár wrote:
* Replace skeleton.dtsi by explicit #address-cells / #size-cells
* Add sdramc@1400 and phy@18300 nodes
* Remove (unused) timeout-ms i2c properties
* Fix compatible string for UARTs
* Add interrupts properties for watchdog
Signed-off-by: Pali Rohár
Reviewed
On 27.07.22 14:47, Pali Rohár wrote:
Linux kernel uses compatible string "marvell,armada370-nand-controller" for
nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
"marvell,armada370-nand" and "marvell,mvebu-pxa3xx-nand".
So unify it and use just Linux kernel compatible string.
On 26.07.22 16:11, Pali Rohár wrote:
Negative return value from cmd main function cause U-Boot to print criplic
error message: exit not allowed from main input shell.
Set return value on error to 1.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
cmd/mvebu/bubt.c
On 26.07.22 16:11, Pali Rohár wrote:
Armada 3700 BootROM supports also images with sha512 checksums and
mox-imager tool [1] generates such bootable images. Without sha512 support
U-Boot bubt command just prints error message:
Error: Unsupported hash_algorithm_id = 64
Error: Image header ve
On 26.07.22 16:11, Pali Rohár wrote:
net_loop() returns signed int type and negative value represents error.
tftp_read_file() returns unsigned size_t type and zero value represents
error. Casting signed negative value to unsigned size_t type cause losing
information about error and bubt thinks th
On 26.07.22 16:11, Pali Rohár wrote:
Current image type verification code is specific to 32-bit Armada SoCs but
used only for Armada 38x. Implement image type verification for Armada 3700
and enable Armada 38x image verification for all 32-bit Armada SoCs.
Signed-off-by: Pali Rohár
Reviewed-b
On 25.07.22 15:01, Pali Rohár wrote:
This allows U-Boot to register new Turris Omnia MCU driver.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-385-turris-omnia.dts | 8 +++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/ar
On 25.07.22 15:01, Pali Rohár wrote:
This driver registers GPIO controller and allows U-Boot to control GPIO
pins on MCU which is connected to Turris Omnia via i2c.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
board/CZ.NIC/turris_omnia/MAINTAINERS | 1 +
dri
On 25.07.22 14:13, Pali Rohár wrote:
From: Konstantin Porotchkin
Current pin control driver applies SDHCI PHY MUX selection
when board DT calls for eMMC function on MPP wires.
However, for CP side eMMC, only the "armada-8k-cpm-pinctrl"
compatibility string is taken into account, which causes
CP
On 25.07.22 14:09, Pali Rohár wrote:
These functions are required for 'pinmux status -a' command to print
current configuration of each MPP pin.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 78 +
On 25.07.22 14:09, Pali Rohár wrote:
To automatically enable GPIO functionality of some MPP pin, it is required
to implement .gpio_request_enable and .gpio_disable_free callbacks in
pinctrl driver and set .request and .rfree callbacks in GPIO driver to
pinctrl_gpio_request / pinctrl_gpio_free fun
On 25.07.22 14:09, Pali Rohár wrote:
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 +++-
1 file changed, 15 insertions(+), 1 deletion(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/dri
On 25.07.22 14:09, Pali Rohár wrote:
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/pinctrl/mvebu/pinctrl-armada-37xx.c
b/drivers/pinc
On 25.07.22 14:08, Pali Rohár wrote:
They are available in pin_data structure.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 21 -
1 file changed, 8 insertions(+), 13 deletions(-)
diff --git a/d
On 25.07.22 14:08, Pali Rohár wrote:
grp->pins is just filled and never used. Remove it.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 +---
1 file changed, 1 insertion(+), 15 deletions(-)
diff --git
On 25.07.22 13:56, Pali Rohár wrote:
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
configs/turris_omnia_defconfig | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/turris_omnia_defconfig b/configs/turris_omnia_defconfig
index e2a0449
On 25.07.22 13:56, Pali Rohár wrote:
Currently bank name is just one alphabetical letter.
Change it to mvebu and number.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/gpio/mvebu_gpio.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --gi
On 25.07.22 13:56, Pali Rohár wrote:
Device tree property "ngpios" contains number of gpios.
Use it when available.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/gpio/mvebu_gpio.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drive
On 25.07.22 13:56, Pali Rohár wrote:
To use particular pin GPIO, it needs to be first switched to GPIO by
pinctrl. Use pinctrl_gpio_request() and pinctrl_gpio_free() for this
purpose.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/gpio/mvebu_gpio.c | 5 ++
On 25.07.22 13:56, Pali Rohár wrote:
This change allows to use pinctrl_gpio_request() function as a direct
pointer for dm_gpio_ops's .request callback.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
drivers/pinctrl/pinctrl-uclass.c | 3 ++-
include/dm/pinctrl.h
On 25.07.22 13:56, Pali Rohár wrote:
This allows U-Boot mvebu-gpio.c driver to switch particular MPP pin into
GPIO mode and enable GPIO support.
Signed-off-by: Pali Rohár
Reviewed-by: Stefan Roese
Thanks,
Stefan
---
arch/arm/dts/armada-38x.dtsi | 2 ++
1 file changed, 2 insertions(+)
On 25.07.22 13:56, Pali Rohár wrote:
This new Armada 38x driver is based on Linux kernel driver. It can set any
pin to any valid function specified in DT like Linux kernel, it provides
support for 'pinmux status -a' command and also for pinctrl_gpio_request().
Signed-off-by: Pali Rohár
I'm ve
On 25.07.22 13:56, Pali Rohár wrote:
This new function pinctrl_generic_set_state_prefix() behaves like
pinctrl_generic_set_state() but it takes third string argument which is
used as the prefix for each device tree string property.
This is needed for Marvell pinctrl drivers, becase Linux device
Hi Fabio, Marcel, Tom,
The intuitive way to make ethernet work in case we do not know which phy is
assembled,and at what address it will be available, is having 3 phy nodes
in the dts, and setting all of their status fields to "okay" - so that they
would be probed in order until one succeeds.
This
On 27.07.22 20:40, Pali Rohár wrote:
On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
Hi Pali
On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
Linux kernel uses compatible string "marvell,armada370-nand-controller" for
nand controllers on Armada 370/XP/38x. U-Boot curre
The KConfig file was updated to indicate support for am57xx SoCs.
Logic was added to the pruss driver to enable the clock for am57xx pruss
during the driver probe function.
This patch depends on patches 0001 and 0004 of this patch series.
Signed-off-by: Greg Leonberg
---
drivers/soc/ti/Kconfi
Added the pruss subsystem to the device tree based on the device tree info
from the Linux kernel.
Signed-off-by: Greg Leonberg
---
arch/arm/dts/dra7.dtsi | 198 +
1 file changed, 198 insertions(+)
diff --git a/arch/arm/dts/dra7.dtsi b/arch/arm/dts
In order to support the am33xx pru_rproc, the KConfig needed to have the
depends updated to support either ARCH_K3 or ARCH_OMAP2PLUS. The Makefile
needed to be tweaked because when building for am33xx, the SPL will not fit
into SRAM if the pru_rproc driver is built into it.
The pru_rproc struct ud
Added the pruss subsystem to the device tree based on the device tree info
from the Linux kernel.
Signed-off-by: Greg Leonberg
---
arch/arm/dts/am33xx.dtsi | 105 +++
1 file changed, 105 insertions(+)
diff --git a/arch/arm/dts/am33xx.dtsi b/arch/arm/d
An integer flag in the private data structure for the udev was added to
indicate run-state. A function was also added to return that flag in order
for the driver to support the is_running driver function.
This patch depends on patch 0007 of this patch series.
Signed-off-by: Greg Leonberg
---
dr
The am57xx pru uses the same logic as the am33xx so it just needed to have
the struct udevice_id updated.
This patch depends on patch 0006 of this patch series.
Signed-off-by: Greg Leonberg
---
drivers/remoteproc/pru_rproc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/remotepr
The PRM_PER structure needs to be defined in order to allow the pruss
driver to bring the pru subsystem out of reset during the pruss
driver probe
Signed-off-by: Greg Leonberg
---
arch/arm/include/asm/arch-am33xx/cpu.h | 7 +++
arch/arm/include/asm/arch-am33xx/hardware_am33xx.h |
In order to support the am33xx pruss, the KConfig needed to have the
depends updated to support either ARCH_K3 or ARCH_OMAP2PLUS. The
Makefile needed to be tweaked because when building for am33xx, the
SPL will not fit into SRAM if the pruss driver is built into it.
Logic was added to the pruss dr
The pruicssclkctrl register needs to be added to the cm_perpll register
structure in order to allow the pruss driver to enable the clock for it
during the pruss probe function call on am33xx
This patch depends on patch 0002 of this patch series.
Signed-off-by: Greg Leonberg
---
arch/arm/include
This series adds support for the pruss/pru_rproc drivers on am33xx and
am57xx SoCs.
All PRU interfaces pru0 and pru1 are supported on am33xx.
All PRU interfaces pru0, pru1, pru2, and pru3 are supported on am57xx.
Testing is done via the "rproc" U-Boot command.
This patch series is based on ti-u-
The pruss1_clkctrl and pruss2_clkctrl registers need to be added to the
prcm register structure in order to allow the pruss driver to enable the
clock for each of them during the pruss probe function calls for am57xx
Signed-off-by: Greg Leonberg
---
arch/arm/include/asm/omap_common.h| 2 ++
On Wed, Jul 27, 2022 at 09:01:15PM +0200, Pali Rohár wrote:
> On Wednesday 27 July 2022 14:58:20 Tom Rini wrote:
> > On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> > > On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > > > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrot
On Wednesday 27 July 2022 14:58:20 Tom Rini wrote:
> On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> > On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > > > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > > >
On Wed, Jul 27, 2022 at 08:52:01PM +0200, Pali Rohár wrote:
> On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> > On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
On Wednesday 27 July 2022 14:48:23 Tom Rini wrote:
> On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> > On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
> > >
> > > > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PRE
On Wed, Jul 27, 2022 at 08:34:41PM +0200, Pali Rohár wrote:
> On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> > On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
> >
> > > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list.
> > > Value CONFIG_PREBOOT="run preboot"
Hi
Il mer 27 lug 2022, 20:43 Pali Rohár ha scritto:
> On Wednesday 27 July 2022 20:41:51 Michael Nazzareno Trimarchi wrote:
> > Hi
> >
> > Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
> >
> > > On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > > > Hi Pali
> > > >
> >
On Wednesday 27 July 2022 20:41:51 Michael Nazzareno Trimarchi wrote:
> Hi
>
> Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
>
> > On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > > Hi Pali
> > >
> > > On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> > > >
> > > >
Hi
Il mer 27 lug 2022, 20:40 Pali Rohár ha scritto:
> On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> > Hi Pali
> >
> > On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> > >
> > > Linux kernel uses compatible string
> "marvell,armada370-nand-controller" for
> > > nand
On Wednesday 27 July 2022 14:55:51 Michael Nazzareno Trimarchi wrote:
> Hi Pali
>
> On Wed, Jul 27, 2022 at 2:49 PM Pali Rohár wrote:
> >
> > Linux kernel uses compatible string "marvell,armada370-nand-controller" for
> > nand controllers on Armada 370/XP/38x. U-Boot currently uses mix of
> > "ma
On Monday 25 July 2022 17:21:00 Tom Rini wrote:
> On Sun, Jul 10, 2022 at 01:42:56PM +0200, Pali Rohár wrote:
>
> > CONFIG_PREBOOT just cause putting "preboot=CONFIG_PREBOOT" into env list.
> > Value CONFIG_PREBOOT="run preboot" in defconfig is just nonsense and does
> > not do anything useful (it
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC batte
Add u-boot,dm-spl and u-boot,dm-pre-reloc related properties
for Rockchip RV1126 SoC.
Both eMMC and SD boot are tested in Edge Compute Module 0.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rv1126-u-boot.dtsi | 62 +
1 file changed, 62 insertions(+)
create mode 10
Edge Compute Module 0 Carrier is an industrial form factor evaluation
board from Edgeble AI.
General features:
- microSD slot
- 2x MIPI CSI2 connectors
- MIPI DSI connector
- 2x USB Host
- 1x USB OTG
- Ethernet
- mini PCIe
- Onboard PoE
- RS485, RS232, CAN
- Micro Phone array
- Speaker
- RTC batte
Edge Compute Module 0 is a 96boards SoM-CB compute module based
on Rockchip RV1126 from Edgeble AI.
General features:
- Rockchip RV1126
- 2/4GB LPDDR4
- 16GB eMMC
- Fn-link 8223A-SR WiFi/BT
Edge Compute Module 0 needs to mount on top of Edgeble AI Carrier
boards for creating complete platform sol
Add support for rv1126 package header in mkimage tool.
Signed-off-by: Jagan Teki
---
tools/rkcommon.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 1325aa83cb..f18b6fad95 100644
--- a/tools/rkcommon.c
+++ b/tools/rkcommon.c
@@ -133,6 +133,7 @@ stat
Add common rv1126 include config.
Signed-off-by: Jagan Teki
---
include/configs/rv1126_common.h | 42 +
1 file changed, 42 insertions(+)
create mode 100644 include/configs/rv1126_common.h
diff --git a/include/configs/rv1126_common.h b/include/configs/rv1126_comm
Unsecure the dram area so that MMC, USB, and SFC controllers
can able to read data from dram.
Signed-off-by: Jason Zhu
Signed-off-by: Jagan Teki
---
arch/arm/mach-rockchip/rv1126/rv1126.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/arch/arm/mach-rockchip/rv1126/rv1126.c
Rockchip RV1126 is a high-performance vision processor SoC
for IPC/CVR, especially for AI related application.
Add arch core support for it.
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-rv1126/boot0.h | 11
arch/arm/include/asm/arch-rv1126/gpio.h | 11
arch/arm/m
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
It is based on quad-core ARM Cortex-A7 32-bit core which integrates
NEON and FPU. There is a 32KB I-cache and 32KB D-cache for each core
and 512KB unified L2 cache. It has build-in NPU supports IN
Add pinctrl definitions for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rv1126-pinctrl.dtsi | 302 +++
1 file changed, 302 insertions(+)
create mode 100644 arch/arm/dts/rv1126-pinctrl.dtsi
diff --git a/arch/arm/dts/rv1126-pinctrl.dtsi b/arch/arm/dts/
Add GRF header for Rockchip RV1126.
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/grf_rv1126.h| 251 ++
1 file changed, 251 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/grf_rv1126.h
diff --git a/arch/arm/include/asm/arch-rockchip/grf_rv1
Add the dt-bindings header for the Rockchip RV1126, that gets shared
between the clock controller and the clock references in the dts.
Signed-off-by: Finley Xiao
Signed-off-by: Jagan Teki
---
include/dt-bindings/clock/rv1126-cru.h | 632 +
1 file changed, 632 insertions(
Add clock driver support for Rockchip RV1126 SoC.
Signed-off-by: Joseph Chen
Signed-off-by: Jagan Teki
---
drivers/clk/rockchip/Makefile |1 +
drivers/clk/rockchip/clk_rv1126.c | 1889 +
2 files changed, 1890 insertions(+)
create mode 100644 drivers/clk/rock
Add power-domain header for RV1126 SoC from description in TRM.
Signed-off-by: Elaine Zhang
Signed-off-by: Jagan Teki
---
include/dt-bindings/power/rv1126-power.h | 35
1 file changed, 35 insertions(+)
create mode 100644 include/dt-bindings/power/rv1126-power.h
diff -
Add clock and reset unit header include for rv1126.
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/cru_rv1126.h| 459 ++
1 file changed, 459 insertions(+)
create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rv1126.h
diff --git a/arch/arm/include/asm/arch-
Add pinctrl driver for Rockchip RV1126.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
drivers/pinctrl/rockchip/Makefile | 1 +
drivers/pinctrl/rockchip/pinctrl-rv1126.c | 416 ++
2 files changed, 417 insertions(+)
create mode 100644 drivers/pinctrl/rockc
Some pins in rockchip are routed via Top GRF and PMU GRF
instead of direct regmap.
Add support to handle all these routing paths so that the
SoC pinctrl drivers will use them accordingly.
Signed-off-by: Jianqun Xu
Signed-off-by: Jagan Teki
---
drivers/pinctrl/rockchip/pinctrl-px30.c | 11
Add DDR driver for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../asm/arch-rockchip/dram_spec_timing.h | 452 +++
.../include/asm/arch-rockchip/sdram_common.h | 212 +
.../include/asm/arch-rockchip/sdram_msch.h| 12 +
.../asm/arch-rockchip/sdram_
Add LPDDR4 detection timings and support for RV1126.
Signed-off-by: Jagan Teki
---
.../sdram-rv1126-lpddr4-detect-1056.inc | 78 +++
.../sdram-rv1126-lpddr4-detect-328.inc| 78 +++
.../sdram-rv1126-lpddr4-detect-396.inc| 78 ++
Control the ddr init print messages via RAM_ROCKCHIP_DEBUG
instead of printing by default.
This gives an option to configs to enable these prints or
not.
Signed-off-by: Jagan Teki
---
drivers/ram/rockchip/sdram_rv1126.c | 38 +++--
1 file changed, 25 insertions(+), 13 de
Add DDR loader parameters for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../rockchip/sdram-rv1126-loader_params.inc | 198 ++
1 file changed, 198 insertions(+)
create mode 100644 drivers/ram/rockchip/sdram-rv1126-loader_params.inc
diff --g
Add DDR3 detection timings for Rockchip RV1126 SoC.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../sdram-rv1126-ddr3-detect-1056.inc | 72 +++
.../rockchip/sdram-rv1126-ddr3-detect-328.inc | 72 +++
.../rockchip/sdram-rv1126-ddr3-detect-396.
High row detection for non-8bit bw requires axi split.
So, update the existing high row detection code in order
to support full bw chips.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../include/asm/arch-rockchip/sdram_common.h | 2 +-
drivers/ram/rockchip/sdram_common.c
Add full ddr pctl registers and bit masks for px30.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
.../asm/arch-rockchip/sdram_pctl_px30.h | 100 +-
drivers/ram/rockchip/sdram_pctl_px30.c| 6 +-
2 files changed, 101 insertions(+), 5 deletions(-)
diff -
DDR chip capacity is computed based on GRF split in some
Rockchip SoC's like PX30 and RV1126.
Add split argument in ddr print info so-that the respective
ddr driver will pass the grf split.
Signed-off-by: YouMin Chen
Signed-off-by: Jagan Teki
---
arch/arm/include/asm/arch-rockchip/sdram_common
Rockchip PX30 has 16KB sram, bootrom reserved 4KB as stack.
Correct it.
Signed-off-by: Jagan Teki
---
tools/rkcommon.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/rkcommon.c b/tools/rkcommon.c
index 0db45c2d41..1325aa83cb 100644
--- a/tools/rkcommon.c
+++ b/tools/r
We have common ddr types in rockchip or in general. So use
the common ddr type names instead of per Rockchip SoC to
avoid confusion.
The respective ddr type names will use on the associated
ddr SoC driver as these drivers are built per SoC at a time.
Signed-off-by: Jagan Teki
---
board/engicam/
ram-uclass is building irrespective of whether TPL_DM
or SPL_DM is enabled. So control the ram uclass build
based on TPL/SPL_DM.
Signed-off-by: Jagan Teki
---
drivers/ram/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/ram/Makefile b/drivers/ram/Makefile
inde
From: Jagan Teki
RV1126 is a high-performance vision processor SoC for IPC/CVR,
especially for AI related application.
This patch series add basic core support for Rockchip RV1126
and boot from eMMC and SD.
Linux support is under review for the same [2].
Tested RV1126 in Edgeble AI Edge Comput
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
Add support for imx6ulz BSH SMM M2 board:
- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.
Signed-off-by: Michael Trimarchi
---
Changes V2->V3:
- remove CO
> Add binding header for i.MXRT1170 pinctrl device tree.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Den
> Add the clock binding doc for i.MXRT1170.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235
> The NXP i.MXRT1170 Evaluation Kit (EVK) provides a platform for rapid
> evaluation of the i.MXRT, which features NXP's implementation of the Arm
> Cortex-M7 and Cortex-M4 core.
> The EVK provides 64 MB SDRAM, Micro SD card socket,
> USB 2.0 OTG.
> This patch aims to support the preliminary bootin
> Add clock driver support for i.MXRT1170.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 M
> The i.MXRT11 series has two new pll types but are variants of existing.
> This patch adds the ability to read one of the pll types' frequency
> as it can't be changed unlike the generic pll it also has the
> division factors swapped.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, th
> Add a base defconfig for the i.MXRT1170
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX Software Engineering GmbH, Managing Director: Wolfgang Denk
HRB 165235 Mu
> This commit adds board support for i.MXRT1170-EVK from NXP. This board
> is an evaluation kit provided by NXP for i.MXRT117x processor family.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
==
> The i.MXRT11 series has different offsets for IOCR_MUX, it also can
> address 64MiB of SDRAM so add a macro for that.
> Signed-off-by: Jesse Taube
Applied to u-boot-imx, master, thanks !
Best regards,
Stefano Babic
--
=
DENX
pulled from kernel tag v5.18
---
scripts/config | 230 +
1 file changed, 230 insertions(+)
create mode 100755 scripts/config
diff --git a/scripts/config b/scripts/config
new file mode 100755
index 00..ff88e2faef
--- /dev/null
+++ b/scripts/
Hi Stefano
On Wed, Jul 27, 2022 at 5:02 PM Stefano Babic wrote:
>
> On 17.07.22 17:56, Michael Trimarchi wrote:
> > Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
> > imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
> >
> > Add support for imx6ulz BSH SMM M2 board:
> >
> > - 12
> Date: Wed, 27 Jul 2022 17:59:02 +0200
> From: Michal Simek
>
> On 7/27/22 16:34, Mark Kettenis wrote:
> > The contents of differ between OSes. It may only define
> > the relocation types for the host architecture, and may not contain
> > machine-specific defines for more obscure architectures
Hi Simon,
On Tue, Jul 26, 2022 at 01:53:44PM -0600, Simon Glass wrote:
> On Tue, 26 Jul 2022 at 10:25, John Keeping wrote:
> >
> > Upstream device trees now use standard node names like "gpio@ff..." but
> > the rk_gpio driver expects a name like "gpio0@ff..." (note the index
> > before the @).
>
On 7/27/22 17:07, Martin Bonner wrote:
Martin
On Wed, 27 Jul 2022 at 14:29, Heinrich Schuchardt mailto:xypron.g...@gmx.de>> wrote:
On 7/25/22 09:42, Martin Bonner wrote:
> * Add three more modules that are required.
> * Remove the version numbers (because they are hard to keep i
On 7/27/22 16:34, Mark Kettenis wrote:
The contents of differ between OSes. It may only define
the relocation types for the host architecture, and may not contain
machine-specific defines for more obscure architectures (such as
Microblaze) at all.
Define the relevant constants for Microblaz
In file included from include/linux/bitops.h:22,
from include/log.h:15,
from include/linux/printk.h:4,
from include/common.h:20,
from lib/lz4_wrapper.c:6:
lib/lz4_wrapper.c: In function ‘ulz4fn’:
include/linux/kernel.h:184:17: warn
On Wed, Jul 27, 2022 at 04:15:52PM +0100, Martin Bonner wrote:
> Martin
>
>
> On Wed, 27 Jul 2022 at 15:15, Tom Rini wrote:
>
> > On Wed, Jul 27, 2022 at 03:56:07PM +0200, Heinrich Schuchardt wrote:
> > > On 7/27/22 15:51, Heinrich Schuchardt wrote:
> > > > On 7/27/22 15:29, Heinrich Schuchardt
U-Boot for initial L2 SRAM uses L2 memory-mapping mode and not L2 with
locked lines. P2020 reference manual about L2 memory-mapping mode says:
Accesses to memory-mapped SRAM are cacheable only in the corresponding
e500 L1 caches.
So there is no need to set Caching-Inhibit I-bit for second par
Martin
On Wed, 27 Jul 2022 at 15:15, Tom Rini wrote:
> On Wed, Jul 27, 2022 at 03:56:07PM +0200, Heinrich Schuchardt wrote:
> > On 7/27/22 15:51, Heinrich Schuchardt wrote:
> > > On 7/27/22 15:29, Heinrich Schuchardt wrote:
> > > > On 7/25/22 09:42, Martin Bonner wrote:
> > > > > * Add three mo
As per https://github.com/actions/virtual-environments/issues/5583 the
macOS-10.15 image is being deprecated. Move us up to macOS-12.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.azure-pipelines.yml b/.azure-pipelines.yml
Martin
On Wed, 27 Jul 2022 at 14:29, Heinrich Schuchardt
wrote:
> On 7/25/22 09:42, Martin Bonner wrote:
> > * Add three more modules that are required.
> > * Remove the version numbers (because they are hard to keep in sync
> >with the latest MSYS2 versions)
> > * Add a pacman command line
On 17.07.22 17:56, Michael Trimarchi wrote:
Introduce BSH SystemMaster (SMM) M2 board family, which consists of:
imx6ulz SMM M2 and imx6ulz SMM M2 PRO boards.
Add support for imx6ulz BSH SMM M2 board:
- 128 MiB DDR3 RAM
- 256MiB Nand
- USBOTG1 peripheral - fastboot.
include/configs/imx6ulz_s
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