Dear Artem,
In message <2029043647.1251416-1-...@khadas.com> you wrote:
> Add possibility setup env variable with additional resolving vars inside
> value.
Hm... if you want to evaluate variables, you should not prevent the
shell to do that by enclosing them in apostrophes?
> Usage examples:
On 11/18/21 19:01, Pali Rohár wrote:
On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
overwrite read-only SAR PCIe registers") it is required to set Maximum Link
On 11/18/21 18:46, Pali Rohár wrote:
On Friday 12 November 2021 15:18:48 Stefan Roese wrote:
On 11/11/21 16:35, Marek Behún wrote:
From: Pali Rohár
Do not call pci_set_region() for resources which were not properly mapped.
This prevents U-Boot to access unmapped memory space.
Update MBUS_PCI
Add new tests for `setenv -r` options (setup env variable with additional
resolving vars inside value).
test.py -k test_env
Signed-off-by: Artem Lapkin
---
test/py/tests/test_env.py | 24
1 file changed, 24 insertions(+)
diff --git a/test/py/tests/test_env.py b/test/py
Add possibility setup env variable with additional resolving vars inside
value.
Usage examples:
=> setenv a hello; setenv b world; setenv c '${a} ${b}'
=> setenv -r d '${c}! ${a}...'
=> printenv d
d=hello world! hello...
/* internal usage example */
env_resolve("d", "${c}! ${a}...");
/* d="hello
Add possibility setup env variable with additional resolving vars inside
value.
Usage examples:
=> setenv a hello; setenv b world; setenv c '${a} ${b}'
=> setenv -r d '${c}! ${a}...'
=> printenv d
d=hello world! hello...
/* internal usage example */
env_resolve("d", "${c}! ${a}...");
/* d="hello
Update maintainer for MediaTek MIPS platform
Signed-off-by: Weijie Gao
---
v2 changes: none
---
MAINTAINERS | 5 +
1 file changed, 5 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 5069f18806..7d65856743 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -855,15 +855,20 @@ R:G
This patch adds GMAC support for MediaTek MT7621 SoC.
MT7621 has the same GMAC/Switch configuration as MT7623.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/net/mtk_eth.c | 27 +--
drivers/net/mtk_eth.h | 8
2 files changed, 29 insertions(+), 6 dele
This patch adds SDXC support for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/mmc/mtk-sd.c | 13 +
1 file changed, 13 insertions(+)
diff --git a/drivers/mmc/mtk-sd.c b/drivers/mmc/mtk-sd.c
index 8599f095bc..1199052a89 100644
--- a/drivers/mmc/mtk-sd
This patch makes mt7621_wdt driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/watchdog/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/watchdog/Kconfig b/drivers/watchdog/Kconfig
inde
This patch makes mt7621_gpio driver available for MediaTek MT7621 SoC
Reviewed-by: Stefan Roese
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/gpio/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpio/Kconfig b/drivers/gpio/Kconfig
index 40abc3377
This patch adds NAND flash controller driver for MediaTek MT7621 SoC.
The NAND flash controller of MT7621 supports only SLC NAND flashes.
It supports 4~12 bits correction with maximum 4KB page size.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/mtd/nand/raw/Kconfig | 11 +
d
This patch makes mt7621_spi driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/spi/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig
index d07e9a28af..a43e652231 100644
--- a/driv
This patch makes mtk-tphy driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/phy/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/phy/Kconfig b/drivers/phy/Kconfig
index 4767d215f3..6ab99d2643 100644
--- a/driver
This patch makes xhci-mtk driver available for MediaTek MT7621 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/usb/host/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig
index ccecb5a3b0..f2c060e692 1006
This patch adds pinctrl support for MediaTek MT7621 SoC.
The MT7621 SoC supports pinconf, but it is not the same as mt7628.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/pinctrl/mtmips/Kconfig| 9 +
drivers/pinctrl/mtmips/Makefile | 1 +
drivers/pin
This patch adds a clock driver for MediaTek MT7621 SoC.
This driver provides clock gate control as well as getting clock frequency
for CPU/SYS/XTAL and some peripherals.
Signed-off-by: Weijie Gao
---
v2 changes: none
---
drivers/clk/mtmips/Makefile| 1 +
drivers/clk/mtmips/clk-mt76
This patch adds reset controller bits definition header file for MediaTek
MT7621 SoC
Signed-off-by: Weijie Gao
---
v2 changes: none
---
include/dt-bindings/reset/mt7621-reset.h | 38
1 file changed, 38 insertions(+)
create mode 100644 include/dt-bindings/reset/mt7621-re
The mt7621_rfb board supports integrated giga PHYs plus one external
giga PHYs. It also has up to 512MiB DDR3, 16MB SPI-NOR, 3 mini PCI-e x1
slots, SDXC and USB.
The mt7621_nand_rfb board is almost the same as mt7621_rfb board, but it
uses NAND flash and SDXC is not available.
Reviewed-by: Daniel
This patch adds support for MediaTek MT7621 SoC.
All files are dedicated for u-boot.
Currently only ramboot is supported.
The default build target is u-boot-lzma.img.
This file can be booted using bootm command, or be used as a payload of the
SDK preloader of MT7621.
The specification of this chi
This series will add support for MediaTek MT7621 SoC with two reference boards
and related drivers.
The MediaTek MT7621 is a network processor integrating a dual-core
dual-threaded MIPS 1004Kc processor running at a normal frequency of 880MHz.
This chip can be found in many wireless routers.
This
On Fri, Nov 19, 2021 at 08:56:08AM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Fri, Nov 19, 2021 at 3:14 AM Tom Rini wrote:
> >
> > On Tue, Oct 19, 2021 at 10:40:53AM +0800, Jon Lin wrote:
> >
> > > Most NVME devcies maintain data in internal cache for an uncertain
> > > times, and u-boot has no meth
Hi Tom,
On Fri, Nov 19, 2021 at 3:14 AM Tom Rini wrote:
>
> On Tue, Oct 19, 2021 at 10:40:53AM +0800, Jon Lin wrote:
>
> > Most NVME devcies maintain data in internal cache for an uncertain
> > times, and u-boot has no method to force NVME to flush cache.
> > So this patch adds FUA to avoid data
Hi,
Op 17-11-2021 om 18:15 schreef Andy Shevchenko:
socat is a very powerful tool to work with socets (and not only)
in UNIX systems. Let's add support for it in netconsole.
Signed-off-by: Andy Shevchenko
Tested-by: Ferry Toth
---
tools/netconsole | 12 ++--
1 file changed, 10 in
On Thu, Nov 18, 2021 at 02:45:25PM +0900, Masami Hiramatsu wrote:
> Without default setting of gd->env_addr, U-Boot will cause
> a synchronous abort if the env-variables on the SPI flash is
> broken or not saved corectly. Set gd->env_addr correctly.
>
> This reverts commit 535870f3b0fb09ee9b28854
On Sat, Nov 13, 2021 at 06:34:59PM +0100, marek.va...@gmail.com wrote:
> From: Marek Vasut
>
> In case U-Boot enters relocation with GD_FLG_SKIP_RELOC, skip the
> relocation. The code still has to set up new_gd pointer and new
> stack pointer.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
On Sat, Nov 13, 2021 at 06:34:37PM +0100, marek.va...@gmail.com wrote:
> From: Marek Vasut
>
> In case U-Boot starts with GD_FLG_SKIP_RELOC, the U-Boot code is
> not relocated, however the stack and heap is at the end of DRAM
> after relocation. Reserve a LMB area for the non-relocated U-Boot
>
On Sat, Nov 13, 2021 at 06:34:04PM +0100, marek.va...@gmail.com wrote:
> From: Marek Vasut
>
> Even if U-Boot has relocation disabled via GD_FLG_SKIP_RELOC , the
> relocated stage of U-Boot still picks GD from new_gd location. The
> U-Boot itself is not relocated, but GD might be, so copy the GD
On Wed, Oct 20, 2021 at 08:15:55PM +0800, schspa wrote:
> In some case, get_info() interface can be NULL, add this check to stop
> from crash.
>
> Signed-off-by: schspa
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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Hi ZHIZHIKIN
On Thu, Nov 18, 2021 at 7:53 PM ZHIZHIKIN Andrey
wrote:
>
> Hello Michael,
>
> > -Original Message-
> > From: U-Boot On Behalf Of Michael Trimarchi
> > Sent: Thursday, November 18, 2021 2:58 PM
> > To: Ye Li ; Stefano Babic ; Fabio Estevam
> >
> > Cc: u-boot@lists.denx.de;
Hi
Yes git bisect
Michael
On Thu, Nov 18, 2021 at 7:39 PM Piotr Lobacz wrote:
>
> By bisect, you mean find the commit responsible for this?
>
> BR
> Peter
>
> Od: Michael Nazzareno Trimarchi
> Wysłano: czwartek, listopada 18, 2021 2:33 PM
> Do: Piotr Lobacz
> D
On Thu, Nov 18, 2021 at 03:26:40PM -0600, Adam Ford wrote:
> On Thu, Nov 18, 2021 at 3:12 PM Tom Rini wrote:
> >
> > On Wed, Nov 17, 2021 at 08:08:10AM -0600, Adam Ford wrote:
> >
> > > On Fri, Oct 22, 2021 at 2:36 PM Adam Ford wrote:
> > > >
> > > > On Wed, Sep 29, 2021 at 8:26 AM Adam Ford wro
On Thu, Nov 18, 2021 at 3:12 PM Tom Rini wrote:
>
> On Wed, Nov 17, 2021 at 08:08:10AM -0600, Adam Ford wrote:
>
> > On Fri, Oct 22, 2021 at 2:36 PM Adam Ford wrote:
> > >
> > > On Wed, Sep 29, 2021 at 8:26 AM Adam Ford wrote:
> > > >
> > > > On Thu, Sep 23, 2021 at 3:03 PM Adam Ford wrote:
> >
On Wed, Nov 17, 2021 at 08:08:10AM -0600, Adam Ford wrote:
> On Fri, Oct 22, 2021 at 2:36 PM Adam Ford wrote:
> >
> > On Wed, Sep 29, 2021 at 8:26 AM Adam Ford wrote:
> > >
> > > On Thu, Sep 23, 2021 at 3:03 PM Adam Ford wrote:
> > > >
> > > > On Tue, Sep 14, 2021 at 9:49 PM Peng Fan (OSS)
>
On Thu, Nov 18, 2021 at 08:04:22PM +0100, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <2028162920.GH24579@bill-the-cat> you wrote:
> >
> > > It is perfectly OK for U-Boot to start with a random MAC address,
> > > use this for a while, and change it so something else later. This
> > > is
On 11/17/21 3:41 AM, qianfan wrote:
在 2021/11/16 23:05, Sean Anderson 写道:
On 11/15/21 8:35 PM, qianfangui...@qq.com wrote:
From: qianfan Zhao
CHUNK_TYPE_RAW buffer is not aligned, and flash sparse images by
fastboot will report "Misaligned operation" if DCACHE is enabled.
Flashing Spar
On Wed, Nov 03, 2021 at 07:16:08AM -0600, Simon Glass wrote:
> Some boards do not enable SPL_SERIAL so cannot use the debug UART. Add
> this condition to the code and drop use of the preprocessor while we are
> here.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Philipp Tomsich
Applied to u-bo
On Wed, Nov 03, 2021 at 07:16:07AM -0600, Simon Glass wrote:
> Enable this to permit early debugging. Due to the way qmeu works, the
> input clock can be zero and things still work.
>
> Signed-off-by: Simon Glass
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Nov 03, 2021 at 07:16:06AM -0600, Simon Glass wrote:
> At present we don't init the debug UART in the generic ARM code, but
> instead leave it to individual machines to handle. This is not the
> way it is supposed to work.
>
> Add the required init to the crt files. This ensures that the
On Wed, Oct 27, 2021 at 02:17:24PM +0800, Chia-Wei Wang wrote:
> Fix inconsistent function parameter name of the hash algorithm.
>
> Signed-off-by: Chia-Wei Wang
> Fixes: 92055e138f2 ("image: Drop if/elseif hash selection in
> calculate_hash()")
> Reviewed-by: Joel Stanley
> Reviewed-by: Simon
On Fri, Nov 05, 2021 at 02:34:14PM +0100, Julien Masson wrote:
> With the recent changes on mmc driver, we saw that the boot is ~5 secs
> longer compared to v2021.07 on mediatek platforms.
>
> This regression is seen during mmc_init and caused by the following
> patch [1].
>
> Indeed since we di
On Wed, Nov 03, 2021 at 07:16:05AM -0600, Simon Glass wrote:
> A few boards enable CONFIG_DEBUG_UART_BOARD_INIT but do not define the
> required init function. Fix this by disabling the debug UART.
>
> With snow the debug UART is enabled but the driver CONFIG is not. Fix this
> too.
>
> Signed-o
On Tue, Nov 02, 2021 at 06:21:57PM +0100, Mark Kettenis wrote:
> This driver supports both pin muxing and GPIO support for the
> pin control logic found on Apple SoCs.
>
> Signed-off-by: Mark Kettenis
Applied to u-boot/next, thanks!
--
Tom
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On Tue, Nov 02, 2021 at 10:17:52AM +0800, Dylan Hung wrote:
> From: Ryan Chen
>
> This driver uses Pinctrl framework and is compatible with the Linux
> driver for AST2600.
>
> Signed-off-by: Ryan Chen
> Signed-off-by: Dylan Hung
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Nov 03, 2021 at 01:01:05AM +0100, Pali Rohár wrote:
> Lot of PCIe controllers are using ECAM addressing. So add common ECAM
> macros into U-Boot's pci.h header file which can be suitable for most
> PCI controller drivers.
>
> Replace custom ECAM address macros in every PCI controller driv
On Wed, Oct 20, 2021 at 09:31:34PM +, Alistair Delva wrote:
> When booting U-Boot in crosvm, the virtual machine emulates a PCI cam
> device, not the PCI-E 'ecam' device normally seen on e.g. QEMU. This
> PCI device can be supported with only trivial changes to the ecam
> driver.
>
> Instead
On Wed, Oct 20, 2021 at 09:09:13PM +0530, Aswath Govindraju wrote:
> Add configs to enable serdes for USB 3.0 support.
>
> Signed-off-by: Aswath Govindraju
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Oct 20, 2021 at 09:02:02PM +0530, Aswath Govindraju wrote:
> Add new compatible for AM64 SoC.
>
> Signed-off-by: Aswath Govindraju
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Oct 20, 2021 at 09:09:12PM +0530, Aswath Govindraju wrote:
> From: Kishon Vijay Abraham I
>
> Add and Enable USB SuperSpeed Host Port in SPL.
>
> Signed-off-by: Kishon Vijay Abraham I
> Signed-off-by: Aswath Govindraju
Applied to u-boot/next, thanks!
--
Tom
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On Wed, Oct 20, 2021 at 08:58:57PM +0530, Aswath Govindraju wrote:
> Search for "phy" in the subnode names, to syncup with kernel.
>
> Signed-off-by: Aswath Govindraju
Applied to u-boot/next, thanks!
--
Tom
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On Tue, Oct 19, 2021 at 10:40:54AM +0800, Jon Lin wrote:
> Consulting to "NVM Express® Base Specification, revision 2.0".
>
> If more PRP List pages are required, then the last entry of
> the PRP List contains the Page Base Address of the next PRP
> List page. The next PRP List page shall be memo
On Tue, Oct 19, 2021 at 10:40:53AM +0800, Jon Lin wrote:
> Most NVME devcies maintain data in internal cache for an uncertain
> times, and u-boot has no method to force NVME to flush cache.
> So this patch adds FUA to avoid data loss caused by power off after data
> programming.
>
> Signed-off-by
Dear Tom,
In message <2028162920.GH24579@bill-the-cat> you wrote:
>
> > It is perfectly OK for U-Boot to start with a random MAC address,
> > use this for a while, and change it so something else later. This
> > is what may happen at production: say the MAC address is stored in
> > some EEPR
Hello Michael,
> -Original Message-
> From: U-Boot On Behalf Of Michael Trimarchi
> Sent: Thursday, November 18, 2021 2:58 PM
> To: Ye Li ; Stefano Babic ; Fabio Estevam
>
> Cc: u-boot@lists.denx.de; Ariel D'Alessandro
> ;
> linux-amar...@amarulasolutions.com; Anthony Brandon
>
> Subje
By bisect, you mean find the commit responsible for this?
BR
Peter
Od: Michael Nazzareno Trimarchi
Wysłano: czwartek, listopada 18, 2021 2:33 PM
Do: Piotr Lobacz
DW: u-boot@lists.denx.de
Temat: Re: [BUG] firefly-rk3399 tpl/spl with optee from tag v2020.07 hangs on
From: David Rivshin
In the case of an erased (sub)page both the data and ECC are all 0xFF
bytes. This fails the normal ECC verification, as the computed ECC of
all-0xFF is not also 0xFF. The GPMC NAND driver attempted to detect
erased pages by checking that the ECC bytes are all-0xFF, but this ha
On Friday 12 November 2021 14:59:31 Stefan Roese wrote:
> > diff --git a/drivers/pci/pci_mvebu.c b/drivers/pci/pci_mvebu.c
> > index 14cd82db6f..a3364d5a59 100644
> > --- a/drivers/pci/pci_mvebu.c
> > +++ b/drivers/pci/pci_mvebu.c
> > @@ -22,6 +22,7 @@
> > #include
> > #include
> > #include
On Friday 12 November 2021 15:01:57 Stefan Roese wrote:
> On 11/11/21 16:35, Marek Behún wrote:
> > From: Pali Rohár
> >
> > As explained in commit 3bedbcc3aa18 ("arm: mvebu: a38x: serdes: Don't
> > overwrite read-only SAR PCIe registers") it is required to set Maximum Link
> > Width bits of PCIe
From: Rayagonda Kokatanur
IPROC qspi driver supports both BSPI and MSPI modes.
Signed-off-by: Rayagonda Kokatanur
Signed-off-by: Bharat Gooty
Acked-by: Rayagonda Kokatanur
Signed-off-by: Roman Bacik
---
Changes in v7:
- remove hardcorded IPROC_BSPI_READ_DUMMY_CYCLES
- remove unnecessary fl
On Friday 12 November 2021 15:18:48 Stefan Roese wrote:
> On 11/11/21 16:35, Marek Behún wrote:
> > From: Pali Rohár
> >
> > Do not call pci_set_region() for resources which were not properly mapped.
> > This prevents U-Boot to access unmapped memory space.
> >
> > Update MBUS_PCI_MEM_SIZE and M
On Wed, Nov 17, 2021 at 1:25 PM Roman Bacik wrote:
>
> From: Rayagonda Kokatanur
>
> IPROC qspi driver supports both BSPI and MSPI modes.
>
> Signed-off-by: Rayagonda Kokatanur
> Signed-off-by: Bharat Gooty
> Acked-by: Rayagonda Kokatanur
>
> Signed-off-by: Roman Bacik
> ---
>
> Changes in v6
On Thu, Nov 18, 2021 at 08:08:14AM +0100, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <2027161545.GA24579@bill-the-cat> you wrote:
> >
> > Yes, you're changing behavior by requiring this change, and fwiw I
> > suggested a slightly different fix-up here of deleting the device tree
> > prop
On Thu, Nov 18, 2021 at 09:29:51AM +0100, Michael Walle wrote:
> Am 2021-11-17 19:24, schrieb Tom Rini:
> > On Wed, Nov 17, 2021 at 05:45:58PM +0100, Michael Walle wrote:
> > > Am 2021-11-16 22:14, schrieb Tom Rini:
> > > > On Mon, Nov 15, 2021 at 11:45:51PM +0100, Michael Walle wrote:
> > > >
> >
On Thu, Nov 18, 2021 at 10:46:28AM +0100, Wolfgang Denk wrote:
> Dear Tom,
>
> In message <1889944.1637219...@gemini.denx.de> I wrote:
> >
> > > We're about to
> > > introduce the 3rd variant. I'd feel a whole lot better about taking in
> > > a v2 of this patch that correct the help (and maybe up
On Mon, 15 Nov 2021 at 19:21, Heinrich Schuchardt
wrote:
>
> Encapsulate the UEFI EFI_TCG2_PROTOCOL unit test in an Python test.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> This patch should be merged after
>
> [PATCH 1/1] tpm: clear state post probing
> https://lists.denx.de/pipermail/u-boot/
On Thu, 18 Nov 2021, Maciej W. Rozycki wrote:
> "Use the Data Link Layer Link Active status flag as the primary indicator
> of successful link speed negotiation, but given that the flag is optional
> by hardware to implement (the ASM2824 does have it though) [...]"
NB I did verify the change t
Hi Roman,
Thank you for your patch.
Sean Anderson writes:
> On 5/8/21 6:25 PM, Roman Stratiienko wrote:
>> In case CONFIG_FASTBOOT_FLASH_MMC_DEV == 0, compile-time condition
>> is not met and fastboot_set_reboot_flag() fails.
>>
>> Fixes: a362ce214f03 ("fastboot: Implement generic fastboot_set
Add support of secondary boot address for imx8mn. The secondary
boot address is hardcoded in the fuse. The value is calculated
from there according to the following description:
The fuse IMG_CNTN_SET1_OFFSET (0x490[22:19]) is defined as follows:
• Secondary boot is disabled if fuse value is bigger
This function defined for two architecture is not really clean
and can be generate problem when people add a new board
Signed-off-by: Michael Trimarchi
---
arch/arm/mach-imx/imx8m/soc.c | 42 ---
1 file changed, 42 deletions(-)
diff --git a/arch/arm/mach-imx/imx8
On Thu, 18 Nov 2021 14:45:25 +0900
Masami Hiramatsu wrote:
> Without default setting of gd->env_addr, U-Boot will cause
> a synchronous abort if the env-variables on the SPI flash is
> broken or not saved corectly. Set gd->env_addr correctly.
>
> This reverts commit 535870f3b0fb09ee9b2885409f053
Hi
On Thu, Nov 18, 2021 at 2:29 PM Piotr Lobacz wrote:
>
> Hi all,
> as in subject when using tpl/spl with u-boot master branch and atf/optee (atf
> v2.5 and optee 3.15.0) on firefly-rk3399 board causes hang out on booting the
> kernel. The problem does not persist with optee 3.7.0 and more ove
Hi all,
as in subject when using tpl/spl with u-boot master branch and atf/optee (atf
v2.5 and optee 3.15.0) on firefly-rk3399 board causes hang out on booting the
kernel. The problem does not persist with optee 3.7.0 and more over, with uboot
<=v2020.04 and optee 3.15.0, the problem does not pe
Hi Stefan,
> > > I would like to hear what Bjorn Helgaas thinks about this issue at all
> > > and how to handle it, without potentially break something else. And
> > > based on the fact that in U-Boot's PCI core code there is no such global
> > > quirk implemented, I really do not know if U-Boot m
Remove clock-names from GEM nodes from clk-ccf because they should be only
present in zynqmp.dtsi. And as is visible both clock-names defined didn't
really match.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp-clk-ccf.dtsi | 4
arch/arm/dts/zynqmp.dtsi | 8
2 files ch
There is a need to get IP out of reset to operate properly.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi
index 07d4d4b91201..2264a80e3312 100644
--- a/arch/arm/dts/zynqmp.dtsi
u-boot,dm-pre-reloc is necessary for DP driver to allocate enough space for
framebuffer before relocation.
Power domain driver is called when video console is used for example by
loading BMP image.
Signed-off-by: Michal Simek
---
arch/arm/dts/zynqmp.dtsi | 1 +
1 file changed, 1 insertion(+)
d
On 10/29/21 13:13, Michal Simek wrote:
gemX_ref clock IDs starts at number 104. Till now it was at gemX_tx
location which wasn't correct.
Signed-off-by: Michal Simek
---
drivers/clk/clk_zynqmp.c | 23 ++-
1 file changed, 18 insertions(+), 5 deletions(-)
diff --git a/
On 10/29/21 13:13, Michal Simek wrote:
USB range is not enabled but for setting up frequency it is needed.
Signed-off-by: Michal Simek
---
drivers/clk/clk_zynqmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/clk/clk_zynqmp.c b/drivers/clk/clk_zynqmp.c
index 52fecec7a7a9..
On 10/29/21 13:11, Michal Simek wrote:
From: T Karthik Reddy
ZynqMP modepin driver has capability to get/set/check status of modepin
gpios. These modepins are accessed using xilinx firmware. In modepin
register, [3:0] bits set direction, [7:4] bits read IO, [11:8] bits
set/clear IO.
Signed-
Why is my question not posted to the mailing list?
Regards,
Vishal Chopra
+91-7837583269
On Thu, Nov 18, 2021 at 3:44 PM vish chopra wrote:
> Hi All,
>
> Trying to enable MMU in uboot. But Hard hang in this function.
> Any lead why its hang after on this function.
>
> More precisely, when enabl
Add PSGTR driver for Xilinx ZynqMP.
The most of configurations are taken from Linux kernel psgtr driver.
USB3.0 and SGMII configurations are tested on SOM. In SGMII case also
IOU_SLCR reg is updated to get proper clock setup and signal detection
configuration.
Signed-off-by: Michal Simek
---
M
SGMII configuration depends on proper GT setting that's why when node has
phys property call PSGTR driver to configure it properly.
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 16
1 file changed, 16 insertions(+)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/z
Perform reset before core initialization.
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 26 ++
1 file changed, 26 insertions(+)
diff --git a/drivers/net/zynq_gem.c b/drivers/net/zynq_gem.c
index 91957757727d..5cbe8d28304b 100644
--- a/drivers/net/zynq_gem.c
+
There are flying two configurations around.
The first (already supported) has phy as subnode of gem node.
The second has mdio subnode (with mdio name) which has phy subnode.
This patch adds support for the second case where mdio subnode
is found driver will look at its parent to find out which gem
From: Ashok Reddy Soma
Timeout for checking mdio phy idle status is 20seconds. In case of errors
this timeout will be too much. Reduce it to 100ms.
Signed-off-by: Ashok Reddy Soma
Signed-off-by: Michal Simek
---
drivers/net/zynq_gem.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(
Using clock-frequency property to define desired clock speed for
controllers.
Signed-off-by: Michal Simek
---
drivers/mmc/zynq_sdhci.c | 10 ++
1 file changed, 10 insertions(+)
diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 5cea4c695e8d..ee87907939fe 100644
---
Core function should make sure that data is stored properly that's why move
cache operations directly to zynqmp_pmufw_load_config_object() to be able
to call it from other functions.
Signed-off-by: Michal Simek
---
board/xilinx/zynqmp/cmds.c | 1 -
drivers/firmware/firmware-zynqmp.c | 3
Previous psu init was targeting SOM + KV260 carrier card and also contain
configurations for other devices on carrier card. This config is removing
all expected configurations for CC and let U-Boot to handle all of it self.
This configuration is designed for SOM itself (and I would bet without
eMMC
From: T Karthik Reddy
Fix the sdhci node name in versal board file as per the name in
device tree and also check for sdhci node as part of backward
compatibility.
Signed-off-by: T Karthik Reddy
Signed-off-by: Michal Simek
---
board/xilinx/versal/board.c | 6 ++
1 file changed, 6 insertio
Hello Fabio,
Em qui., 18 de nov. de 2021 às 08:36, Fabio Estevam
escreveu:
> On Thu, Nov 18, 2021 at 8:33 AM Otavio Salvador
> wrote:
> >
> > Em qui., 18 de nov. de 2021 às 07:06, Fabio Estevam
> > escreveu:
> > > According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
> > > have the ESA
Hi Otavio,
On Thu, Nov 18, 2021 at 8:33 AM Otavio Salvador
wrote:
>
> Em qui., 18 de nov. de 2021 às 07:06, Fabio Estevam
> escreveu:
> > According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
> > have the ESAI_TX0 functionality, not ESAI_T0.
> >
> > Also, NXP's i.MX Config Tools 10.0 ge
Em qui., 18 de nov. de 2021 às 07:06, Fabio Estevam
escreveu:
> According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
> have the ESAI_TX0 functionality, not ESAI_T0.
>
> Also, NXP's i.MX Config Tools 10.0 generates dtsi with the
> MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming.
>
> Add an entry f
Hi All,
Trying to enable MMU in uboot. But Hard hang in this function.
Any lead why its hang after on this function.
More precisely, when enabling MMU in sctlr register.
I'm using ARMv8 A65 AARCH64.
Regards,
Vishal Chopra
+91-7837583269
Adding Macronix Octal flash for Octal DTR support.
The octaflash series can be divided into the following types:
MX25 series : Serial NOR Flash.
MX66 series : Serial NOR Flash with stacked die.(Size larger than 1Gb)
LM/UM series : Up to 250MHz clock frequency with both DTR/STR operation.
LW/UW se
Power-on-Reset is a method to restore flash back to 1S-1S-1S mode from 8D-8D-8D
in the begging of probe.
Command extension type is not standardized across flash vendors in DTR mode.
For suiting different vendor flash devices, adding a flag to seperate types for
soft reset on boot.
Signed-off-by:
Follow patch "f6adec1af4b2f5d3012480c6cdce7743b74a6156" for adding
Macronix flash in Octal DTR mode.
Enable Octal DTR mode with 20 dummy cycles to allow running at the
maximum supported frequency.
-https://www.mxic.com.tw/Lists/Datasheet/Attachments/7841/MX25LM51245G,%203V,%20512Mb,%20v1.1.pdf
This series add support for Macronix octal DTR flash, add flag for
Softreset with "INVERT" command extension type on boot and follow
linux kernel to enable 4byte opcode when possible.
v5:
Replace SPI_FLASH_MACRONIX_OCTAL with SPI_FLASH_MACRONIX.
Remove patch of set_4byte opcode.
v4:
Add fla
According to the i.MX6ULL Reference Manual, pad CSI_DATA07 may
have the ESAI_TX0 functionality, not ESAI_T0.
Also, NXP's i.MX Config Tools 10.0 generates dtsi with the
MX6ULL_PAD_CSI_DATA07__ESAI_TX0 naming.
Add an entry for the correct name and still keep the old one to
avoid potential breakage.
Dear Tom,
In message <1889944.1637219...@gemini.denx.de> I wrote:
>
> > We're about to
> > introduce the 3rd variant. I'd feel a whole lot better about taking in
> > a v2 of this patch that correct the help (and maybe updates
> > doc/README.enetaddr!) if someone could report back on what's going
Am 2021-11-17 19:24, schrieb Tom Rini:
On Wed, Nov 17, 2021 at 05:45:58PM +0100, Michael Walle wrote:
Am 2021-11-16 22:14, schrieb Tom Rini:
> On Mon, Nov 15, 2021 at 11:45:51PM +0100, Michael Walle wrote:
>
> > Nowadays, u-boot (when CONFIG_NET_RANDOM_ETHADDR is set) will set
> > enetaddr to a
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