[PATCH] sdhci: zynqmp: Setting up clock frequency based on DT

[Michal Simek]

Using clock-frequency property to define desired clock speed for
controllers.

Signed-off-by: Michal Simek <michal.si...@xilinx.com>
---

 drivers/mmc/zynq_sdhci.c | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c
index 5cea4c695e8d..ee87907939fe 100644
--- a/drivers/mmc/zynq_sdhci.c
+++ b/drivers/mmc/zynq_sdhci.c
@@ -58,6 +58,7 @@ struct arasan_sdhci_plat {
 struct arasan_sdhci_priv {
        struct sdhci_host *host;
        struct arasan_sdhci_clk_data clk_data;
+       u32 frequency;
        u8 deviceid;
        u8 bank;
        u8 no_1p8;
@@ -721,6 +722,14 @@ static int arasan_sdhci_probe(struct udevice *dev)
                return ret;
        }
 
+       if (priv->frequency) {
+               ret = clk_set_rate(&clk, priv->frequency);
+               if (IS_ERR_VALUE(ret)) {
+                       dev_err(dev, "failed to set clock rate\n");
+                       return ret;
+               }
+       }
+
        clock = clk_get_rate(&clk);
        if (IS_ERR_VALUE(clock)) {
                dev_err(dev, "failed to get rate\n");
@@ -804,6 +813,7 @@ static int arasan_sdhci_of_to_plat(struct udevice *dev)
        if (IS_ERR(priv->host->ioaddr))
                return PTR_ERR(priv->host->ioaddr);
 
+       priv->frequency = dev_read_u32_default(dev, "clock-frequency", 0);
        priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
        priv->bank = dev_read_u32_default(dev, "xlnx,mio-bank", 0);
        priv->no_1p8 = dev_read_bool(dev, "no-1-8-v");
-- 
2.33.1