On 7/15/21 7:00 PM, Ilias Apalodimas wrote:
Since we removed embeddingg the capsule key into a .dtb and fixed
authenticated capsule updates for all boards, move the relevant
documentation in the efi file and update it accordingly
Signed-off-by: Ilias Apalodimas
---
doc/board/emulation/qemu_ca
On Thu, 15 Jul 2021 at 22:30, Ilias Apalodimas
wrote:
> The capsule signature is now part of our DTB. This is problematic when a
> user is allowed to change/fixup that DTB from U-Boots command line since he
> can overwrite the signature as well.
> So Instead of adding the key on the DTB, embed i
On 7/14/21 7:19 AM, Masami Hiramatsu wrote:
Use %pD to log device-path instead of using efi_dp_str() and
efi_free_pool() locally in find_boot_device().
This is a cleanup patch, no feature update nor fix.
Suggested-by: Heinrich Schuchardt
Signed-off-by: Masami Hiramatsu
Reviewed-by: Heinrich
On 4/22/21 6:09 PM, Pali Rohár wrote:
BIOS Release Date must be in format mm/dd/ and must be release date.
%s/BIOS/The SMBIOS/
Please add a reference to the System Management BIOS (SMBIOS) Reference
Specification here an as comment in the code.
U-Boot currently sets BIOS Release Date fro
2021年7月16日(金) 2:00 Ilias Apalodimas :
>
> commit 322c813f4bec ("mkeficapsule: Add support for embedding public key in a
> dtb")
> added a bunch of options enabling the addition of the capsule public key
> in a dtb. Since now we embeded the key in U-Boot's .rodata we don't this
> this functionalit
Enable SPL FIT image load and verification support.
The HW accelerated SHA is also available with the
newly added support of the HACE HW hash engine.
Signed-off-by: Chia-Wei Wang
---
configs/evb-ast2600_defconfig | 24 +---
1 file changed, 21 insertions(+), 3 deletions(-)
di
2021年7月16日(金) 2:00 Ilias Apalodimas :
>
> The capsule signature is now part of our DTB. This is problematic when a
> user is allowed to change/fixup that DTB from U-Boots command line since he
> can overwrite the signature as well.
> So Instead of adding the key on the DTB, embed it in the u-boot
Move CONFIG_EXTRA_ENV_SETTINGS to board-specific
configuration headers.
Signed-off-by: Chia-Wei Wang
---
include/configs/aspeed-common.h | 9 -
include/configs/evb_ast2500.h | 6 ++
include/configs/evb_ast2600.h | 6 ++
3 files changed, 12 insertions(+), 9 deletions(-)
diff
AST2600 leverages the FIT hash/signature verification to fulfill
secure boot trust chain. To improve the performance and save SW
code size for those crypto operations, the two HW crypto engine,
HACE and ARCY, are enabled.
However, both of the engines can only access to data stored in
DRAM space. T
From: Joel Stanley
Add HACE DTS node and enable it for AST2600 EVB.
Signed-off-by: Joel Stanley
Signed-off-by: Chia-Wei Wang
---
arch/arm/dts/ast2600-evb.dts | 5 +
arch/arm/dts/ast2600.dtsi| 8
2 files changed, 13 insertions(+)
diff --git a/arch/arm/dts/ast2600-evb.dts b/ar
From: Joel Stanley
Currently the FIT verification calls directly into
SW implemented functions to get a CRC/SHA/MD5 hash.
This patch removes duplcated algorithm lookup and use
hash_lookup_algo to get the hashing function with HW
accelearation supported if configured.
The MD5 direct call remains
Return CONFIG_SYS_LOAD_ADDR pointing to DRAM space for
spl_get_load_buffer() to allow generic SPL image loading
code (e.g. FIT and Ymodem) to store data in DRAM.
Signed-off-by: Chia-Wei Wang
---
arch/arm/mach-aspeed/ast2600/spl.c | 9 +
1 file changed, 1 insertion(+), 8 deletions(-)
dif
Add ARCY DTS node and enable it for AST2600 EVB.
Signed-off-by: Chia-Wei Wang
---
arch/arm/dts/ast2600-evb.dts | 5 +
arch/arm/dts/ast2600.dtsi| 9 +
2 files changed, 14 insertions(+)
diff --git a/arch/arm/dts/ast2600-evb.dts b/arch/arm/dts/ast2600-evb.dts
index adb80a30ef..fd4e
Add RSACLK enable for ARCY, the HW RSA/ECC crypto engine
of ASPEED AST26xx SoCs.
Signed-off-by: Chia-Wei Wang
---
arch/arm/include/asm/arch-aspeed/scu_ast2600.h | 1 +
drivers/clk/aspeed/clk_ast2600.c | 15 +++
2 files changed, 16 insertions(+)
diff --git a/arch/arm/i
Probe ARCY driver in SPL board init if enabled.
Signed-off-by: Chia-Wei Wang
---
arch/arm/mach-aspeed/ast2600/spl.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-aspeed/ast2600/spl.c
b/arch/arm/mach-aspeed/ast2600/spl.c
index a0fc420ff1..2172bb4ae7 100644
--- a/arch/ar
ARCY is deisnged to accerlerate ECC/RSA digital signature
generation and verification.
Signed-off-by: Chia-Wei Wang
---
drivers/crypto/aspeed/Kconfig | 10 ++
drivers/crypto/aspeed/Makefile | 1 +
drivers/crypto/aspeed/aspeed_arcy.c | 182
lib/rsa/Kconf
The AST2600 SRAM has been extended to 88KB since A1
chip revision. This patch updates the SRAM size to
offer more space for early stack/heap use.
Signed-off-by: Chia-Wei Wang
---
arch/arm/include/asm/arch-aspeed/platform.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/
From: Joel Stanley
Hash and Crypto Engine (HACE) is designed to accelerate the
throughput of hash data digest, and symmetric-key encryption.
Signed-off-by: Joel Stanley
Signed-off-by: Chia-Wei Wang
---
drivers/crypto/Kconfig | 2 +
drivers/crypto/Makefile | 1 +
d
From: Joel Stanley
Add YCLK enable for HACE, the HW hash engine of
ASPEED AST2600 SoCs.
Signed-off-by: Joel Stanley
Signed-off-by: Chia-Wei Wang
---
.../arm/include/asm/arch-aspeed/scu_ast2600.h | 5 +++--
drivers/clk/aspeed/clk_ast2600.c | 20 +++
2 files change
From: Joel Stanley
Probe HACE driver in SPL board init if enabled.
Signed-off-by: Joel Stanley
Signed-off-by: Chia-Wei Wang
---
arch/arm/mach-aspeed/ast2600/spl.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/arch/arm/mach-aspeed/ast2600/spl.c
b/arch/arm/mach-aspeed/ast
This patch series intends to provide a secure boot chain from SPL to Linux
kernel
based on the hash and signature verification of FIT image paradigm.
To improve the performance and save code size (SPL is limited to 64KB due to
HW-RoT),
the drviers of two HW crypto engine HACE and ARCY are also a
On Thu, Jul 15, 2021 at 04:51:35PM +0200, Heinrich Schuchardt wrote:
> On 7/8/21 10:22 AM, Michael Chang wrote:
> > The u-boot efi console service registers a timer to poll the keyboard
> > input in every 50ns. In the efi block io service, this timer is
>
> The event is triggered every 5000 ns not
Hi Tim,
On Thu, 15 Jul 2021 at 16:58, Tim Harvey wrote:
>
> Greetings,
>
> I'm taking a look at moving imx8mm-venice to use binman for packaging.
> After doing so U-Boot proper fails to boot:
>
> U-Boot SPL 2021.07-00475-g1126252f40 (Jul 15 2021 - 11:09:02 -0700)
> GSC : v58 0xf098 RST:VIN Th
In DM Ethernet, the old "egiga0" name is no longer valid, so replace it
with Ethernet PHY name from device tree. Also, Ethernet PHY address
is available so read it from device tree.
Reviewed-by: Stefan Roese
Signed-off-by: Tony Dinh
---
Changes in v3:
- Get eth0 PHY address from device tree
Ch
Previously, the GPT device GUID was being used instead of the partition,
which was incorrect.
Signed-off-by: Alfonso Sánchez-Beato
Reviewed-by: Heinrich Schuchardt
---
lib/efi_loader/efi_device_path.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/lib/efi_loader/efi_
> - fuller implementation with more features
Is that a good thing? Didn't we just have a long discussion eschewing
a heavy-handed, bulky hand-off block design in favor of more simple
and flexible structures? I think simplicity is key for this and the
bl_aux_params are trying to be about as simple
On Thu, 15 Jul 2021 13:19:00 +0300
Ivan Uvarov wrote:
Hi Ivan,
thanks for sending this upstream!
> The FETA40i-C is a SoM by Forlinx based on the Allwinner R40/A40i.
>
> SoM specifications:
>
> - SoC: R40 or A40i
> - PMIC: AXP221S
> - RAM: 1GiB/2GiB DDR3 (dual-rank)
> - eMMC: 8GB,
> - Mates w
Greetings,
I'm taking a look at moving imx8mm-venice to use binman for packaging.
After doing so U-Boot proper fails to boot:
U-Boot SPL 2021.07-00475-g1126252f40 (Jul 15 2021 - 11:09:02 -0700)
GSC : v58 0xf098 RST:VIN Thermal Protection Disabled
Model : GW7300-00-B1B
Serial : 852420
MFGDa
On Thu, 15 Jul 2021 13:18:59 +0300
Ivan Uvarov wrote:
Hi Ivan,
> The Forlinx OKA40i-C devboard makes use of UARTs 0,2,3,4,5 and 7 of the R40
> SoC, of which UART 0 is connected to an RS232 converter, UART 5 routed to
> an RS485 converter, and the rest broken out directly via labeled headers.
> T
On Thu, Jul 15, 2021 at 10:24:09AM +0200, gianluca wrote:
> Hello list!
> I know this mail will be OT, but I am worried about what will happen to a
> new project using the PowerPC T2080,e6500 64-bit PPC on this web site:
>
> https://www.powerpc-notebook.org
>
> I suspect the same architecture wi
On Thu, Jul 15, 2021 at 08:13:55PM +0200, Marek Behún wrote:
> Hello Tom and others,
>
> many boards still use the obsolete mtdparts command.
> What is the plan with this command? Do we still want to support it?
>
> Recently as discovered by Masami, my patch
> mtd: spi-nor: allow registering
On Thu, 15 Jul 2021 at 22:04, Ilias Apalodimas
wrote:
>
> On Mon, Jul 05, 2021 at 09:48:49AM -0600, Simon Glass wrote:
> > It is fairly easy to handle this case and it makes the emulator more
> > useful, since PCRs are commonly extended several times.
> >
> > Add support for this, using U-Boot's s
Add the "/reserved-memory/optee" node to the SPL devicetree. The
purpose is to allow configuring TZC regions when booting OP-TEE.
Signed-off-by: Alexandru Gagniuc
Reviewed-by: Simon Glass
---
arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/ar
The purpose of this change is to allow configuring TrustZone (TZC)
memory permissions. For example, OP-TEE expects TZC regions to be
configured in a very particular way. The API presented here is
intended to allow exactly that.
UCLASS support is not implemented, because it would not be too useful.
OP-TEE is very particular about how the TZC should be configured.
When booting an OP-TEE payload, an incorrect TZC configuration will
result in a panic.
Most information can be derived from the SPL devicetree. The only
information we don't have is the split between TZDRAM and shared
memory. This h
OP-TEE requires some particular setup, which is not needed for linux
or other payloads. Add a hook for platform-specific code to perform
any OP-TEE related configuration and initialization.
A weak function is used because it is symmetrical to other
spl_board_prepare_for_*() implementations. A solu
In general, Falcon mode means we're booting a linux kernel directly.
With FIT images, however, an OP-TEE secure kernel can be booted before
linux. Thus, if the next stage is an IH_OS_TEE, this isn't necessarily
a problem.
Of course, a general solution would involve mmc_load_image_raw_os()
only loa
v4 branch was reported to have some issues with SPL becoming too big
on some platforms (e.g. imx6dl_mamoj) This is fixed by dropping the
call to genimg_get_os_name().
Alexandru Gagniuc (5):
spl: mmc: Support OP-TEE payloads in Falcon mode
spl: Introduce spl_board_prepare_for_optee() hook
arm
On 7/15/21 1:27 PM, Patrick DELAUNAY wrote:
Hi,
[snip]
When I merge this patch on master branch, I get the error:
arm: + imx6dl_mamoj
+spl/u-boot-spl.bin exceeds file size limit:
+ limit: 0xefa0 bytes
+ actual: 0xf41d bytes
+ excess: 0x47d bytes
+make[1]: *** [Makefile:1997: spl/u-
On Mon, Jul 05, 2021 at 09:48:49AM -0600, Simon Glass wrote:
> It is fairly easy to handle this case and it makes the emulator more
> useful, since PCRs are commonly extended several times.
>
> Add support for this, using U-Boot's sha256 support.
>
> Signed-off-by: Simon Glass
> ---
>
> driver
Enable DM_PCI and DM_ETH on MIPS Malta.
Signed-off-by: Daniel Schwierzeck
---
(no changes since v1)
arch/mips/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/mips/Kconfig b/arch/mips/Kconfig
index e54801673b..6b1f10d9a0 100644
--- a/arch/mips/Kconfig
+++ b/arch/mips/Kconf
As almost all peripherals are connected via PCI dependent on the
used core card, PCI setup is always required. Thus run pci_init()
including PCI scanning and probing and core card specific setups
in board_early_init_r().
Also prepare support for dynamically managing the status of the
different PCI
Add DT binding for GT64120 and MSC01 PCI controllers. Only
GT64120 is enabled by default to support Qemu. The MSC01 node
will be dynamically enabled by Malta board code dependent
on the plugged core card.
Signed-off-by: Daniel Schwierzeck
---
(no changes since v1)
arch/mips/dts/mti,malta.dts |
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
Reviewed-by: Simon Glass
---
Changes in v2:
- add empty line before return statements
drivers/pci/pci_msc01.c | 72 -
1 file changed, 71 insertions(+), 1 deleti
This driver is currently only used on MIPS Malta boards.
Signed-off-by: Daniel Schwierzeck
Reviewed-by: Simon Glass
---
Changes in v2:
- add empty line before return statements
drivers/pci/pci_gt64120.c | 74 ++-
1 file changed, 73 insertions(+), 1 deleti
On MIPS the DRAM start address respectively CONFIG_SYS_SDRAM_BASE
is still used as a virtual, CPU-mapped address instead of being used
as physical address. Converting all MIPS boards and generic MIPS code
to fix that is not trivial. Due to the approaching deadline for
PCI DM conversion, this workar
This series converts the PCI host controller drivers used by MIPS
Malta and the board-specific PCI setup code to PCI driver model.
Because the AMD PCNET driver is already converted to ETH driver
model, simply enable CONFIG_DM_ETH as well.
A patch in PCI uclass core is currently required for MIPS
On Thu, Jul 15, 2021 at 09:54:08PM +0800, Bin Meng wrote:
> Hi Tom,
>
> This PR includes the following changes for v2021.10:
>
> - x86: various improvements made in getting Chromium OS verified boot
> running on top of coreboot, booting into U-Boot.
>
> Azure results: PASS
> https://dev.azure
On Thu, Jul 15, 2021 at 12:36:58PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the next batch of Marvell MVEBU related patches. Here the
> summary log:
>
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
Hi,
On 5/31/21 7:43 PM, Alexandru Gagniuc wrote:
In general, Falcon mode means we're booting a linux kernel directly.
With FIT images, however, an OP-TEE secure kernel can be booted before
linux. Thus, if the next stage is an IH_OS_TEE, this isn't necessarily
a problem.
Of course, a general sol
Hi Marek,
On Thu, 15 Jul 2021 at 12:13, Marek Behún wrote:
>
> Hello Tom and others,
>
> many boards still use the obsolete mtdparts command.
> What is the plan with this command? Do we still want to support it?
>
> Recently as discovered by Masami, my patch
> mtd: spi-nor: allow registering m
The current stable release of LLVM is 12, update to that. While at it,
fix that we had not correctly upgraded to LLVM 11 previously.
Signed-off-by: Tom Rini
---
.azure-pipelines.yml| 4 ++--
.gitlab-ci.yml | 4 ++--
tools/docker/Dockerfile | 6 +++---
3 files changed, 7 insertions(
Hello Tom and others,
many boards still use the obsolete mtdparts command.
What is the plan with this command? Do we still want to support it?
Recently as discovered by Masami, my patch
mtd: spi-nor: allow registering multiple MTDs when DM is enabled
caused that mtds may have different name th
Hi Sebastian,
On Thu, 15 Jul 2021 at 09:40, Sebastian Reichel
wrote:
>
> Introduce driver for I2C based MCP230xx GPIO chips, which are
> quite common and already well supported by the Linux kernel.
>
> Reviewed-by: Simon Glass
> Signed-off-by: Sebastian Reichel
> ---
> drivers/gpio/Kconfig
On Thu, 15 Jul 2021 at 09:40, Sebastian Reichel
wrote:
>
> Add function to apply a bitmask to an i2c register, so
> that specific bits can be cleared and/or set.
>
> Suggested-by: Simon Glass
> Signed-off-by: Sebastian Reichel
> ---
> drivers/i2c/i2c-uclass.c | 15 +++
> include/i2c
On Mon, Jul 05, 2021 at 09:48:45AM -0600, Simon Glass wrote:
> Tidy up the missing comments for this struct.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/tpm/tpm2_tis_sandbox.c | 20
> 1 file changed, 16 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/tpm/tpm2_t
Hi Simon,
On Mon, Jul 05, 2021 at 09:48:44AM -0600, Simon Glass wrote:
> This function current handles the kernel case incorrectly. Fix it, and
> use the shorter TPM_HDR_LEN while we are here.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/tpm/tpm_tis_sandbox.c | 14 --
> 1 file
Fixup SPI NOR partition nodes in Linux' device tree prior booting Linux.
Linux' devicetree does not contain "u-boot-env" partition and we do not
want to add it there because the address is different between stock
U-Boot and current upstream U-Boot.
Instead we add code that recreates partition nod
Specify a separate partition `u-boot-env` for U-Boot's env settings for
the Turris Omnia board.
Do this only in U-Boot's specific DTS. We do not want to do this in
Linux' official DTS, because Omnia's stock U-Boot stores env at a
different address, and there are still boards with stock U-Boot.
In
Hello Patrick,
On 15.07.21 17:22, Patrick Delaunay wrote:
> With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE
> is not activated), the DT nodes needed by OP-TEE are added by OP-TEE
> firmware in U-Boot device tree, present in FIP.
What about the SCMI nodes. Who will fix up those?
> The
Since we removed embeddingg the capsule key into a .dtb and fixed
authenticated capsule updates for all boards, move the relevant
documentation in the efi file and update it accordingly
Signed-off-by: Ilias Apalodimas
---
doc/board/emulation/qemu_capsule_update.rst | 203
do
commit 322c813f4bec ("mkeficapsule: Add support for embedding public key in a
dtb")
added a bunch of options enabling the addition of the capsule public key
in a dtb. Since now we embeded the key in U-Boot's .rodata we don't this
this functionality anymore
Signed-off-by: Ilias Apalodimas
---
t
The capsule signature is now part of our DTB. This is problematic when a
user is allowed to change/fixup that DTB from U-Boots command line since he
can overwrite the signature as well.
So Instead of adding the key on the DTB, embed it in the u-boot binary it
self as part of it's .rodata. This as
On 14/07/2021 23:52, Gowtham Tammana wrote:
Add pmic lp876411 node needed for CPU AVS support.
Signed-off-by: Gowtham Tammana
---
.../arm/dts/k3-j7200-r5-common-proc-board.dts | 26 +++
1 file changed, 26 insertions(+)
diff --git a/arch/arm/dts/k3-j7200-r5-common-proc-boa
Hi Heinrich,
On Thu, 15 Jul 2021 at 09:35, Heinrich Schuchardt wrote:
>
>
>
> On 15.07.21 17:18, Simon Glass wrote:
> > Hi Heinrich,
> >
> > On Thu, 15 Jul 2021 at 08:38, Heinrich Schuchardt
> > wrote:
> >>
> >> On 7/15/21 2:57 PM, Simon Glass wrote:
> >>> Hi Ilias,
> >>>
> >>> On Thu, 15 Jul 2
Hi,
Add driver for mcp230xx devices, which are quite common.
Changes since PATCHv1:
* add new patch adding dm_i2c_reg_clrset() as suggested
by Simon Glass
* Use | instead of + to build device register
(resulting number is the same)
* Properly handle GPIOD_IS_OUT_ACTIVE flag
* Use bool f
Introduce driver for I2C based MCP230xx GPIO chips, which are
quite common and already well supported by the Linux kernel.
Reviewed-by: Simon Glass
Signed-off-by: Sebastian Reichel
---
drivers/gpio/Kconfig | 10 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/mcp230xx_gpio.c | 23
Add function to apply a bitmask to an i2c register, so
that specific bits can be cleared and/or set.
Suggested-by: Simon Glass
Signed-off-by: Sebastian Reichel
---
drivers/i2c/i2c-uclass.c | 15 +++
include/i2c.h| 14 ++
test/dm/i2c.c| 29
On 15.07.21 17:18, Simon Glass wrote:
Hi Heinrich,
On Thu, 15 Jul 2021 at 08:38, Heinrich Schuchardt wrote:
On 7/15/21 2:57 PM, Simon Glass wrote:
Hi Ilias,
On Thu, 15 Jul 2021 at 00:20, Ilias Apalodimas
wrote:
On Wed, Jul 14, 2021 at 08:52:07AM -0600, Simon Glass wrote:
Hi Ilias,
O
Add TF-A FIP support for trusted boot on STM32MP15x,
when STM32MP15x_STM32IMAGE is not activated.
With FIP support the SSBL partition is named "fip" and its size is 4MB,
so the ENV partition name in device tree (for SD card or eMMC)
or offset in defconfig (CONFIG_ENV_OFFSET / CONFIG_ENV_OFFSET_RE
TF-A for STM32MP15 now supports the FIP: it is a packaging format which
includes the secure monitor, u-boot-nodtb.bin and u-boot.dtb
This FIP file is loaded by FSBL = TF-A BL2.
This patch updates the board documentation to use this FIP file and no
more u-boot.stm32 (with STM32 image header) which
The MTD tee partitions used to save the OP-TEE binary are needed when
TF-A doesn't use the FIP container to load binaries.
This patch puts under CONFIG_STM32MP15x_STM32IMAGE flag the associated
code in U-Boot binary and prepare the code cleanup when
CONFIG_STM32MP15x_STM32IMAGE support will be rem
By default for trusted boot with TF-A, U-Boot (u-boot-nodtb)
is located in FIP container with its device tree and with
the secure monitor (provided by TF-A or OP-TEE).
The FIP file is loaded by TF-A BL2 and each components is
extracted at the final location.
This patch add CONFIG_STM32MP15x_STM32I
With FIP support in TF-A (when CONFIG_STM32MP15x_STM32IMAGE
is not activated), the DT nodes needed by OP-TEE are added by OP-TEE
firmware in U-Boot device tree, present in FIP.
These nodes are only required in trusted boot, when TF-A load the file
u-boot.stm32, including the U-Boot device tree wit
In next TF-A version the stm32mp1 platform will support the Firmware
Image Package (FIP) [1], a container filled with:
- the U-Boot binary = u-boot-nodtb.bin
- the U-Boot device tree = u-boot.dtb
- the Secure OS (OP-TEE) or the secure monitor (SP_MIN)
Upstream is in progress on TF-A side ([3] bu
Hi Heinrich,
On Thu, 15 Jul 2021 at 08:38, Heinrich Schuchardt wrote:
>
> On 7/15/21 2:57 PM, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Thu, 15 Jul 2021 at 00:20, Ilias Apalodimas
> > wrote:
> >>
> >> On Wed, Jul 14, 2021 at 08:52:07AM -0600, Simon Glass wrote:
> >>> Hi Ilias,
> >>>
> >>> On M
Hi Bin,
On Thu, 15 Jul 2021 at 05:44, Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Jun 28, 2021 at 7:51 AM Simon Glass wrote:
> >
> > At present this driver relies on coreboot to provide information about
> > the console UART. However if coreboot is not compiled with the UART
> > enabled, the infor
Hi Patrick,
On Thu, 15 Jul 2021 at 07:50, Patrick DELAUNAY
wrote:
>
> Hi Simon
>
> On 7/11/21 2:01 AM, Simon Glass wrote:
> > Hi Patrick,
> >
> > On Thu, 8 Jul 2021 at 03:17, Patrick Delaunay
> > wrote:
> >>
> >> In next TF-A version the stm32mp1 platform will support the Firmware
> >> Image Pac
Hi François,
On Thu, 15 Jul 2021 at 08:25, François Ozog
wrote:
>
>
> On Sat, 10 Jul 2021 at 01:07, Julius Werner wrote:
>
>> > - "bloblist" is a general term for concept of linked list and it's not
>> exactly U-boot implementation. The proposed solution will cause some degree
>> of changes in
On 7/8/21 10:22 AM, Michael Chang wrote:
The u-boot efi console service registers a timer to poll the keyboard
input in every 50ns. In the efi block io service, this timer is
The event is triggered every 5000 ns not 50 ns. See
lib/efi_loader/efi_console.c:1309. The SetTimer() parameter is in
mu
On 7/15/21 2:57 PM, Simon Glass wrote:
Hi Ilias,
On Thu, 15 Jul 2021 at 00:20, Ilias Apalodimas
wrote:
On Wed, Jul 14, 2021 at 08:52:07AM -0600, Simon Glass wrote:
Hi Ilias,
On Mon, 12 Jul 2021 at 03:28, Ilias Apalodimas
wrote:
On Mon, 12 Jul 2021 at 11:40, Masahisa Kojima
wrote:
Hi S
On Sat, 10 Jul 2021 at 01:07, Julius Werner wrote:
> > - "bloblist" is a general term for concept of linked list and it's not
> exactly U-boot implementation. The proposed solution will cause some degree
> of changes in all the participating projects. For backward compatibility
> issue, we have a
Hi Tom,
This PR includes the following changes for v2021.10:
- x86: various improvements made in getting Chromium OS verified boot
running on top of coreboot, booting into U-Boot.
Azure results: PASS
https://dev.azure.com/bmeng/GitHub/_build/results?buildId=383&view=results
The following chan
Hi Simon
On 7/11/21 2:01 AM, Simon Glass wrote:
Hi Patrick,
On Thu, 8 Jul 2021 at 03:17, Patrick Delaunay
wrote:
In next TF-A version the stm32mp1 platform will support the Firmware
Image Package (FIP) [1], a container filled with:
- the U-Boot binary = u-boot-nodtb.bin
- the U-Boot device t
Hi Pali and Stefan,
> -Original Message-
> From: Stefan Roese
> Sent: Thursday, July 15, 2021 11:00
> To: Pali Rohár ; Tom Rini
> Cc: u-boot@lists.denx.de; Marek Behún ; Kostya
> Porotchkin
> Subject: [EXT] Re: [RFC 1/7] ARM: mvebu: a38x: Correct mismatched bound
> warnings
>
> Externa
Hi Ilias,
On Thu, 15 Jul 2021 at 00:20, Ilias Apalodimas
wrote:
>
> On Wed, Jul 14, 2021 at 08:52:07AM -0600, Simon Glass wrote:
> > Hi Ilias,
> >
> > On Mon, 12 Jul 2021 at 03:28, Ilias Apalodimas
> > wrote:
> > >
> > > On Mon, 12 Jul 2021 at 11:40, Masahisa Kojima
> > > wrote:
> > > >
> > > >
On Thu, Jul 15, 2021 at 7:54 PM Bin Meng wrote:
>
> On Sun, Jul 11, 2021 at 11:15 AM Simon Glass wrote:
> >
> > This is a revert of a recent logic change in setup_zimage(). We do
> > actually need to install this information always. Change it to install
> > from the Coreboot tables if available,
On Sun, Jul 11, 2021 at 11:15 AM Simon Glass wrote:
>
> This is a revert of a recent logic change in setup_zimage(). We do
> actually need to install this information always. Change it to install
> from the Coreboot tables if available, else the normal source.
>
> Fixes: e7bae8283fe ("x86: Allow i
On Fri, 18 Jun 2021 15:31:08 +0200, Pali Rohár wrote:
> Unfortunately for testing is required qflasher which works only in 32-bit
> x86 mode. Apparently 64-bit x86 Azure CI has no problems as it has
> preinstalled 32-bit libraries and can execute also 32-bit x86 executables.
>
> This change just s
On Fri, 18 Jun 2021 15:27:03 +0200, Pali Rohár wrote:
> Enable U-Boot bootz command and update env scripts to try loading also
> zImage file and to try booting via bootz command.
>
> Update also lowlevel_init.S code for checking validity of zImage magic to
> correctly relocate kernel in zImage for
On Wed, 14 Jul 2021 15:52:55 -0500, Gowtham Tammana wrote:
> The J7200 EVM has PMIC LP876441 for supporting CPU AVS. This patchset
> adds dt nodes, compatible string, and configs to enable the
> corresponding driver.
>
> v3:
> - rebased to resolve minor conflicts against master
>
> [...]
Appli
On Wed, 23 Jun 2021 16:14:49 -0500, Gowtham Tammana wrote:
> The J7200 EVM has PMIC LP876441 for supporting CPU AVS. This patchset
> adds dt nodes, compatible string, and configs to enable the
> corresponding driver.
>
> v2:
> - rebased the changes are reordered patches 3/4
>
> [...]
Applied t
Hi Simon,
On Wed, Jul 14, 2021 at 11:47 PM Simon Glass wrote:
>
> Hi Bin,
>
> On Sun, 27 Jun 2021 at 17:51, Simon Glass wrote:
> >
> > Various issues were discovered in getting Chromium OS verified boot
> > running on top of coreboot, booting into U-Boot.
> >
> > Improvements include:
> > - enab
Hi Simon,
On Mon, Jun 28, 2021 at 7:51 AM Simon Glass wrote:
>
> At present this driver relies on coreboot to provide information about
> the console UART. However if coreboot is not compiled with the UART
> enabled, the information is left out. This configuration is quite
> common, e.g. with shi
There is no separate SPL/TPL config for WATCHDOG_AUTOSTART.
So use IS_ENABLED instead of CONFIG_IS_ENABLED to make watchdog
working in SPL again.
Fixes: 830d29ac3721 ("watchdog: Allow to use CONFIG_WDT without starting
watchdog")
Signed-off-by: Teresa Remmet
Reviewed-by: Stefan Roese
---
Change
Hi Tom,
please pull the next batch of Marvell MVEBU related patches. Here the
summary log:
- Turris_omnia/mox: SPI NOR and MTD related changes / fixes (Marek)
- a37xx: pci: Misc fixes / optimizations (Pali)
- Espressobin: Fix setti
On 08.07.21 20:18, Pali Rohár wrote:
Remapped address of PCIe outbound window may have set only bits from the
mask. Add additional check that remapped address which is calculated from
PCIe bus address specified in DTS file is valid.
Remove also useless clearing of low 16 bits in win_mask. As win
On 09.07.21 16:56, Marek Behún wrote:
Commit e2e95e5e2542 ("spi: Update speed/mode on change") changed the
boot time on Turris Omnia from ~2.3s to over 8s, due to SPL loading main
U-Boot from SPI NOR at 1 MHz instead of 40 MHz.
This is because the SPL code passes the CONFIG_SF_DEFAULT_SPEED opti
On 14.07.21 16:37, Pali Rohár wrote:
Ensure that 'env default -a' always set correct value to $fdtfile, even
when custom user variable is already stored in non-volatile env storage
(means that env_get("fdtfile") call returns non-NULL value).
As default value is now correctly set like if specifie
Hi Paul,
On 2021/7/15 8:50, Ying-Chun Liu wrote:
From: "Ying-Chun Liu (PaulLiu)"
Add initial support for Advantech RSB-3720 board.
The initial support includes:
- MMC
- eMMC
- I2C
- FEC
- Serial console
Signed-off-by: Darren Huang
Signed-off-by: Kevin12.Chen
Signed-off-by: Phill.L
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