EMMC_CFG register has a cfg_ddr bit(BIT[2]).
It needs to set when mmc is running to ddr mode.
Otherwise, its bit should be cleared.
CFG_DDR[2] - 1: DDR mode, 0: SDR mode
Signed-off-by: Jaehoon Chung
---
arch/arm/include/asm/arch-meson/sd_emmc.h | 1 +
drivers/mmc/meson_gx_mmc.c|
A following patch introduces EFI_TCG2_PROTOCOL.
Add the required TPMv2 headers to support it.
Signed-off-by: Ilias Apalodimas
---
changes since v2:
- Added description and pointers to TCG specs
- updated copyright info
include/tpm-v2.h | 77
1 fil
Since U-boot EFI implementation is getting richer it makes sense to
add support for EFI_TCG2_PROTOCOL taking advantage of any hardware TPM
available on the device.
This is the initial implementation of the protocol which only adds
support for GetCapability(). It's limited in the newer and safer
TP
Hi Ran,
On Tue, Nov 10, 2020 at 3:36 PM Ran Wang wrote:
>
> Hi Bin,
>
> On Tuesday, November 10, 2020 1:43 PM Bin Meng wrote:
> >
> > Hi Ran,
> >
> > On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
> > >
> > > Hi Ran,
> > >
> > > On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> > > >
> > > > I
Hi Pragnesh
> Hi Rick,
>
> >-Original Message-
> >From: Rick Chen
> >Sent: 09 November 2020 13:44
> >To: Pragnesh Patel
> >Cc: U-Boot Mailing List ; Atish Patra
> >; Bin Meng ; Paul Walmsley (
> >Sifive) ; Anup Patel ; Sagar
> >Kadam ; Simon Glass ; Sean
> >Anderson ; palmerdabb...@googl
On 2020/11/8 下午10:00, Hugh Cole-Baker wrote:
Commit c4cea2bbf995 ("rockchip: Enable building a SPI ROM image on bob")
added an alias spi1 referring to spi@ff1d, however there was already
an alias spi0 referring to the same node in rockpro64's u-boot.dtsi, and
having both aliases present bro
Hi Bin,
On Tuesday, November 10, 2020 1:43 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
> >
> > Hi Ran,
> >
> > On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> > >
> > > In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it
> > > will
> >
> >
Hi Peter,
On 2020/11/9 上午7:02, Peter Robinson wrote:
Move the bits that are device specific to the -u-boot.dtsi as the
bits may be different on other devices and hence breaks SPI on
those devices such as the Pinebook Pro.
Signed-off-by: Peter Robinson
Fixes: c4cea2bbf995 ("rockchip: Enable bui
Booting Agilex and Diamond Mesa with Vendor Authorized Boot.
Signed-off-by: Siew Chin Lim
---
configs/{socfpga_agilex_atf_defconfig => socfpga_agilex_vab_defconfig} | 3 ++-
configs/{socfpga_dm_atf_defconfig => socfpga_dm_vab_defconfig} | 3 ++-
2 files changed, 4 insertions(+), 2 deleti
Remove 'run linux_qspi_enable' from bootcommand. When using FIT for
OS boot, 'run linux_qspi_enable' will be called 'board_prep_linux'
function.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_soc64_common.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/include/c
FIT image of Vendor Authentication Coot (VAB) contains signed images.
Signed-off-by: Siew Chin Lim
---
arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi | 22 ++
1 file changed, 22 insertions(+)
diff --git a/arch/arm/dts/socfpga_soc64_fit-u-boot.dtsi
b/arch/arm/dts/socfpga_soc64_f
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
loaded from FIT, the VAB certificate and signature block appended
at the end of each image are sent to Secu
Support 'vab' command to perform vendor authentication.
Command format: vab addr len
Authorize 'len' bytes starting at 'addr' via vendor public key
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/vab.c| 37 +
This patchset add Vendor Authorized Boot (VAB) support for
Intel Agilex and Diamond Mesa SoC devices.
Vendor Authorized Boot is a security feature for authenticating
the images such as U-Boot, ARM trusted Firmware, Linux kernel,
device tree blob and etc loaded from FIT. After those images are
load
Add device tree for Diamond Mesa.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/socfpga_dm-u-boot.dtsi | 102 +
arch/arm/dts/socfpga_dm.dtsi | 640 ++
arch/arm/dts
Add defconfig for Diamond Mesa to support both
legacy boot flow and ATF boot flow.
Legacy boot:
SPL -> U-Boot proper -> OS (Linux)
ATF boot flow:
SPL -> ATF(BL31) -> U-Boot proper -> OS (Linux)
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Kconfig| 19 ++
arch/arm/mach-soc
Rename to common file name to used by all SOC64 devices.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile| 4 ++--
.../mach-socfpga/{wrap_pll_config_s10.c => wrap_pll_config_soc64.c} | 2 +-
2 files changed, 3 insertions(+), 3 deletions(-)
Add CONFIGs for Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
include/configs/socfpga_dm_socdk.h | 46 ++
1 file changed, 46 insertions(+)
create mode 100644 include/configs/socfpga_dm_socdk.h
diff --git a/include/configs/socfpga_dm_socdk.h
b/include/confi
The DDR subsystem in Diamond Mesa is consisted of controller, PHY,
memory reset manager and memory clock manager.
Configuration settings of controller, PHY and memory reset manager
is come from DDR handoff data in bitstream, which contain the register
base addresses and user settings from Quartus
Move Stratix10 and Agilex SPL common code to spl_soc64.c
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 2 ++
arch/arm/mach-socfpga/spl_agilex.c | 16
arch/arm/mach-socfpga/spl_s10.c| 17 -
arch/arm/mach-socfpga/spl_soc64.c | 26 +
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/spl_dm.c | 93 ++
1 file changed, 93 insertions(+)
create mode 100644 arch/arm/mach-socfpga/spl_dm.c
diff --git a/arch/arm/mach-socfpga/spl_dm.c b/arch/arm/mach-socfpga/spl_dm.c
new file mode 100644
i
Add Diamond Mesa SoC devkit board.
Signed-off-by: Siew Chin Lim
---
board/intel/dm-socdk/MAINTAINERS | 7 +++
board/intel/dm-socdk/Makefile| 7 +++
board/intel/dm-socdk/socfpga.c | 7 +++
3 files changed, 21 insertions(+)
create mode 100644 board/intel/dm-socdk/MAINTAINERS
cr
Add clock manager for Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_dm.c | 79 ++
arch/arm/mach-socfpga/include/mach/clock_manager.h | 2 +
.../mach-socfpga/include/mach/clock_manager_dm.h | 14
3 files changed, 95 insert
Move duplicated function cm_get_qspi_controller_clk_hz to clock_manager.c.
Signed-off-by: Siew Chin Lim
Signed-off-by: Tien Fong Chee
---
arch/arm/mach-socfpga/clock_manager.c | 10 ++
arch/arm/mach-socfpga/clock_manager_agilex.c | 6 --
arch/arm/mach-soc
Diamond Mesa support both HPS handoff data and DDR handoff data.
HPS handoff data support re-use Straix10 and Agilex code. DDR
handoff data is newly introduced in Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 19 ++
arch/arm/mach-socf
Changed to store QSPI reference clock in kHz instead of Hz in
boot scratch cold0 register for Stratix10 and Agilex.
This patch is in preparation for Diamond Mesa SDRAM driver
support. Reserved 4 bits for Diamond Mesa SDRAM driver,
and there will be 28 bits to store QSPI reference clock.
Due to lim
Add memory clock manager driver for Diamond Mesa. Provides
clock initialization and enable functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 2 +-
drivers/clk/altera/clk-mem-dm.c | 135
drivers/clk/altera/clk-mem-dm.h | 80 +
Add clock manager driver for Diamond Mesa. Provides clock
initialization and get_rate functions.
Signed-off-by: Siew Chin Lim
---
drivers/clk/altera/Makefile | 3 +-
drivers/clk/altera/clk-dm.c | 504 +++
drivers/clk/altera/clk-dm.h |
Restructure Stratix10 and Agilex handoff code to used by
all SOC64 devices, in preparation to support handoff for
Diamond Mesa.
Remove wrap_pinmux_config_s10.c. Add wrap_handoff_soc64.c
which contains the generic function to parse the handoff
data.
Update system_manager_soc64.c to use generic han
No functionality change. In preparation for Stratix10 and
Agilex handoff function restructuring.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/handoff_soc64.h | 46 +++---
1 file changed, 24 insertions(+), 22 deletions(-)
diff --git a/arch/arm/mach-socfpga/
Disable the MPFE firewall for SMMU and HMC adapter for
Agilex and Diamond Mesa.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/firewall.c | 10 ++
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 1 +
arch/arm/mach-socfpga/include/mach/firewall.h | 6
Add Diamond Mesa clock manager to socfpga_get_managers_addr
function.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/misc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-socfpga/misc.c b/arch/arm/mach-socfpga/misc.c
index ac2b891fad..b63eec779a 100644
--- a/arch/ar
Rename handoff_s10.h to handoff_soc64.h. Changed macros prefix from
S10_HANDOFF to SOC64_HANDOFF.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/clock_manager_s10.c | 2 +-
arch/arm/mach-socfpga/include/mach/handoff_s10.h | 39 --
arch/arm/mach-socfpga/inc
Reuse base_addr_s10.h for Diamond Mesa, the address is the
same as Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/include/mach/base_addr_s10.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-socfpga/include/mach/base_addr_s10.h
b/arch/arm/mach-s
Create common macro TARGET_SOCFPGA_SOC64 for Stratix10 and Agilex.
Signed-off-by: Siew Chin Lim
---
arch/arm/Kconfig| 6 +++---
arch/arm/mach-socfpga/Kconfig | 5 +
arch/arm/mach-socfpga/include/mach/reset_manager.h | 3 +--
arch/arm
Rename to common file name to used by all SOC64 devices.
No functionality change.
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/Makefile | 5 +++--
.../mach-socfpga/{system_manager_s10.c => system_manager_soc64.c}| 0
2 files changed, 3 insertio
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in Diamond Mesa are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch statu
Hi Peng,
Any comments on the patches.
Thanks.
Best regards,
Yangbo Lu
> -Original Message-
> From: Yangbo Lu
> Sent: Tuesday, October 20, 2020 11:05 AM
> To: u-boot@lists.denx.de; Peng Fan ; 'Jaehoon Chung'
>
> Cc: Y.b. Lu
> Subject: [v2, 0/2] mmc: fsl_esdhc: fix up for eMMC HS400
>
Hi All,
Kindly ignore "[v2,00/22] Add Intel Diamond Mesa SoC support" series of
patches.
Sorry that I make some mistake when send for review. I will resend this series.
I sincerely apologize for the inconvenience caused
Thanks,
Siew Chin
> -Original Message-
> From: Lim, Elly Siew Ch
Hi Siew,
On Tue, Nov 10, 2020 at 1:56 PM Siew Chin Lim
wrote:
>
> This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
>
> Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
> hard processor system (HPS). New IPs in Diamond Mesa are clock manager
> and D
Add binman node to device tree to generate the FIT image for u-boot
(u-boot.itb) and OS kernel (kernel.itb).
u-boot.itb contains arm trusted firmware (ATF), u-boot proper and
u-boot device tree for ATF u-boot flow.
kernel.itb contains Linux Image and Linux device tree.
Signed-off-by: Siew Chin L
From: Chee Hong Ang
Booting Agilex and Stratix 10 with ATF support.
SPL now loads ATF (BL31), U-Boot proper and DTB from FIT
image. The new boot flow with ATF support is as follow:
SPL -> ATF (BL31) -> U-Boot proper -> OS (Linux)
U-Boot proper now starts at 0x20 (CONFIG_SYS_TEXT_BASE).
ATF
Add new build target "fit-itb" for FIT image generation.
In preparation to support Vendor Authorized Boot (VAB) for Intel
SOC64 device in near future. With VAB, u-boot proper, dtb and
arm trusted firmware need to be signed before FIT image generation.
To align user experience for ATF boot with an
From: Chee Hong Ang
mbox_reset_cold() will invoke ATF's PSCI service when running in
non-secure mode (EL2).
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/mailbox_s10.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/mach-socfpga/mailbox_s10.c
b/arch/arm/mach-socfpga
From: Chee Hong Ang
SPL already setup the Clock Manager with the handoff data
from OCRAM. When the Clock Manager's driver get probed again
in SSBL, it shall skip the handoff data access in OCRAM.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/wrap_pll_config_s10.c | 3 ++-
1 file chang
From: Chee Hong Ang
Since SSBL is running in DRAM, it shall setup the stack in DRAM
instead of OCRAM which is occupied by SPL and handoff data.
Signed-off-by: Chee Hong Ang
---
include/configs/socfpga_soc64_common.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/configs/socfp
From: Chee Hong Ang
In non-secure mode (EL2), FPGA reconfiguration driver calls the
SMC/PSCI services provided by ATF to configure the FPGA.
Signed-off-by: Chee Hong Ang
---
drivers/fpga/intel_sdm_mb.c | 139
1 file changed, 139 insertions(+)
diff
From: Chee Hong Ang
In non-secure mode (EL2), MMC driver calls the SMC/PSCI services
provided by ATF to set SDMMC's DRVSEL and SMPLSEL.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/mmc/socfpga_dw_mmc.c | 17 +
1 file changed, 17 insertions(+)
diff --g
From: Chee Hong Ang
In non-secure mode (EL2), Reset Manager driver calls the
SMC/PSCI service provided by ATF to enable/disable the
SOCFPGA bridges.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
arch/arm/mach-socfpga/reset_manager_s10.c | 13 +
1 file changed, 13 i
From: Chee Hong Ang
This header file defines the Secure Monitor Call (SMC) message
protocol for ATF (BL31) PSCI runtime services. It includes all
the PSCI SiP function identifiers for the secure runtime services
provided by ATF. The secure runtime services include System Manager's
registers acces
From: Chee Hong Ang
In non-secure mode (EL2), MAC driver calls the SMC/PSCI services
provided by ATF to setup the PHY interface.
Signed-off-by: Chee Hong Ang
Signed-off-by: Siew Chin Lim
---
drivers/net/dwmac_socfpga.c | 30 ++
1 file changed, 26 insertions(+), 4 d
From: Chee Hong Ang
invoke_smc() allow U-Boot proper running in non-secure mode (EL2)
to invoke SMC call to ATF's PSCI runtime services such as
System Manager's registers access, 2nd phase bitstream FPGA
reconfiguration, Remote System Update (RSU) and etc.
smc_send_mailbox() is a send mailbox co
From: Chee Hong Ang
Override 'lowlevel_init' to make sure secondary CPUs trapped
in ATF instead of SPL. After ATF is initialized, it will signal
the secondary CPUs to jump from SPL to ATF waiting to be 'activated'
by Linux OS via PSCI call.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpg
From: Chee Hong Ang
Instead of loading u-boot proper image (u-boot.img), SPL
now loads FIT image (u-boot.itb) which includes u-boot
proper, ATF and u-boot proper's DTB.
For OS, u-boot now loads FIT images (kernel.itb) which
includes Linux Image and Linux's DTB.
Signed-off-by: Chee Hong Ang
Sig
From: Chee Hong Ang
Standard PSCI function "CPU_ON" provided by ATF is now used
by Linux kernel to bring up the secondary CPUs to enable SMP
booting in Linux on SoC 64bits platform.
Signed-off-by: Chee Hong Ang
---
arch/arm/mach-socfpga/Kconfig | 2 --
1 file changed, 2 deletions(-)
diff --gi
From: Chee Hong Ang
Add board_fit_config_name_match() for matching board name with
device tree files in FIT image. This will ensure correct DTB
file is loaded for different board type. Currently, we are not
supporting multiple device tree files in FIT image therefore this
function basically do no
From: Simon Glass
Now that we can use devicetree to specify this information, drop the old
CONFIG options.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
configs/clearfog_gt_8k_defconfig| 2 --
configs/mt7622_rfb_defconfig| 1 -
configs/mvebu_db_armada8k_defconfig | 2 --
From: Simon Glass
Add a file containing defaults for these, using the existing CONFIG
options. This file must be included with #include since it needs to
be passed through the C preprocessor.
Enable the driver for all x86 boards that generate SMBIOS tables.
Disable it for coral since it has its
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/x86/dts/galileo.dts| 28
board/intel/galileo/Kconfig | 11 ---
2 files changed,
This is the 2nd version of patchset add Intel Diamond Mesa SoC[1] support.
Intel Diamond Mesa SoC is with a 64-bit quad core ARM Cortex-A53 MPCore
hard processor system (HPS). New IPs in Diamond Mesa are clock manager
and DDR subsystem, other IPs have minor changes compared to Agilex.
Patch statu
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/arm/dts/armada-3720-uDPU-u-boot.dtsi | 20
configs/uDPU_defconfig| 3 ++-
2 fil
From: Pali Rohár
Calling 'make V=1 all' on Ubuntu 18.04 with gcc version 9.2.1 and GNU Make
version 4.1 fails on error:
scripts/Kbuild.include:220: *** Recursive variable 'echo-cmd' references
itself (eventually). Stop.
As a workaround expand 'echo-cmd' variable via 'call' construction in
From: Simon Glass
Add settings and enable the default sysinfo driver so that these can come
from the device tree.
Signed-off-by: Simon Glass
Reviewed-by: Bin Meng
---
arch/arm/dts/meson-gxbb-odroidc2-u-boot.dtsi | 23 +++
configs/odroid-c2_defconfig | 4 +
Hi Ran,
On Tue, Nov 10, 2020 at 1:30 PM Bin Meng wrote:
>
> Hi Ran,
>
> On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
> >
> > In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it will
>
> typo: function
>
> > send request in more than 1 Transfer TRB by chaining them, but then handl
Hi Ran,
On Tue, Sep 22, 2020 at 1:02 PM Ran Wang wrote:
>
> In functiion xhci_bulk_tx(), when buffer cross 64KB boundary, it will
typo: function
> send request in more than 1 Transfer TRB by chaining them, but then handle
> only 1 event TRB to mark request completed.
>
> However, on Layerscape
Rockchip has many 32bit SoCs and some of them are support SPL_OPTEE now,
only boards with SPL_OPTEE support can fit BINMAN well, other boards
will fail at initr_binman() in U-Boot proper after below patch,
eg. rv1108 board.
83187546ae binman: Support multiple images in the library
Fixes: 79030
Hi Tom,
This PR includes the following x86 changes for v2021.01 release:
- Avoid using hardcoded number of variable range MTRRs in mtrr_commit()
- coral: Correct max98357 file
- coral: Update smbios tables to latest definition
Azure results: PASS
https://dev.azure.com/bmeng/GitHub/_build/results
On Tue, Nov 10, 2020 at 9:43 AM Bin Meng wrote:
>
> On Mon, Nov 9, 2020 at 10:12 PM Simon Glass wrote:
> >
> > The accepted binding uses multiple nodes, one for each table type. Update
> > coral accordingly.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > arch/x86/dts/chromebook_coral.dts |
On Mon, Nov 9, 2020 at 10:12 PM Simon Glass wrote:
>
> The accepted binding uses multiple nodes, one for each table type. Update
> coral accordingly.
>
> Signed-off-by: Simon Glass
> ---
>
> arch/x86/dts/chromebook_coral.dts | 27 +--
> 1 file changed, 21 insertions(+), 6
On Tue, Nov 10, 2020 at 9:34 AM Bin Meng wrote:
>
> Hi Simon,
>
> On Mon, Nov 9, 2020 at 9:41 PM Simon Glass wrote:
> >
> > This somehow ended up as an empty file. Fix it.
> >
> > Signed-off-by: Simon Glass
> > ---
> >
> > .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes
>
Hi Simon,
On Mon, Nov 9, 2020 at 9:41 PM Simon Glass wrote:
>
> This somehow ended up as an empty file. Fix it.
>
> Signed-off-by: Simon Glass
> ---
>
> .../max98357-render-2ch-48khz-24b.dat | Bin 0 -> 116 bytes
> 1 file changed, 0 insertions(+), 0 deletions(-)
>
Acked-by: Bin Men
On Tue, Nov 10, 2020 at 12:05 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
> >
> > Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> > the maximum number of variable range MTRRs was increased from 8 to 10,
> > which caused a #GP exceptio
Hi Simon,
On Tue, Nov 10, 2020 at 12:05 AM Simon Glass wrote:
>
> Hi Bin,
>
> On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
> >
> > Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> > the maximum number of variable range MTRRs was increased from 8 to 10,
> > which caused a #
On 09/11/2020 22:37, Simon Glass wrote:
> Hi Heinrich,
>
> On Mon, 9 Nov 2020 at 12:34, Heinrich Schuchardt wrote:
>>
>> On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
>>> The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
>>> keyboard, but this host command was superseded by EC_C
On 03/11/2020 03:32, Samuel Holland wrote:
> The PinePhone is a smartphone produced by Pine64, with an A64 SoC,
> 2 or 3 GiB LPDDR3 RAM, 16 or 32 GiB eMMC, 720x1440 MIPI-DSI panel,
> and Quectel EG25-G modem.
>
> There are two main board revisions: 1.1 for early adopters, and 1.2
> for mass produc
Dear Anand,
On 11/10/20 4:02 AM, Anand Moon wrote:
> Hi Neil,
>
> On Mon, 9 Nov 2020 at 19:56, Neil Armstrong wrote:
>>
>> On 09/11/2020 15:10, Mark Kettenis wrote:
From: Neil Armstrong
Date: Mon, 9 Nov 2020 14:37:09 +0100
Hi,
On 09/11/2020 04:12, Jaehoon Chung wro
On 11/9/20 10:38 PM, Neil Armstrong wrote:
> On 09/11/2020 09:37, Jaehoon Chung wrote:
>> On 11/6/20 7:01 PM, Neil Armstrong wrote:
>>> On 06/11/2020 10:59, Jaehoon Chung wrote:
Hi,
On 11/6/20 6:28 PM, Neil Armstrong wrote:
> Hi,
>
> On 06/11/2020 03:10, Jaehoon Chung wro
Hey all,
It's regular release day and I'm back on schedule, so here's -rc2.
There's a few small'ish things outstanding in my queue, and a queue of
things building up for -next already. I'm going to try and make sure
what I pull in, even when a clean-up, is as close as can be to the
obviously cor
On Thu, Oct 08, 2020 at 03:14:17PM +0200, Marek Vasut wrote:
> In case there is an EEPROM attached to the KS8851 MAC and the EEPROM
> contains a valid MAC address, the MAC address is loaded into the NIC
> registers on power on. Read the MAC address out of the NIC registers
> and provide it to U-Bo
On Mon, Nov 09, 2020 at 07:31:08PM +0530, Amit Singh Tomar wrote:
> after commit 4ab3817ff16a ("clk: fixed-rate: Enable DM_FLAG_PRE_RELOC flag")
> Cubieboard7 (based on actions S700 SoC) fails to boot.
>
> It is due to the fact that the default value of CONFIG_SYS_MALLOC_F_LEN
> (0x400)
> would
On Mon, Nov 09, 2020 at 07:54:38PM +0100, Heinrich Schuchardt wrote:
> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>
> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> 11:27:14 -0500)
>
> are available in the Git repository at:
>
> http
On 11/9/20 11:23 PM, Neil Armstrong wrote:
> On 09/11/2020 15:10, Mark Kettenis wrote:
>>> From: Neil Armstrong
>>> Date: Mon, 9 Nov 2020 14:37:09 +0100
>>>
>>> Hi,
>>>
>>> On 09/11/2020 04:12, Jaehoon Chung wrote:
Core clock phase value is changed from 180' to 270'.
It's more stable tha
-Original Message-
From: Simon Glass
Sent: Saturday, November 7, 2020 1:33 PM
To: Duffin, CooperX
Cc: U-Boot Mailing List ; uboot-snps-...@synopsys.com;
Tom Rini ; Robert Beckett ;
Heiko Schocher ; Wolgang Denk ; Ian Ray
Subject: Re: [dwi2c PATCH v1] dwi2c add offsets to reads
Hi Co
Hi,
On 11/9/20 11:10 PM, Mark Kettenis wrote:
>> From: Neil Armstrong
>> Date: Mon, 9 Nov 2020 14:37:09 +0100
>>
>> Hi,
>>
>> On 09/11/2020 04:12, Jaehoon Chung wrote:
>>> Core clock phase value is changed from 180' to 270'.
>>> It's more stable than before.
>>> - Odroidn-N2/C4 : Working fine wit
On 11/9/20 10:37 PM, Neil Armstrong wrote:
> Hi,
>
> On 09/11/2020 04:12, Jaehoon Chung wrote:
>> Core clock phase value is changed from 180' to 270'.
>> It's more stable than before.
>> - Odroidn-N2/C4 : Working fine with 52MHz
>> - VIM3 : Working fine with 52MHz
>>
>> Before this patch, Odroid-C
On 11/9/20 10:13 PM, Alper Nebi Yasak wrote:
> On 09/11/2020 23:34, Heinrich Schuchardt wrote:
>> With commit 690079767803 ("cros_ec: Support keyboard scanning with
>> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
>> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
On 09/11/2020 23:34, Heinrich Schuchardt wrote:
> With commit 690079767803 ("cros_ec: Support keyboard scanning with
> EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
> strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
> not understand this command. We need to reply w
With commit 690079767803 ("cros_ec: Support keyboard scanning with
EC_CMD_GET_NEXT_EVENT") check_for_keys() tries to read keyboard
strokes using EC_CMD_GET_NEXT_EVENT. But the sandbox driver does
not understand this command. We need to reply with
-EC_RES_INVALID_COMMAND to force check_for_keys() to
Hi Heinrich,
[...]
>
> > > + */
> > > +#define TPM2_NUM_PCR_BANKS 16
> > > +
> > > +/* Definition of (UINT32) TPM2_CAP Constants */
> > > +#define TPM2_CAP_PCRS 0x0005U
> > > +#define TPM2_CAP_TPM_PROPERTIES 0x0006U
> > > +
> > > +/* Definition of (UINT32) TPM2_PT Constants */
> > > +#de
On 11/9/20 8:18 PM, Tom Rini wrote:
> On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote:
>
>> On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
>>> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>>>
>>> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-
Hi Heinrich,
On Mon, 9 Nov 2020 at 12:34, Heinrich Schuchardt wrote:
>
> On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> > The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> > keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> > and unavailable on more re
Align the pin setup for sdhci0 with linux kernel.
This means to have slew rate enable and high drive strength.
Signed-off-by: Eugen Hristev
---
arch/arm/dts/sam9x60.dtsi | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/sam9x60.dtsi b/arch/arm/d
On 10/30/20 6:25 PM, Alper Nebi Yasak wrote:
> The cros_ec_keyb driver currently uses EC_CMD_MKBP_STATE to scan the
> keyboard, but this host command was superseded by EC_CMD_GET_NEXT_EVENT
> and unavailable on more recent devices (including gru-kevin), as it was
> removed in cros-ec commit 87a0719
On Mon, Nov 09, 2020 at 08:15:43PM +0100, Heinrich Schuchardt wrote:
> On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
> > The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
> >
> > Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> > 11:27:14 -0500)
On 11/9/20 7:54 PM, Heinrich Schuchardt wrote:
> The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
>
> Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
> 11:27:14 -0500)
>
> are available in the Git repository at:
>
> https://gitlab.denx.de/u-boot/
Hi Neil,
On Mon, 9 Nov 2020 at 19:56, Neil Armstrong wrote:
>
> On 09/11/2020 15:10, Mark Kettenis wrote:
> >> From: Neil Armstrong
> >> Date: Mon, 9 Nov 2020 14:37:09 +0100
> >>
> >> Hi,
> >>
> >> On 09/11/2020 04:12, Jaehoon Chung wrote:
> >>> Core clock phase value is changed from 180' to 270
The following changes since commit 22ad69b7987eb4b10221330661db4427e40174fb:
Merge tag 'dm-pull5nov20' of git://git.denx.de/u-boot-dm (2020-11-06
11:27:14 -0500)
are available in the Git repository at:
https://gitlab.denx.de/u-boot/custodians/u-boot-efi.git
tags/efi-2021-01-rc2-2
for you to
> From: Heinrich Schuchardt
> Date: Mon, 9 Nov 2020 15:36:33 +0100
>
> On 09.11.20 14:51, Mark Kettenis wrote:
> >> From: Paulo Alcantara
> >> Date: Mon, 09 Nov 2020 10:24:08 -0300
> >>
> >> Heinrich Schuchardt writes:
> >>
> >>> On 09.11.20 00:58, Paulo Alcantara wrote:
> The UEFI specifi
Hi Bin,
On Mon, 9 Nov 2020 at 01:05, Bin Meng wrote:
>
> Since commit 29d2d64ed55f ("x86: Add support for more than 8 MTRRs"),
> the maximum number of variable range MTRRs was increased from 8 to 10,
> which caused a #GP exception during VESA video driver probe.
>
> On the BayTrail platform there
If the clock driver does not offer a clk_enable ops, then the system will
return -ENOSYS.
The clk_enable works with CCF (common clock framework).
Some clocks in some cases (like the generic clock for some products: sama5d2)
do not have the clk_enable primitive, and in this case probing of the drive
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