On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel
wrote:
>
> Release ethernet clock reset
Please add a detailed commit message of why the ethernet clock is
resetting in SPL code since ethernet won't need for SPL at all?
Jagan.
On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote:
>
> When the flash is handed to us in a stateful mode like 8D-8D-8D, it is
> difficult to detect the mode the flash is in. One option is to read SFDP
> in all modes and see which one gives the correct "SFDP" signature, but
> not all flashes sup
On Mon, Mar 30, 2020 at 9:16 PM Pratyush Yadav wrote:
>
> On probe, the SPI NOR core will put a flash in 8D-8D-8D mode if it
> supports it. But Linux as of now expects to get the flash in 1S-1S-1S
> mode. Handing the flash to Linux in Octal DTR mode means the kernel will
> fail to detect the flash
OpenSBI generic platform support provides platform specific
functionality based on the FDT passed by previous booting stage.
Depends on OpenSBI commit:
platform: Add generic FDT based platform support
(sha1: f1aa9e54e6ae70aeac638d5b75093520f65d)
Signed-off-by: Pragnesh Patel
---
doc/board/s
From: Jagan Teki
Add U-Boot proper sector start offset for SiFive FU540.
This value is based on the partition layout supported
by SiFive FU540.
u-boot.itb need to write on this specific offset so-that
the SPL will retrieve it from here and load.
Signed-off-by: Jagan Teki
Reviewed-by: Bin Meng
With sifive_fu540_defconfig:
User can use FSBL or u-boot-spl.bin anyone at a time.
For FSBL,
fsbl->fw_payload.bin (opensbi + U-Boot)
For u-boot-spl.bin,
u-boot-spl.bin->FIT image (opensbi + U-Boot proper + dtb)
U-Boot SPL will be loaded by ZSBL from SD card (replace fsbl.bin with
u-boot-spl.bin
This sync has changes required to use GPIO in U-Boot and
U-Boot SPL.
Sync dts from linux v5.7-rc2 commit:
"riscv: dts: Add GPIO reboot method to HiFive Unleashed DTS file"
(sha1: 0a91330b2af9f71cd483f92774182b58f6d9)
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
---
arch/riscv/dts/fu
Add SiFive fu540 cpu to support RISC-V arch
Signed-off-by: Pragnesh Patel
---
arch/riscv/Kconfig | 1 +
arch/riscv/cpu/fu540/Kconfig | 15 ++
arch/riscv/cpu/fu540/Makefile| 7 +
arch/riscv/cpu/fu540/cpu.c | 22
From: Jagan Teki
This is a sample GPT partition layout for SD card,
right now three important partitions are added to
make the system bootable.
partition layout:
PartStart LBA End LBA Name
Attributes
Type GUID
Partition GUID
1 0x0022 0x00
Add a support for SPL which will boot from L2 LIM (0x0800_) and
then SPL will boot U-Boot FIT image (OpenSBI FW_DYNAMIC + u-boot.bin)
from MMC boot devices.
SPL related code is leveraged from FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
Revi
Add dmc node to enable ddr driver. dmc is used to
initialize the memory controller.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 9 +
1 file changed, 9 insertions(+)
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dt
Release ethernet clock reset
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 20
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index f26a370a64..45491a77d5 100644
--- a/drivers/clk/sifive/
Add DDR controller and phy register settings, taken from fsbl
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
.../dts/fu540-hifive-unleashed-a00-ddr.dtsi | 1489 +
1 file changed, 1489 insertions(+)
create mode 100644 arch/riscv/d
Release ddr clock reset
Signed-off-by: Pragnesh Patel
---
drivers/clk/sifive/fu540-prci.c | 51 +
1 file changed, 45 insertions(+), 6 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c
index bf06c3a3bb..f26a370a64 100644
-
Added clock enable and disable functions in prci ops
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/clk/sifive/fu540-prci.c | 108
1 file changed, 96 insertions(+), 12 deletions(-)
diff --git a/drivers/clk/sifive/fu540-prci
Devicetree files in FU540 platform is synced from Linux, like other
platforms does. Apart from these U-Boot in FU540 would also require
some U-Boot specific node like clint.
So, create board specific -u-boot.dtsi files. This would help of
maintain U-Boot specific changes separately without touchin
Add driver for fu540 to support ddr initialization in SPL.
This driver is based on FSBL
(https://github.com/sifive/freedom-u540-c000-bootloader.git)
Signed-off-by: Pragnesh Patel
---
board/sifive/fu540/Kconfig | 2 +
drivers/ram/Kconfig| 1 +
drivers/ram/Makefile |
When build U-Boot SPL, meet an issue of undefined reference to
'crc7' for drivers/mmc/mmc_spi.c, so let's compile crc7.c when
CONFIG_MMC_SPI selected.
Signed-off-by: Pragnesh Patel
---
lib/Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/lib/Makefile b/lib/Makefile
in
For SPL_SEPARATE_BSS, Device tree will be put at _image_binary_end
Signed-off-by: Pragnesh Patel
Reviewed-by: Anup Patel
Reviewed-by: Jagan Teki
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/cpu/u-boot-spl.lds | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/riscv/cpu/u-bo
Use the OTP DM driver to set the serial environment variable.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
arch/riscv/dts/fu540-c000-u-boot.dtsi | 14 +++
.../dts/hifive-unleashed-a00-u-boot.dtsi | 2 +
board/sifive/fu540/Kconfig
Added a misc driver to handle OTP memory in SiFive SoCs.
Signed-off-by: Pragnesh Patel
Reviewed-by: Bin Meng
Tested-by: Bin Meng
---
drivers/misc/Kconfig | 7 +
drivers/misc/Makefile | 1 +
drivers/misc/sifive-otp.c | 273 ++
3 files changed, 28
This series add support for SPL to FU540. U-Boot SPL can boot from
L2 LIM (0x0800_) and jump to OpenSBI(FW_DYNAMIC firmware) and
U-Boot proper from MMC devices.
This series depends on:
[1] https://patchwork.ozlabs.org/patch/1281853
[2] https://patchwork.ozlabs.org/patch/1281852
All these toge
On 5/11/20 8:14 PM, Ilias Apalodimas wrote:
> In OP-TEE we can run EDK2's StandAloneMM on a secure partition.
> StandAloneMM is responsible for the UEFI variable support. In
> combination with OP-TEE and it's U-Boot supplicant, variables are
> authenticated/validated in secure world and stored on a
Hello Heinrich,
Am 13.05.2020 um 07:53 schrieb Heinrich Schuchardt:
On 5/13/20 5:54 AM, Heiko Schocher wrote:
Hello Tom,
Am 12.05.2020 um 15:28 schrieb Heiko Schocher:
Hello Tom,
Am 12.05.2020 um 00:28 schrieb Tom Rini:
Hey all,
It's release day and I've tagged v2020.07-rc2. At this point
On 5/13/20 5:54 AM, Heiko Schocher wrote:
> Hello Tom,
>
> Am 12.05.2020 um 15:28 schrieb Heiko Schocher:
>> Hello Tom,
>>
>> Am 12.05.2020 um 00:28 schrieb Tom Rini:
>>> Hey all,
>>>
>>> It's release day and I've tagged v2020.07-rc2. At this point out we
>>> should be seeing stabilization, clean-
Our email addresses have changed from @c-s.fr to @csgroup.eu
Update entry in MAINTAINERS
Signed-off-by: Christophe Leroy
---
MAINTAINERS | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index ec59ce8b8802..d67112479700 100644
--- a/MAINTAINERS
+++ b/
Hello Tom,
Am 12.05.2020 um 15:28 schrieb Heiko Schocher:
Hello Tom,
Am 12.05.2020 um 00:28 schrieb Tom Rini:
Hey all,
It's release day and I've tagged v2020.07-rc2. At this point out we
should be seeing stabilization, clean-up and localized new features.
Once again, for a changelog,
git lo
On Mon, May 11, 2020 at 09:08:03PM +0200, Heinrich Schuchardt wrote:
> On 5/11/20 8:40 PM, Tom Rini wrote:
> > On Sun, May 10, 2020 at 10:12:07PM +0900, Masahiro Yamada wrote:
> >> On Sun, May 10, 2020 at 12:12 AM Heinrich Schuchardt
> >> wrote:
> >>>
> >>> GCC recognizes /* fallthrough */ if -Wi
Hi Rayagonda,
On Tue, 12 May 2020 at 02:00, Rayagonda Kokatanur
wrote:
>
> From: Srinath Mannam
>
> Add support for IPROC PAXC PCIe RC driver.
>
> Signed-off-by: Srinath Mannam
> Signed-off-by: Rayagonda Kokatanur
> ---
> drivers/pci/Kconfig |7 +
> drivers/pci/Makefile |1 +
Hi Simon,
On Wed, May 13, 2020 at 7:56 AM Simon Glass wrote:
>
> Hi Rayagonda,
>
> On Tue, 12 May 2020 at 02:00, Rayagonda Kokatanur
> wrote:
> >
> > From: Srinath Mannam
> >
> > Add support for IPROC PAXC PCIe RC driver.
> >
> > Signed-off-by: Srinath Mannam
> > Signed-off-by: Rayagonda Kokat
Hi Rayagonda,
On Tue, 12 May 2020 at 02:00, Rayagonda Kokatanur
wrote:
>
> From: Srinath Mannam
>
> Add support for IPROC PAXC PCIe RC driver.
>
> Signed-off-by: Srinath Mannam
> Signed-off-by: Rayagonda Kokatanur
> ---
> drivers/pci/Kconfig |7 +
> drivers/pci/Makefile |1 +
Hi Rayagonda,
On Tue, 12 May 2020 at 02:00, Rayagonda Kokatanur
wrote:
>
> Add api to get dma regions.
>
> Signed-off-by: Rayagonda Kokatanur
> ---
> drivers/pci/pci-uclass.c | 42
> include/pci.h| 3 ++-
> 2 files changed, 44 insertions(+),
It goes without saying, that the satellite broadband often costs more than
fixed line broadband deals and set up costs are between £100 to £400. Prices
for satellite broadband tend to vary between £20 per month to £100 per
month. Satellite broadband deals also often have restrictive download limits
Hi Marek,
On 2020/5/12 15:26, Marek Vasut wrote:
On 5/12/20 3:08 AM, Frank Wang wrote:
Hi Marek,
On 2020/5/11 17:48, Marek Vasut wrote:
On 5/11/20 9:57 AM, Frank Wang wrote:
[...]
@@ -394,6 +407,12 @@ static int dwc3_glue_probe(struct udevice *dev)
if (ret)
return ret;
Hi Simon,
Thanks for your response.
On 5/7/20 6:36 PM, Simon Glass wrote:
> Hi Rudolf,
>
> On Wed, 18 Mar 2020 at 05:25, Rudolf J Streif
> wrote:
>> I ran into an issue today with a U-CLASS SPI NOR flash device on a NXP
>> FlexSPI controller. U-Boot started correctly from the flash device but
>
Hi Andy,
On Tue, 12 May 2020 at 06:32, Andy Shevchenko
wrote:
>
> On Tue, May 12, 2020 at 01:55:49PM +0200, Wolfgang Wallner wrote:
>
> > > Since you were involved a lot in the discussion in the part A series,
> > > would you please let me know if you get some time to review this?
> >
> > Unfortu
Hi Peng,
On Sun, May 3, 2020 at 9:37 AM Peng Fan wrote:
>
> From: Ye Li
>
> Add flexspi relevant clocks, and fix set parent clock, so we can
These are two different changes, which should be addressed by two
separate patches.
Thanks
On Sun, May 3, 2020 at 7:37 AM Peng Fan wrote:
>
> From: Ye Li
>
> Add flexspi relevant clocks, and fix set parent clock, so we can
> assign clocks through DTB
In one place it's called flexspi, but in two other places it's called
QSPI. I recognize that the FlexSPI is controlling a quad-spi no
On Tue, May 12, 2020 at 08:39:16PM +0200, Marek Vasut wrote:
> The following changes since commit 2a38d2239d0bb4d128b00886bf097ab247a0b1a7:
>
> Prepare v2020.07-rc2 (2020-05-11 18:28:19 -0400)
>
> are available in the Git repository at:
>
> git://git.denx.de/u-boot-usb.git master
>
> for y
H6 SOC needs additional initialization of PHY registers. Corresponding
changes can be found in the kernel patch [1].
Without this changes there is no enumeration of 'musb' gadget.
[1] -
https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/commit/?id=ae409cc7c3cdb9ac4a1dba3eae70efec
On Tue, May 12, 2020 at 12:42 PM Sylwester Nawrocki
wrote:
>
> Hi Jim,
>
> On 08.05.2020 16:25, Jim Quinlan wrote:
> static int brcm_pcie_probe(struct udevice *dev)
> +{
> + struct udevice *ctlr = pci_get_controller(dev);
> + struct pci_controller *hose = dev_get_uc
On Tue, May 12, 2020 at 1:51 PM Matthias Brugger wrote:
>
>
>
> On 12/05/2020 13:39, Matthias Brugger wrote:
> >
> >
> > On 12/05/2020 13:36, Belisko Marek wrote:
> >> On Tue, May 12, 2020 at 1:16 PM Matthias Brugger
> >> wrote:
> >>>
> >>>
> >>>
> >>> On 12/05/2020 13:00, Belisko Marek wrote:
>
On Tue, May 12, 2020 at 05:39:46PM +0100, André Przywara wrote:
> On 12/05/2020 16:09, Tom Rini wrote:
>
> Hi,
>
> > On Tue, May 12, 2020 at 03:53:55PM +0100, André Przywara wrote:
> >> On 12/05/2020 15:25, Tom Rini wrote:
> >>> On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
> >>
On Tue, May 12, 2020 at 11:26:52AM +0200, Neil Armstrong wrote:
> Hi Tom,
>
> This PR enables adds GPIO Open-Drain/Open-Source emulation in GPIO uclass
> and finally enables USB Host support for the Odroid-C2 board.
>
> The CI job is at
> https://gitlab.denx.de/u-boot/custodians/u-boot-amlogic/
The following changes since commit 2a38d2239d0bb4d128b00886bf097ab247a0b1a7:
Prepare v2020.07-rc2 (2020-05-11 18:28:19 -0400)
are available in the Git repository at:
git://git.denx.de/u-boot-usb.git master
for you to fetch changes up to 648856ac19ea528ecdc3788a638e080c33256a3c:
usb: dwc3
On 09.05.20 19:59, Denis 'GNUtoo' Carikli wrote:
> On Sun, 1 Mar 2020 14:59:23 +0100
> Soeren Moch wrote:
>
>> To ease the review process it is good style to add a patch revision
>> history below the sign-off after a "---" separator. This would look
>> like ---
>> changes in v4:
>> - bla
> I u
From: Nicolas Saenz Julienne
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne
[s.nawroc
This patch adds basic driver PCI Express controller found on Broadcom
set-top-box SoCs, e.g. BCM2711.
The code is based on Linux upstream driver (pcie-brcmstb.c) with MSI
handling removed. The inbound access memory region is not currently
parsed from dma-ranges DT property and a fixed 3GB region is
This requires enabling BRCMSTB PCIe and XHCI_PCI drivers as well as PCI
and USB commands. To get it working one has to call the following commands:
"pci enum; usb start;", thus such commands have been added to the default
"preboot" environment variable. One has to update their environment if it
is
Add PCI Express capability definitions required by the Broadcom
STB PCIe controller driver.
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Bin Meng
Reviewed-by: Nicolas Saenz Julienne
---
Changes since v2:
- added Current Link Speed defines.
Changes since v1:
- none.
Changes since RFC:
- ens
From: Marek Szyprowski
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge.
Signed-off-by: Marek Szyprowski
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Nicolas Saenz Julienne
---
Ch
Some PCI Express register offsets are currently defined in multiple
drivers, move them to a common header to avoid re-definitions and
as a pre-requisite for adding new PCIe driver.
While at it replace some spaces with tabs.
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Bin Meng
Reviewed-by: Nic
From: Nicolas Saenz Julienne
Imports Al Viro's original Linux commit 00b0c9b82663a, which contains
an in depth explanation and two fixes from Johannes Berg:
e7d4a95da86e0 "bitfield: fix *_encode_bits()",
37a3862e12382 "bitfield: add u8 helpers".
Signed-off-by: Nicolas Saenz Julienne
[s.nawroc
From: Marek Szyprowski
Remove the overlap between DRAM and device's IO area.
Signed-off-by: Marek Szyprowski
Signed-off-by: Sylwester Nawrocki
Reviewed-by: Nicolas Saenz Julienne
---
Changes since v1:
- none.
---
arch/arm/mach-bcm283x/init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletio
In current code there is no cache flush after initializing the scratchpad
buffer array with the scratchpad buffer pointers. This leads to a failure
of the "slot enable" command on the rpi4 board (Broadcom STB PCIe
controller + VL805 USB hub) - the very first TRB transfer on the command
ring fails a
Hi all,
This patch series adds USB host support for Raspberry Pi 4 board.
It includes the Broadcom STB PCIe controller driver ported from Linux
kernel, a memory mapping update for the xHCI controller on PCIe bus
for 64-bit builds and some related fixes and updates in the usb/xhci
and the pci dr
There might be hardware configurations where 64-bit data accesses
to XHCI registers are not supported properly. This patch removes
the readq/writeq so always two 32-bit accesses are used to read/write
64-bit XHCI registers, similarly as it is done in Linux kernel.
This patch fixes operation of th
On 12/05/20 10:13PM, Jagan Teki wrote:
> On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav wrote:
> >
> > Hi,
> >
> > This series adds support for octal DTR flashes in the spi-nor framework,
> > and then adds hooks for the Cypress Semper flash which is an xSPI
> > compliant Octal DTR flash.
> >
> > T
On Mon, May 4, 2020 at 12:27 PM Rayagonda Kokatanur
wrote:
>
> Add brcm iproc qspi support.
>
> Signed-off-by: Rayagonda Kokatanur
> ---
> drivers/spi/Kconfig | 14 +
> drivers/spi/Makefile | 1 +
> drivers/spi/iproc_qspi.c | 852 +++
> drivers/spi
There are two speed grades of the STM32MP1, the A/C and D/F, the
former can run up to 650 MHz, the later at up to 800 MHz. Allow
specifying PLL config for both in the DT, so that it is possible
to cater for boards which can be populated with either SoC.
Signed-off-by: Marek Vasut
Cc: Patrick Dela
Make the bsec driver available both in SPL and in U-Boot proper
to make it possible to read out the SoC type (A/C/D/F) and thus
to determine the MPU PLL configuration (650/800 MHz).
Signed-off-by: Marek Vasut
Cc: Patrick Delaunay
Cc: Patrice Chotard
---
arch/arm/mach-stm32mp/Makefile | 2 +-
1
On Tue, May 12, 2020 at 03:09:54PM +0200, S??bastien Szymanski wrote:
> According to the table 6-25 "Primary image offset and IVT offset
> details", in the IMX8MNRM, the ROM expects the following image offset:
>
> SD: 32KB
> eMMC: 0 if image is in boot partion and 32KB if it is on user partition
>
On 4/29/20 3:08 PM, Marek Vasut wrote:
> Add custom DDR DRAM settings for the DHCOR and DHCOM SoMs and put them
> into use by the board file instead of the default ones. These new DRAM
> settings are a better fit for the SoMs.
>
> Signed-off-by: Marek Vasut
> Cc: Patrick Delaunay
> Cc: Patrice C
On Mon, Mar 30, 2020 at 9:15 PM Pratyush Yadav wrote:
>
> Hi,
>
> This series adds support for octal DTR flashes in the spi-nor framework,
> and then adds hooks for the Cypress Semper flash which is an xSPI
> compliant Octal DTR flash.
>
> The Cadence QSPI controller driver is also updated to run
Hi Jim,
On 08.05.2020 16:25, Jim Quinlan wrote:
static int brcm_pcie_probe(struct udevice *dev)
+{
+ struct udevice *ctlr = pci_get_controller(dev);
+ struct pci_controller *hose = dev_get_uclass_priv(ctlr);
+ struct brcm_pcie *pcie = dev_get_priv(dev);
>
On 12/05/2020 16:09, Tom Rini wrote:
Hi,
> On Tue, May 12, 2020 at 03:53:55PM +0100, André Przywara wrote:
>> On 12/05/2020 15:25, Tom Rini wrote:
>>> On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
On 09/05/2020 15:25, Amit Singh Tomar wrote:
> This patch adds node for e
On Sun, 1 Mar 2020 14:59:23 +0100
Soeren Moch wrote:
> To ease the review process it is good style to add a patch revision
> history below the sign-off after a "---" separator. This would look
> like ---
> changes in v4:
> - bla
I usually use that to indicate changes that do not correspond to th
> So, we're at -rc2 for v2020.07. The DDR calculation stuff I can see
> getting pulled in. Is the ethernet driver for this SoC so far from done
> that it's not ready for linux-next? Things don't have to be in mainline
> proper, but the expectation is that it's making reasonable progress
> there
On Thu, 30 Apr 2020 11:31:27 +0200, Michal Simek wrote:
> List U-Boot project in vendor prefixes.
>
> For more information take a look at:
> https://en.wikipedia.org/wiki/Das_U-Boot
> Source code is available here:
> https://gitlab.denx.de/u-boot/u-boot
>
> Signed-off-by: Michal Simek
> ---
>
>
On 12.05.2020 15:17, Marek Szyprowski wrote:
> -void mmu_set_region_dcache_behaviour(phys_addr_t start, size_t size,
> - enum dcache_option option);
> +static inline void mmu_set_region_dcache_behaviour(phys_addr_t start,
> + size_t size, enum dc
On Tue, May 12, 2020 at 03:53:55PM +0100, André Przywara wrote:
> On 12/05/2020 15:25, Tom Rini wrote:
> > On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
> >> On 09/05/2020 15:25, Amit Singh Tomar wrote:
> >>> This patch adds node for ethernet controller found on Action Semi OWL
>
On 12/05/2020 15:37, Amit Tomer wrote:
> Hi,
>
> On Tue, May 12, 2020 at 7:49 PM André Przywara wrote:
>>
>> On 09/05/2020 15:25, Amit Singh Tomar wrote:
>>> This patch adds node for ethernet controller found on Action Semi OWL
>>> S700 SoC.
>>>
>>> Since, there is no upstream Linux binding exist
On 12/05/2020 15:25, Tom Rini wrote:
> On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
>> On 09/05/2020 15:25, Amit Singh Tomar wrote:
>>> This patch adds node for ethernet controller found on Action Semi OWL
>>> S700 SoC.
>>>
>>> Since, there is no upstream Linux binding exist for
On Tue, May 12, 2020 at 08:12:37PM +0530, Amit Tomer wrote:
> Hi,
>
> > The general way to move forward here is that bindings should be getting
> > proposed to Linux and accepted there, and U-Boot can take a WIP of them,
> > that gets updated later on to match, but we shouldn't get it here first.
Hi,
> The general way to move forward here is that bindings should be getting
> proposed to Linux and accepted there, and U-Boot can take a WIP of them,
> that gets updated later on to match, but we shouldn't get it here first.
I do have a plan to propose this binding to Linux but this is kind of
Hi,
On Tue, May 12, 2020 at 7:49 PM André Przywara wrote:
>
> On 09/05/2020 15:25, Amit Singh Tomar wrote:
> > This patch adds node for ethernet controller found on Action Semi OWL
> > S700 SoC.
> >
> > Since, there is no upstream Linux binding exist for S700 ethernet
> > controller, Changes are
On 28/04/2020 18:57, Simon Glass wrote:
Hi,
sorry for the delay, found this, slightly mouldy already, in my draft
folder.
First, thanks for the review! I saw the Tom merged this already, but
wanted to come back to the DT hacks:
> Hi Andre,
>
> On Mon, 27 Apr 2020 at 12:18, Andre Przywara wrot
On Tue, May 12, 2020 at 03:18:33PM +0100, André Przywara wrote:
> On 09/05/2020 15:25, Amit Singh Tomar wrote:
> > This patch adds node for ethernet controller found on Action Semi OWL
> > S700 SoC.
> >
> > Since, there is no upstream Linux binding exist for S700 ethernet
> > controller, Changes a
On 09/05/2020 15:25, Amit Singh Tomar wrote:
> This patch adds node for ethernet controller found on Action Semi OWL
> S700 SoC.
>
> Since, there is no upstream Linux binding exist for S700 ethernet
> controller, Changes are put in u-boot specific dtsi file.
But that should not be the S700 SoC .d
On 11/05/2020 12:55, Heinrich Schuchardt wrote:
On 11.05.20 10:48, Grant Likely wrote:
On 07/05/2020 19:19, Heinrich Schuchardt wrote:
According to the UEFI spec ACPI tables should be placed in
EfiACPIReclaimMemory. Let's do the same with the device tree.
Suggested-by: Ard Biesheuvel
Cc: G
Hello Tom,
Am 12.05.2020 um 00:28 schrieb Tom Rini:
Hey all,
It's release day and I've tagged v2020.07-rc2. At this point out we
should be seeing stabilization, clean-up and localized new features.
Once again, for a changelog,
git log --merges v2020.07-rc1..v2020.07-rc2
and as always, I ask f
Hi All,
This is a result of the following discussion:
https://lists.denx.de/pipermail/u-boot/2020-May/411086.html
Those 2 patches are replacement for the patch discussed there.
Best regards
Marek Szyprowski
Samsung R&D Institute Poland
Marek Szyprowski (2):
arm: provide a function for boards
Create a non-cacheable mapping for the 0x6 physical memory region,
where MMIO registers for the PCIe XHCI controller are instantiated by the
PCIe bridge. Due to 32bit limit in the CPU virtual address space in ARM
32bit mode, this region is mapped at 0xff80 CPU virtual address.
Signed-o
Provide a function for setting arbitrary virtual-physical MMU mapping
for the given region.
Signed-off-by: Marek Szyprowski
---
arch/arm/include/asm/mmu.h| 8
arch/arm/include/asm/system.h | 18 --
arch/arm/lib/cache-cp15.c | 18 --
3 files chang
Hi Gary,
On Mon, May 11, 2020 at 1:11 PM Gary Bisson
wrote:
>
> Doing the same as the unittests for libavb [1].
>
> Allows to run 'avb verify' multiple times which can be useful after a
> failure to be able to re-flash the partition and try again.
>
> [1]
> https://android.googlesource.com/platfo
According to the table 6-25 "Primary image offset and IVT offset
details", in the IMX8MNRM, the ROM expects the following image offset:
SD: 32KB
eMMC: 0 if image is in boot partion and 32KB if it is on user partition
NAND: 0
FlexSPI: 4KB
SPI: 0
On eMMC, it is more likely that U-Boot is on the boo
dm_gpio_lookup_name() searches for a gpio through
the bank name. But we have also gpio labels, and it
makes sense to search for a gpio also in the labels
we have defined, if no gpio is found through the
bank name definition.
This is useful for example if you have a wp pin on
different gpios on dif
currently gpio hog function is not tested with "ut dm gpio"
so add some basic tests for gpio hog functionality.
For this enable GPIO_HOG in sandbox_defconfig, add
in DTS some gpio hog entries, and add testcase in
"ut dm gpio" command.
Signed-off-by: Heiko Schocher
---
Changes in v4:
- rebased
search for gpio label if gpio name from bankname is not found.
This makes sense on boards with different hardware verions. You
can now search for the gpio label name, and can give the gpio
a unique name. The real gpio pin number is not needed in board
code anymore.
while at it add basic gpio hog
save the GPIOD_ flags also in the gpio descriptor.
Signed-off-by: Heiko Schocher
---
Changes in v4:
- new in version 4
Changes in v3: None
Changes in v2: None
drivers/gpio/gpio-uclass.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/gpio/gpio-uclass.c b/drivers/gpio/gpio-ucl
> Subject: [PATCH 2/2] configs: rpi_arm64: enable SDHCI SDMA support
>
> From: Matthias Brugger
>
> RPi4 supports SDMA on it's SDHCI controller. Enable to option for the combine
> RPi3/4 config.
>
> Signed-off-by: Matthias Brugger
>
> ---
>
> configs/rpi_arm64_defconfig | 1 +
> 1 file chan
> Subject: [PATCH 1/2] mmc: sdhci: Use debug for not supported SDMA info
> message
>
> From: Matthias Brugger
>
> If CONFIG_MMC_SDHCI_SDMA is enabled but the HW could not support it,
> we no longer error out. Instead we do not enable it in the host.
> Change the output from printf to debug as th
On Tue, May 12, 2020 at 01:55:49PM +0200, Wolfgang Wallner wrote:
> > Since you were involved a lot in the discussion in the part A series,
> > would you please let me know if you get some time to review this?
>
> Unfortunately, I don't have as much time now for review of part B as I had for
> pa
On Tue, May 12, 2020 at 11:35:06AM +0530, Lokesh Vutla wrote:
> Hi Tom,
>
> On 12/05/20 1:11 AM, Tom Rini wrote:
> > Given limitations on the current implementation of our test framework,
> > having both am65x_evm_r5 and am65x_evm_a53 have serial output on the
> > same port confuses the tests. If
Hi Simon,
-"Simon Glass" schrieb: -
>Betreff: [PATCH v2] test: Use ut_asserteq_mem() where possible
>
>Quite a few tests still use ut_assertok(memcmp(...)) and variants.
>Modify
>them to use the macro designed for this purpose.
>
>Suggested-by: Wolfgang Wallner
>
>Signed-off-by: Simon Gl
On Tue, May 12, 2020 at 11:24:10AM +0530, Vignesh Raghavendra wrote:
>
>
> On 11/05/20 11:53 pm, Tom Rini wrote:
> > On Mon, May 11, 2020 at 06:12:59PM +0530, Lokesh Vutla wrote:
> >
> >> Hi Tom,
> >>Please find the pull request for v2020.07-rc2 containing TI specific
> >> changes.
> >>
> >
Hi Peng,
On Tue, May 12, 2020 at 8:59 AM Peng Fan wrote:
> I not met this error. Which commit hash are you using?
I am using top of tree U-Boot master:
commit 2a38d2239d0bb4d128b00886bf097ab247a0b1a7
Author: Tom Rini
Date: Mon May 11 18:28:19 2020 -0400
Prepare v2020.07-rc2
Signed
Hi Matthias,
On 08.05.2020 23:26, Matthias Brugger wrote:
> Adding Tom as he is the arm maintainer.
>
> On 04/05/2020 14:45, Sylwester Nawrocki wrote:
>> From: Marek Szyprowski
>>
>> Create a non-cacheable mapping for the 0x6 physical memory region,
>> where MMIO registers for the PCIe XH
On Thu, Apr 30, 2020 at 11:31 AM Michal Simek wrote:
> List U-Boot project in vendor prefixes.
>
> For more information take a look at:
> https://en.wikipedia.org/wiki/Das_U-Boot
> Source code is available here:
> https://gitlab.denx.de/u-boot/u-boot
>
> Signed-off-by: Michal Simek
> ---
>
> The
> Subject: Re: [PATCH V2 1/5] imx8mp_evk: spl: drop useless code
>
> Hi Peng,
>
> On Tue, May 12, 2020 at 6:16 AM Peng Fan wrote:
> >
> > Drop useless getting ccm device, there is no need to explicted do this
> > in board code, and we not enable SPL CLK currently.
> >
> > Signed-off-by: Peng Fan
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