On Mon, May 4, 2020 at 12:27 PM Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com> wrote: > > Add brcm iproc qspi support. > > Signed-off-by: Rayagonda Kokatanur <rayagonda.kokata...@broadcom.com> > --- > drivers/spi/Kconfig | 14 + > drivers/spi/Makefile | 1 + > drivers/spi/iproc_qspi.c | 852 +++++++++++++++++++++++++++++++++++++++ > drivers/spi/iproc_qspi.h | 18 + > drivers/spi/iproc_spi.c | 71 ++++ > 5 files changed, 956 insertions(+) > create mode 100644 drivers/spi/iproc_qspi.c > create mode 100644 drivers/spi/iproc_qspi.h > create mode 100644 drivers/spi/iproc_spi.c > > diff --git a/drivers/spi/Kconfig b/drivers/spi/Kconfig > index 4166c6104e..6333536468 100644 > --- a/drivers/spi/Kconfig > +++ b/drivers/spi/Kconfig > @@ -148,6 +148,20 @@ config ICH_SPI > access the SPI NOR flash on platforms embedding this Intel > ICH IP core. > > +config IPROC_QSPI > + bool "QSPI driver for BCM iProc QSPI Controller" > + select IPROC_SPI > + help > + This selects the BCM iProc QSPI controller. > + This driver support spi flash single, quad and memory reads. > + > +config BCM_IPROC_USE_BSPI > + bool "Broadcom BSPI driver for fast read" > + depends on IPROC_QSPI > + help > + This selects the BCM BSPI driver for fast read mode. > + Enable this mode if flash(nand/nor) supports. > + > config MESON_SPIFC > bool "Amlogic Meson SPI Flash Controller driver" > depends on ARCH_MESON > diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile > index 52462e19a3..359f6a87cb 100644 > --- a/drivers/spi/Makefile > +++ b/drivers/spi/Makefile > @@ -32,6 +32,7 @@ obj-$(CONFIG_FSL_DSPI) += fsl_dspi.o > obj-$(CONFIG_FSL_ESPI) += fsl_espi.o > obj-$(CONFIG_FSL_QSPI) += fsl_qspi.o > obj-$(CONFIG_ICH_SPI) += ich.o > +obj-$(CONFIG_IPROC_QSPI) += iproc_qspi.o > obj-$(CONFIG_KIRKWOOD_SPI) += kirkwood_spi.o > obj-$(CONFIG_LPC32XX_SSP) += lpc32xx_ssp.o > obj-$(CONFIG_MESON_SPIFC) += meson_spifc.o > diff --git a/drivers/spi/iproc_qspi.c b/drivers/spi/iproc_qspi.c > new file mode 100644 > index 0000000000..e28b063f82 > --- /dev/null > +++ b/drivers/spi/iproc_qspi.c > @@ -0,0 +1,852 @@ > +// SPDX-License-Identifier: GPL-2.0+ > +/* > + * Copyright 2020 Broadcom > + */ > + > +#include <asm/io.h> > +#include <linux/err.h> > +#include <common.h> > +#include <dm.h> > +#include <errno.h> > +#include <malloc.h> > +#include <spi.h> > +#include "iproc_qspi.h" > + > +#define QSPI_AXI_CLK 175000000 /* 175MHz */ > + > +/* default SCK frequency, unit: HZ */ > +#define QSPI_DEF_SCK_FREQ 50000000 > + > +#define QSPI_WAIT_TIMEOUT_MS 200U /* msec */ > + > +/* Chip attributes */ > +#define SPBR_MIN 8U > +#define SPBR_MAX 255U > +#define NUM_CDRAM 16U > + > +#define CDRAM_PCS0 2 > +#define CDRAM_CONT BIT(7) > +#define CDRAM_BITS_EN BIT(6) > +#define CDRAM_QUAD_MODE BIT(8) > +#define CDRAM_RBIT_INPUT BIT(10) > + > +#define MSPI_SPE BIT(6) > +#define MSPI_CONT_AFTER_CMD BIT(7) > + > +/* > + * Register fields > + */ > +#define MSPI_SPCR0_MSB_BITS_8 0x00000020 > +#define BSPI_RAF_CONTROL_START_MASK 0x00000001 > +#define BSPI_RAF_STATUS_SESSION_BUSY_MASK 0x00000001 > +#define BSPI_RAF_STATUS_FIFO_EMPTY_MASK 0x00000002 > +#define BSPI_BITS_PER_PHASE_ADDR_MARK 0x00010000 > +#define BSPI_BITS_PER_CYCLE_DATA_SHIFT 0 > +#define BSPI_BITS_PER_CYCLE_ADDR_SHIFT 16 > +#define BSPI_STRAP_OVERRIDE_DATA_QUAD_SHIFT 3 > +#define BSPI_STRAP_OVERRIDE_DATA_DUAL_SHIFT 1 > +#define BSPI_STRAP_OVERRIDE_SHIFT 0 > + > +/* > + * Flash opcode and parameters > + */ > +#define OPCODE_RDSR 0x05 > +#define OPCODE_FAST_READ 0x0B > +#define OPCODE_DUAL_READ 0x3b > +#define OPCODE_QUAD_READ 0x6b > +#define OPCODE_EN4B 0xB7 > +#define OPCODE_EX4B 0xE9 > +#define OPCODE_BRWR 0x17
Flash opcode cannot be in the spi bus driver. I have already commented similar stuff in previous version [1] > + > +/* MSPI registers */ > +#define MSPI_SPCR0_LSB_REG 0x000 > +#define MSPI_SPCR0_MSB_REG 0x004 > +#define MSPI_SPCR1_LSB_REG 0x008 > +#define MSPI_SPCR1_MSB_REG 0x00c > +#define MSPI_NEWQP_REG 0x010 > +#define MSPI_ENDQP_REG 0x014 > +#define MSPI_SPCR2_REG 0x018 > +#define MSPI_STATUS_REG 0x020 > +#define MSPI_CPTQP_REG 0x024 > +#define MSPI_TXRAM_REG 0x040 > +#define MSPI_RXRAM_REG 0x0c0 > +#define MSPI_CDRAM_REG 0x140 > +#define MSPI_WRITE_LOCK_REG 0x180 > +#define MSPI_DISABLE_FLUSH_GEN_REG 0x184 > + > +/* BSPI registers */ > +#define BSPI_REVISION_ID_REG 0x000 > +#define BSPI_SCRATCH_REG 0x004 > +#define BSPI_MAST_N_BOOT_CTRL_REG 0x008 > +#define BSPI_BUSY_STATUS_REG 0x00c > +#define BSPI_INTR_STATUS_REG 0x010 > +#define BSPI_B0_STATUS_REG 0x014 > +#define BSPI_B0_CTRL_REG 0x018 > +#define BSPI_B1_STATUS_REG 0x01c > +#define BSPI_B1_CTRL_REG 0x020 > +#define BSPI_STRAP_OVERRIDE_CTRL_REG 0x024 > +#define BSPI_FLEX_MODE_ENABLE_REG 0x028 > +#define BSPI_BITS_PER_CYCLE_REG 0x02C > +#define BSPI_BITS_PER_PHASE_REG 0x030 > +#define BSPI_CMD_AND_MODE_BYTE_REG 0x034 > +#define BSPI_FLASH_UPPER_ADDR_BYTE_REG 0x038 > +#define BSPI_XOR_VALUE_REG 0x03C > +#define BSPI_XOR_ENABLE_REG 0x040 > +#define BSPI_PIO_MODE_ENABLE_REG 0x044 > +#define BSPI_PIO_IODIR_REG 0x048 > +#define BSPI_PIO_DATA_REG 0x04C > + > +/* RAF registers */ > +#define BSPI_RAF_START_ADDRESS_REG 0x00 > +#define BSPI_RAF_NUM_WORDS_REG 0x04 > +#define BSPI_RAF_CTRL_REG 0x08 > +#define BSPI_RAF_FULLNESS_REG 0x0C > +#define BSPI_RAF_WATERMARK_REG 0x10 > +#define BSPI_RAF_STATUS_REG 0x14 > +#define BSPI_RAF_READ_DATA_REG 0x18 > +#define BSPI_RAF_WORD_CNT_REG 0x1C > +#define BSPI_RAF_CURR_ADDR_REG 0x20 > + > +/* > + * Register access macros > + */ > +#define REG_RD(x) readl(x) > +#define REG_WR(x, y) writel((y), (x)) > +#define REG_CLR(x, y) REG_WR((x), REG_RD(x) & ~(y)) > +#define REG_SET(x, y) REG_WR((x), REG_RD(x) | (y)) > + > +/* State */ > +enum bcm_qspi_state { > + QSPI_STATE_DISABLED, > + QSPI_STATE_MSPI, > + QSPI_STATE_BSPI > +}; > + > +/* QSPI platform data */ > +struct bcmspi_platdata { > + /* Registers */ > + s32 frequency; > + void *mspi_hw; > + void *bspi_hw; > + void *bspi_hw_raf; > +}; > + > +/* QSPI private data */ > +struct bcmspi_priv { > + /* Specified SPI parameters */ > + unsigned int max_hz; > + unsigned int spi_mode; > + > + /* State */ > + enum bcm_qspi_state state; > + u8 bspi_op; > + u32 bspi_addr; > + int mspi_16bit; > + int mode_4byte; > + > + /* Registers */ > + void *mspi_hw; > + void *bspi_hw; > + void *bspi_hw_raf; > + void *cru_hw; > +}; > + > +#ifdef CONFIG_BCM_IPROC_USE_BSPI > +static void bspi_flush_prefetch_buffers(struct bcmspi_priv *priv) > +{ > + REG_WR(priv->bspi_hw + BSPI_B0_CTRL_REG, 0); > + REG_WR(priv->bspi_hw + BSPI_B1_CTRL_REG, 0); > + REG_WR(priv->bspi_hw + BSPI_B0_CTRL_REG, 1); > + REG_WR(priv->bspi_hw + BSPI_B1_CTRL_REG, 1); > +} > + > +static int bcmspi_enable_bspi(struct bcmspi_priv *priv) > +{ > + if (priv->state == QSPI_STATE_BSPI) > + return 0; > + > + /* Disable write lock */ > + REG_WR(priv->mspi_hw + MSPI_WRITE_LOCK_REG, 0); > + > + /* Flush prefetch buffers */ > + bspi_flush_prefetch_buffers(priv); > + > + /* Switch to BSPI */ > + REG_WR(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG, 0); > + > + /* Update state */ > + priv->state = QSPI_STATE_BSPI; > + > + return 0; > +} > +#endif /* CONFIG_BCM_IPROC_USE_BSPI */ > + > +static int bcmspi_disable_bspi(struct bcmspi_priv *priv) > +{ > + if (priv->state == QSPI_STATE_MSPI) > + return 0; > + > + /* Switch to MSPI if not yet */ > + if ((REG_RD(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & 1) == 0) { > + unsigned long start = get_timer(0); > + > + while (get_timer(start) < > + QSPI_WAIT_TIMEOUT_MS * CONFIG_SYS_HZ / 1000) { > + if ((REG_RD(priv->bspi_hw + BSPI_BUSY_STATUS_REG) & 1) > + == 0) { > + REG_WR(priv->bspi_hw + > + BSPI_MAST_N_BOOT_CTRL_REG, 1); > + udelay(1); > + break; > + } > + udelay(1); > + } > + if ((REG_RD(priv->bspi_hw + BSPI_MAST_N_BOOT_CTRL_REG) & 1) > + != 1) > + return -1; > + } > + > + /* Update state */ > + priv->state = QSPI_STATE_MSPI; > + > + return 0; > +} > + > +#ifdef CONFIG_BCM_IPROC_USE_BSPI Better handle the ifdef specific via driver data? [1] https://patchwork.ozlabs.org/project/uboot/patch/20191122230939.30390-2-vladimir.olovyanni...@broadcom.com/ Jagan.