On 10/17/2019 12:22 PM, Laurentiu Tudor wrote:
> +struct icid_id_table icid_tbl[] = {
> + SET_SDHC_ICID(1, FSL_SDMMC_STREAM_ID),
> + SET_USB_ICID(1, "snps,dwc3", FSL_USB1_STREAM_ID),
> + SET_USB_ICID(2, "snps,dwc3", FSL_USB2_STREAM_ID),
> + SET_SATA_ICID(1, "fsl,ls2080a-ahci", FSL_S
On 10/17/2019 12:21 PM, Laurentiu Tudor wrote:
> From: Laurentiu Tudor
>
> If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
> compilation error happens:
> arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
> 'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (n
>-Original Message-
>From: u-boot-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>Sent: Thursday, October 17, 2019 2:52 PM
>To: u-boot@lists.denx.de; Prabhakar X
>Subject: [u-boot] [PATCH 6/6] armv8: ls1028a: erratum A050382 workaround
"Add erratum"
>
>-Original Message-
>From: u-boot-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>Sent: Thursday, October 17, 2019 2:52 PM
>To: u-boot@lists.denx.de; Prabhakar X
>Subject: [u-boot] [PATCH 4/6] armv8: fsl-layerscape: add missing SATA3 and
>SATA4 base a
>-Original Message-
>From: u-boot-boun...@linux.nxdi.nxp.com boun...@linux.nxdi.nxp.com> On Behalf Of Laurentiu Tudor
>Sent: Thursday, October 17, 2019 2:52 PM
>To: u-boot@lists.denx.de; Prabhakar X
>Subject: [u-boot] [PATCH 5/6] armv8: lx2160a: add icid setup for platform
>devices
>
>Fr
On 10/17/2019 12:21 PM, Laurentiu Tudor wrote:
> From: Laurentiu Tudor
>
> These macros should only be used when CONFIG_FSL_CAAM is present.
>
> Signed-off-by: Laurentiu Tudor
Reviewed-by: Horia Geantă
Thanks,
Horia
___
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U-Boot@li
A bug in the ZynqMP bootrom sets the PS_SYSMON_ANALOG_BUS register
at 0xFFA50914 to the wrong value 0x3201. This causes the AMS to
exchange the PS supply voltages 0 and 1. On Xilinx boards this is
not noticable since these are tied together, it's only really
noticable if banks 500 and 501 have diff
Hello Tom,
Am 16.10.2019 um 10:45 schrieb Heiko Schocher:
Hello Tom,
Am 16.10.2019 um 06:56 schrieb Heiko Schocher:
Hello Tom,
I planned to send my patches which convert the imx6 based aristainetos
boards to support DM ... building U-Boot works fine on 2 different build
machines at home, also
>-Original Message-
>From: U-Boot On Behalf Of Priyanka Jain
>Sent: Friday, October 18, 2019 10:46 AM
>To: Pankaj Bansal ; Xiaowei Bao
>; Tom Rini ; Z.q. Hou
>
>Cc: u-boot@lists.denx.de
>Subject: Re: [U-Boot] [PATCH v2] pci: layerscape: remove multiple definitions
>of SVR
>
>
>
>>-Or
>-Original Message-
>From: Pankaj Bansal
>Sent: Wednesday, October 16, 2019 3:40 PM
>To: Priyanka Jain ; Albert Aribaud
>; Simon Glass
>Cc: u-boot@lists.denx.de; Pankaj Bansal
>Subject: [PATCH] arm: freescale: ls102xa: add helper Macro to get the SVR
>
>32 bit System Version Register (S
>-Original Message-
>From: Pankaj Bansal
>Sent: Wednesday, October 16, 2019 3:43 PM
>To: Priyanka Jain ; Xiaowei Bao
>; Tom Rini ; Z.q. Hou
>
>Cc: u-boot@lists.denx.de; Pankaj Bansal
>Subject: [PATCH v2] pci: layerscape: remove multiple definitions of SVR
>
>SVR values for various nxp SO
This allows the use of PSCI calls to trusted firmware to
initiate reset and poweroff events with CONFIG_PSCI_RESET and
CONFIG_ARM_PSCI_FW. This is desirable, for example, if the target
board has implemented a custom reset or poweroff procedure in EL3.
Signed-off-by: Mathew McBride
Cc: Priyanka Ja
If the secure world reset handlers are used (via CONFIG_PSCI_RESET),
then do not use the layerscape-specific implementation.
Signed-off-by: Mathew McBride
Cc: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/c
This patch allows the use of PSCI for power operations - this is
desirable if the target board has implemented it's own power operation
handlers in Trusted Firmware/EL3.
Layerscape has it's own EFI service handlers for power operations - if
PSCI is used the generic handlers will be used instead.
Hi Simon,
On Fri, Oct 18, 2019 at 10:22 AM Simon Glass wrote:
>
> Hi,
>
> On Thu, 17 Oct 2019 at 08:28, Simon Glass wrote:
> >
> > Hi Vignesh,
> >
> > On Wed, 16 Oct 2019 at 04:28, Vignesh Raghavendra wrote:
> > >
> > > Hi Simon,
> > >
> > > On 12/10/19 10:03 AM, Bin Meng wrote:
> > > > Hi Simo
Hi,
On Thu, 17 Oct 2019 at 08:28, Simon Glass wrote:
>
> Hi Vignesh,
>
> On Wed, 16 Oct 2019 at 04:28, Vignesh Raghavendra wrote:
> >
> > Hi Simon,
> >
> > On 12/10/19 10:03 AM, Bin Meng wrote:
> > > Hi Simon,
> > >
> > > On Sat, Oct 12, 2019 at 11:08 AM Simon Glass wrote:
> > >>
> > >> Hi Bin,
Hi Tom,
On Thu, Oct 17, 2019 at 11:12 PM Tom Rini wrote:
>
> On Thu, Oct 17, 2019 at 11:02:47PM +0800, Bin Meng wrote:
> > Hi Tom,
> >
> > On Thu, Oct 17, 2019 at 10:10 PM Tom Rini wrote:
> > >
> > > On Thu, Oct 17, 2019 at 09:50:57AM +0800, Bin Meng wrote:
> > > > Hi Tom,
> > > >
> > > > On Thu
On Thu, Oct 17, 2019 at 02:05:05PM +, liu hao wrote:
> This adds platform code and the device tree for the Phytium Durian Board.
> The initial support comprises the UART the GMAC and the PCIE.
>
> v3:
> - Change the board name from ft2004 to durian.
> The dts does not on mainline Kernel. @
The instructions in doc/README.rockchip for installing rock64-rk3328
make use of u-boot.itb, but it is not built by default.
Add u-boot.itb to BUILD_TARGET for RK3328 platforms.
Signed-off-by: Vagrant Cascadian
---
Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Kco
Rockchip has documentation file, doc/README.rockchip but
which is not so readable to add or understand the existing
contents. Even the format that support is legacy readme
in U-Boot.
Add rockchip specific documentation file using new rst
format, which describes the information about Rockchip
suppo
idbloader.img name is specific to rockchip, where it usually
created using rockchip tools. Since the image is created as
per U-Boot generic builds like SPL, better to follow the
generic U-Boot naming notation like other SoC's following.
Enable idbloader.img with u-boot-spl-rockchip.bin and create
TPL-based rockchip platform like rk3288, rk3328, rk3368
and rk3399 has three stage boot loaders like TPL, SPL and
U-Boot proper. For each stage we need to burn the image
on to flash with respective offsets.
This patch create a single image using binman, so that
user can get rid of burning differen
Add U-Boot specific dtsi file for rk3368 SoC. This
would help to add U-Boot specific dts nodes, properties
which are common across rk3368.
Right now, the file is empty, will add required changes
in future patches.
Signed-off-by: Jagan Teki
---
arch/arm/dts/rk3368-geekbox-u-boot.dtsi | 2 ++
arc
Add rockchip image type support. right now the image
type marked with rksd, So create image type variable
with required image type like rksd or rkspi.
Cc: Kever Yang
Cc: Matwey V. Kornilov
Signed-off-by: Jagan Teki
---
Makefile | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
dif
This is v3 set for Binman support in rockchip, [1] here is
previous patchset.
This series add binman support for TPL-based targets,
binman for SPL-alone boards add in future.
Changes for v3:
- rebase on master
- add binman for rk3288, rk3328, rk3368, rk3399
- added rst documentation for rockchip
mtk_clk_find_parent_rate is calling clk_get_rate to know the rate
of a parent clock. clk_get_rate returns a ulong, while
mtk_clk_find_parent_rate returns an int. This implicit cast creates
an issue for clock rates big enough to need the full 32 bits to
store its data. When that happen the clk rate
On 10/17/19 4:05 PM, liu hao wrote:
v3:
- Change the board name from ft2004 to durian.
The dts does not on mainline Kernel. @ Kever Yang
- Add pcie driver and boot kernel from scsi-pci card.
Add README about durian board.
The system initialization is worked in BPF that
we do not want
Hi All,
On 10/17/2019 12:12 AM, Patrick Wildt wrote:
On Thu, Oct 17, 2019 at 03:08:59PM +0800, Bin Meng wrote:
Hi Patrick,
On Thu, Oct 17, 2019 at 2:44 PM Patrick Wildt wrote:
On Thu, Oct 17, 2019 at 10:55:11AM +0800, Bin Meng wrote:
Hi Patrick,
On Wed, Oct 16, 2019 at 11:35 PM Patrick Wild
On Tue, Oct 15, 2019 at 06:25:19PM +0900, AKASHI Takahiro wrote:
> On Tue, Oct 15, 2019 at 07:33:18AM +0200, Heinrich Schuchardt wrote:
> > On 10/15/19 5:18 AM, AKASHI Takahiro wrote:
> > >On Sat, Oct 12, 2019 at 03:02:09PM +0200, Heinrich Schuchardt wrote:
> > >>On 10/11/19 9:55 AM, AKASHI Takahir
On Thu, Oct 17, 2019 at 11:02:47PM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Thu, Oct 17, 2019 at 10:10 PM Tom Rini wrote:
> >
> > On Thu, Oct 17, 2019 at 09:50:57AM +0800, Bin Meng wrote:
> > > Hi Tom,
> > >
> > > On Thu, Oct 17, 2019 at 2:20 AM Tom Rini wrote:
> > > >
> > > > On Wed, Oct 16, 201
Hi Tom,
On Thu, Oct 17, 2019 at 10:10 PM Tom Rini wrote:
>
> On Thu, Oct 17, 2019 at 09:50:57AM +0800, Bin Meng wrote:
> > Hi Tom,
> >
> > On Thu, Oct 17, 2019 at 2:20 AM Tom Rini wrote:
> > >
> > > On Wed, Oct 16, 2019 at 09:27:25AM -0700, Bin Meng wrote:
> > >
> > > > This adds a reST document
On Tue, 2019-10-15 at 21:40 -0600, Simon Glass wrote:
> Hi Robert,
>
> On Tue, 15 Oct 2019 at 09:55, Robert Beckett <
> bob.beck...@collabora.com> wrote:
> > Some devices (2 wire eeproms for example) use some bits from the
> > chip
> > address to represent the high bits of the offset instead of or
Hi Vignesh,
On Wed, 16 Oct 2019 at 04:28, Vignesh Raghavendra wrote:
>
> Hi Simon,
>
> On 12/10/19 10:03 AM, Bin Meng wrote:
> > Hi Simon,
> >
> > On Sat, Oct 12, 2019 at 11:08 AM Simon Glass wrote:
> >>
> >> Hi Bin,
> >>
> >> On Wed, 9 Oct 2019 at 07:55, Bin Meng wrote:
> >>>
> >>> Hi Simon,
>
On Thu, Oct 17, 2019 at 09:50:57AM +0800, Bin Meng wrote:
> Hi Tom,
>
> On Thu, Oct 17, 2019 at 2:20 AM Tom Rini wrote:
> >
> > On Wed, Oct 16, 2019 at 09:27:25AM -0700, Bin Meng wrote:
> >
> > > This adds a reST document for how to build U-Boot host tools,
> > > including information for both Li
This adds platform code and the device tree for the Phytium Durian Board.
The initial support comprises the UART the GMAC and the PCIE.
v3:
- Change the board name from ft2004 to durian.
The dts does not on mainline Kernel. @ Kever Yang
- Add pcie driver and boot kernel from scsi-pci card.
Add
Hi, Simon, Vignesh,
On 10/17/2019 02:20 PM, Simon Goldschmidt wrote:
> On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>> Current Cadence QSPI driver has few limitations. It assumes all read
>> operations to be in Quad mode and thus does not support SFDP parsing.
>> Also, adding suppor
On 16/10/19 16:57, Jun Nie wrote:
> Stefano Babic 于2019年10月13日周日 下午9:35写道：
>>
>> Hi Jun,
>>
>> I am just trying to check if some patch was silently lost, I found yours:
>>
>> On 16/07/19 09:42, Jun Nie wrote:
>>> Polish uart clock id definition. Default IMX7 UART ID is UART1
>>> as original parame
Hi Marek,
On Tue, Oct 15, 2019 at 1:27 PM Marek Vasut wrote:
>
> According to IMX28CEC rev. 4, 10/2018, Table 15. Recommended Operating
> Conditions, page 16, the VDDD should be set to 1.55V when the CPU is
> operating at 454MHz. This is the case in U-Boot, hence increase the
> VDDD voltage. This
On Thu, Oct 17, 2019 at 2:44 PM Vignesh Raghavendra wrote:
>
> Hi,
>
> On 17/10/19 5:09 PM, Simon Goldschmidt wrote:
> > On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
> >>
> >> Add support for Direct Access Controller mode of Cadence QSPI. This
> >> allows MMIO access to SPI NOR flas
Hi,
On 17/10/19 5:09 PM, Simon Goldschmidt wrote:
> On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>>
>> Add support for Direct Access Controller mode of Cadence QSPI. This
>> allows MMIO access to SPI NOR flash providing better read performance.
>>
>> Signed-off-by: Vignesh R
>> Sig
Hi Simon,
On 17/10/19 4:50 PM, Simon Goldschmidt wrote:
> On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>>
>> Current Cadence QSPI driver has few limitations. It assumes all read
>> operations to be in Quad mode and thus does not support SFDP parsing.
>> Also, adding support for new
On Thu, Oct 17, 2019 at 5:52 AM Claudius Heine wrote:
>
> imx6_is_bmode_from_gpr10 always returns false, because
> IMX6_SRC_GPR10_BMODE is 1<<28 and gets casted to u8 on return.
>
> This changes the return type to bool in order to cast correctly.
>
> Signed-off-by: Claudius Heine
Reviewed-by: Fa
On Wed, Oct 16, 2019 at 10:28 AM Claudius Heine wrote:
>
> Signed-off-by: Claudius Heine
Reviewed-by: Fabio Estevam
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On Thu, Oct 17, 2019 at 5:52 AM Claudius Heine wrote:
>
> The only register used in that function is gpr10, which is used to store
> the flag. So naming it after this makes sense.
>
> Signed-off-by: Claudius Heine
Reviewed-by: Fabio Estevam
___
U-Boot
On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>
> Add support for Direct Access Controller mode of Cadence QSPI. This
> allows MMIO access to SPI NOR flash providing better read performance.
>
> Signed-off-by: Vignesh R
> Signed-off-by: Vignesh Raghavendra
I've tested this on my so
On Tue, Oct 15, 2019 at 10:28:45AM +0200, Lukasz Majewski wrote:
> This commit adds falcon boot support (by also copying args necessary for
> booting) to the SPL NOR memory driver.
>
> After this change it is possible to use the falcon boot in the same way
> as on NAND memories. The necessary con
On Tue, Oct 15, 2019 at 07:27:13AM -0400, Tom Rini wrote:
> - Split "tqc" and "technexion" out into their own jobs and exclude
> them from the catch-all jobs
> - Clarify the job labels a little more.
>
> Cc: Stefano Babic
> Signed-off-by: Tom Rini
> Acked-by: Stefano Babic
Applied to u-boot
On Tue, Oct 15, 2019 at 07:27:14AM -0400, Tom Rini wrote:
> Split the 32bit and 64bit platforms into separate jobs, to avoid them
> taking too long to build overall.
>
> Cc: Jagan Teki
> Signed-off-by: Tom Rini
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Oct 15, 2019 at 09:53:22AM -0400, Tom Rini wrote:
> Split the ARMv7 and AArch64 platforms into separate jobs, to avoid them
> taking too long to build overall. Also rename them from "Xilinx" to
> "Zynq*" to reflect slightly better what is being built and to pull in a
> few more board matc
On Tue, Oct 08, 2019 at 08:54:49PM +0200, Heinrich Schuchardt wrote:
> U-Boot cannot be built for h2200_defconfig with CONFIG_DM=y.
>
> The maintainer Lukasz Dalek suggested to remove the board.
> https://lists.denx.de/pipermail/u-boot/2019-August/380685.html
>
> Cc: Lukasz Dalek
> Signed-off-b
On Thu, Aug 15, 2019 at 08:25:07PM +0300, Sam Protsenko wrote:
> In new versions of Android Boot Image next fields are added to the
> header (and corresponding payloads are added to the image itself):
> - v1: Recovery DTBO
> - v2: DTB
>
> Account for these new fields in next functions:
> 1.
On Fri, Aug 09, 2019 at 03:31:29PM +0300, Sam Protsenko wrote:
> As android_image.h uses types like u32, we need to include corresponding
> headers in place. Otherwise the user will be forced to include those in
> C file, or next build error can occur:
>
> include/android_image.h:32:5: error:
On Thu, Oct 10, 2019 at 05:33:09PM -0400, Tom Rini wrote:
> Fully take over the ARM maintainers entry.
>
> Signed-off-by: Tom Rini
> Reviewed-by: Bin Meng
> Reviewed-by: Neil Armstrong
Applied to u-boot/master, thanks!
--
Tom
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__
On Tue, Oct 08, 2019 at 09:12:45PM +0300, Andy Shevchenko wrote:
> cscope complains that it can't find files that appears to be symbolic links
>
> cscope: cannot find file tools/binman/test/u_boot_binman_syms_bad.c
> cscope: cannot find file tools/version.h
>
> `find -L` tests properties, but na
On Tue, Oct 15, 2019 at 08:46:46AM -0600, Simon Glass wrote:
> Hi Tom,
>
> https://gitlab.denx.de/u-boot/custodians/u-boot-dm/pipelines/950
>
>
> The following changes since commit 6891152a4596d38ac25d2fe1238e3b6a938554b8:
>
> Merge branch 'master' of git://git.denx.de/u-boot-socfpga
> (2019
On Mon, Oct 14, 2019 at 3:27 PM Vignesh Raghavendra wrote:
>
> Current Cadence QSPI driver has few limitations. It assumes all read
> operations to be in Quad mode and thus does not support SFDP parsing.
> Also, adding support for new mode such as Octal mode would not be
> possible with current co
On Thu, Oct 17, 2019 at 5:22 AM Patrick Wildt wrote:
>
> It's possible that the data cache for the buffer still holds data
> to be flushed to memory, since the buffer was probably used as stack
> before. Thus we need to make sure to flush it also on reads, since
> it's possible that the cache is
From: Laurentiu Tudor
Description:
The eDMA ICID programmed in the eDMA_AMQR register in DCFG is not
correctly forwarded to the SMMU.
Workaround:
Program eDMA ICID in the eDMA_AMQR register in DCFG to 0x28.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/lx2160_ids.c | 48 +++
arch/arm/cpu/armv8/fsl-la
From: Laurentiu Tudor
There are chips that have 4 sata controllers. Add missing base
addresses for SATA3 and SATA4.
Signed-off-by: Laurentiu Tudor
---
arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/arch-fsl-laye
From: Laurentiu Tudor
Add ICID setup for the platform devices contained on this chip: usb,
sata, sdhc, sec.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/Makefile| 1 +
.../arm/cpu/armv8/fsl-layerscape/ls2088_ids.c | 33 +++
arch/arm/cpu/armv8/fsl-la
From: Laurentiu Tudor
If SEC FW support is not enabled (ARMV8_SEC_FIRMWARE_SUPPORT=n) this
compilation error happens:
arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h:169:4: error:
'CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT' undeclared here (not in a function)
Fix it by adding an intermediate macro t
From: Laurentiu Tudor
These macros should only be used when CONFIG_FSL_CAAM is present.
Signed-off-by: Laurentiu Tudor
---
arch/arm/cpu/armv8/fsl-layerscape/ls1028_ids.c | 2 ++
arch/arm/cpu/armv8/fsl-layerscape/ls1088_ids.c | 2 ++
2 files changed, 4 insertions(+)
diff --git a/arch/arm/cpu/a
> On 17.10.2019, at 09:22, d...@t-chip.com.cn wrote:
>
> From: Levin Du
>
> Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
> as expected. When board_boot_order() `spl-boot-order.c` meets
> "same-as-spl", it gets the conf by looking the boot_devices table by boot
> s
> From: d...@t-chip.com.cn
> Date: Thu, 17 Oct 2019 15:22:38 +0800
>
> From: Levin Du
>
> Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
> as expected. When board_boot_order() `spl-boot-order.c` meets
> "same-as-spl", it gets the conf by looking the boot_devices table
Hi all, I have difficulties with TPL in the firefly-rk3288 board.
1. Without defining DEBUG in `drivers/mmc/dw_mmc.c`, boot with TF card:
U-Boot TPL 2019.10-00017-g5b02ac7fa5dd-dirty (Oct 17 2019 - 16:36:39)
Trying to boot from BOOTROM
Returning to boot ROM...
U-Boot SPL 2019.10-
On Tue, Oct 15, 2019 at 04:17:04PM +0900, AKASHI Takahiro wrote:
> On Sat, Oct 12, 2019 at 02:47:33PM +0200, Heinrich Schuchardt wrote:
> > On 10/10/19 3:04 AM, AKASHI Takahiro wrote:
> > >On Wed, Oct 09, 2019 at 07:56:04PM +0200, Heinrich Schuchardt wrote:
> > >>On 10/9/19 7:30 AM, AKASHI Takahiro
From: Levin Du
Without the prefix, "same-as-spl" in `u-boot,spl-boot-order` will not work
as expected. When board_boot_order() `spl-boot-order.c` meets
"same-as-spl", it gets the conf by looking the boot_devices table by boot
source, and parse the node by the conf with:
node = fdt_path_offset
On Thu, Oct 17, 2019 at 03:08:59PM +0800, Bin Meng wrote:
> Hi Patrick,
>
> On Thu, Oct 17, 2019 at 2:44 PM Patrick Wildt wrote:
> >
> > On Thu, Oct 17, 2019 at 10:55:11AM +0800, Bin Meng wrote:
> > > Hi Patrick,
> > >
> > > On Wed, Oct 16, 2019 at 11:35 PM Patrick Wildt wrote:
> > > >
> > > > O
Hi Patrick,
On Thu, Oct 17, 2019 at 2:44 PM Patrick Wildt wrote:
>
> On Thu, Oct 17, 2019 at 10:55:11AM +0800, Bin Meng wrote:
> > Hi Patrick,
> >
> > On Wed, Oct 16, 2019 at 11:35 PM Patrick Wildt wrote:
> > >
> > > On Wed, Oct 16, 2019 at 06:11:23PM +0800, Bin Meng wrote:
> > > > On Mon, Oct 1
On Sat, Oct 12, 2019 at 02:29:49PM +0200, Heinrich Schuchardt wrote:
> On 10/11/19 9:41 AM, AKASHI Takahiro wrote:
> >Imported from linux kernel v5.3.
> >
> >Signed-off-by: AKASHI Takahiro
> >---
> > lib/Kconfig| 6 +
> > lib/Makefile | 1 +
> > lib/asn1_decoder.c | 527
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