Hi Peng,
> Add i.MX8MM clk driver support.
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/imx/Makefile | 2 +
> drivers/clk/imx/clk-imx8mm.c | 414
> +++
> 2 files changed, 416 insertions(+)
> create mode 100644 drivers/clk/imx/clk-imx8mm.c
>
>
Hi Peng,
> Add pll14xx driver
>
> Signed-off-by: Peng Fan
> ---
> drivers/clk/imx/clk-pll14xx.c | 371
> ++
> drivers/clk/imx/clk.h | 25 +++
> 2 files changed, 396 insertions(+)
> create mode 100644 drivers/clk/imx/clk-pll14xx.c
>
> diff --gi
> Subject: [PATCH v2 01/11] imx: tpc70: config: Add script commands to update
> u-boot and OE's wic
>
> Signed-off-by: Lukasz Majewski
> ---
>
> include/configs/kp_imx6q_tpc.h | 21 +
> 1 file changed, 21 insertions(+)
>
> diff --git a/include/configs/kp_imx6q_tpc.h b/inclu
Currently dozens of boards still do not use the driver model for the
network devices. This makes integration between devices in the UEFI
sub-system with the U-Boot devices complicated.
See: https://travis-ci.org/xypron2/u-boot/builds/569675547
In doc/driver-model/migration.rst I am missing a mig
On 8/8/19 1:21 PM, Harald Seiler wrote:
Hi Heinrich,
On Wed, 2019-08-07 at 21:26 +0200, Heinrich Schuchardt wrote:
Hello Harald,
Tom suggested you could help on this issue.
I suggest that the pipeline status should be public on all custodian
gits, e.g. page
https://gitlab.denx.de/u-boot/custo
Hi Angus,
Hi Sherry,
On Aug. 8, 2019 2:38 a.m., Sherry Sun
mailto:sherry@nxp.com>> wrote:
Hi Angus,
Sorry for the late reply.
> -邮件原件-
> 发件人: Angus Ainslie mailto:an...@akkea.ca>>
> 发送时间: 2019年8月2日 10:30
> 收件人: Peng Fan mailto:peng@nxp.com>>
> 抄送: Sherry Sun mailto:sherry
From: Yegor Yefremov
Also disable OMAP watchdog timer till it is converted to the
driver model.
Signed-off-by: Yegor Yefremov
---
configs/am335x_baltos_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/am335x_baltos_defconfig b/configs/am335x_baltos_defconfig
index aa8fe
From: Yegor Yefremov
The full path has changed in the recent kernels so that it is
not possible to load them. Aliases "ethernet0" and "ethernet1"
are still present in both legacy and new kernels.
Also, fix error messages to correspond to the taken actions.
Signed-off-by: Yegor Yefremov
---
bo
i.MX8MQ and i.MX8MM use different analog pll design, but they
share same ccm design.
Add clock_imx8mq.h for i.MX8MQ
keep common part in clock.h
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/clock.h| 491 +++--
arch/arm/include/asm/arch-imx8m/clock_imx8mq
Add board and SoC dts
Add ddr training code
support SD/MMC/GPIO/PINCTRL/UART
Signed-off-by: Peng Fan
---
arch/arm/dts/Makefile |3 +-
arch/arm/dts/imx8mm-evk-u-boot.dtsi| 92 ++
arch/arm/dts/imx8mm-evk.dts| 235
arch/arm/mach-imx/imx8m/Kco
i.MX8MQ and i.MX8MM has totally different pll design, so
rename clock to clock_imx8mq.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Makefile| 3 ++-
arch/arm/mach-imx/imx8m/{clock.c => clock_imx8mq.c} | 0
2 files changed, 2 insertions(+), 1 deletion(-)
rename arch/ar
When running with OPTEE, the MMU table in u-boot does not remove the OPTEE
memory from its settings. So ARM speculative prefetch in u-boot may access
that OPTEE memory. Due to trust zone is enabled by OPTEE and that memory
is set to secure access, then the speculative prefetch will fail and cause
v
From: Ye Li
Set trustzone region 0 to allow both non-secure and secure access
when trust zone is enabled. We found USB controller fails to access
DDR if the default region 0 is secure access only.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++
1 fil
Add pin header file for i.MX8MM
To IMX8MM_PAD_NAND_WE_B_USDHC3_CLK, IOMUX_CONFIG_SION needs to be
selected.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/imx8mm_pins.h | 691 ++
1 file changed, 691 insertions(+)
create mode 100644 arch/arm/include/asm/arch
set the BYPASS ID SWAP bit (GPR10 bit 1) in order for GPU not to
generated AXI bus errors with TZC380 enabled.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index dd393
i.MX8MM does not have LVTTL, it has a PE property
Signed-off-by: Peng Fan
---
arch/arm/include/asm/mach-imx/iomux-v3.h | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/include/asm/mach-imx/iomux-v3.h
b/arch/arm/include/asm/mach-imx/iomux-v3.h
index b899a4ff6f..720e8f7043 100644
Introduce clk implementation for i.MX8MM, including pll configuration,
ccm configuration. Mostly will be done clk dm driver,
but such as DRAM part, we still use non clk dm driver, because we
have limited sram.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/clock.h| 2 +
ar
Import i.MX8MM dtsi from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm.dtsi | 733 +++
1 file changed, 733 insertion
i.MX8MM has similar architecture with i.MX8MQ, but it has totally
different PLL design and some register layout change.
Note: Some registers in this file are not updated because not used now.
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx8m/imx-regs.h | 75 +++
Add i.MX8MM cpu type and related helper functions
Signed-off-by: Peng Fan
---
arch/arm/include/asm/arch-imx/cpu.h | 6 ++
arch/arm/include/asm/mach-imx/sys_proto.h | 8
arch/arm/mach-imx/cpu.c | 12
3 files changed, 26 insertions(+)
diff --git
To i.MX8MM SCTR clock is disabled by ROM, so before timer init
need to enable it.
To i.MX8MQ, it does not hurt the clock is enabled again.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/
Import i.MX8MM pin func from Linux Kernel,
commit <0a8ad0ffa4d8> ("Merge tag 'for-linus-5.3-ofs1' of
git://git.kernel.org/pub/scm/linux/kernel/git/hubcap/linux")
Signed-off-by: Peng Fan
---
arch/arm/dts/imx8mm-pinfunc.h | 629 ++
1 file changed, 629 inser
Differnet board has different controller used, it is
hard to use one layout for them all.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/spl.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-imx/spl.c b/arch/arm/mach-imx/spl.c
index 1f230aca33..7ada60d7a2 100644
--- a/ar
Add IMX8MM kconfig entry
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Kconfig | 4
1 file changed, 4 insertions(+)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 9c487870a6..35c978e863 100644
--- a/arch/arm/mach-imx/imx8m/Kconfig
+++ b/arch/arm/
There are several variants based on i.MX8MM, add the support in
get_cpu_rev
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/soc.c | 57 +++
1 file changed, 47 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-im
Import clock bindings header file from Linux 5.3.0-rc2
Signed-off-by: Peng Fan
---
include/dt-bindings/clock/imx8mm-clock.h | 253 +++
1 file changed, 253 insertions(+)
create mode 100644 include/dt-bindings/clock/imx8mm-clock.h
diff --git a/include/dt-bindings/cloc
There is no HDMI on i.MX8MM, so we need to remove HDMI entry, then
we could not reuse imximage.cfg, so create a new one.
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/imximage-8mm-lpddr4.cfg | 16
1 file changed, 16 insertions(+)
create mode 100644 arch/arm/mach-imx/imx8m
With SPL_OF_SPERATE, the device tree will be padded to
end of the u-boot-spl-nodtb.bin, however we also put
the ddr firmware file to this location, so need to adapt
the code with SPL OF and align to 16bytes to ease copy firmware.
Signed-off-by: Peng Fan
---
drivers/ddr/imx/imx8m/helper.c | 12 ++
Align spl bin image size to 4 byte aligned, because we need
to pad ddr firmware in the end of spl bin. However when enable
SPL OF, the spl dtb will be padded to u-boot-nodtb.bin, then
u-boot-spl.bin size might not be 4 bytes aligned.
ddr_load_train_firmware in drivers/ddr/imx/imx8m/helper.c use 4
Add IMX8MQ kconfig entry, preparing support IMX8MM
Signed-off-by: Peng Fan
---
arch/arm/mach-imx/imx8m/Kconfig | 6 +-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig
index 317dee9bc1..9c487870a6 100644
--- a/arch
This is a splitted and updated patch from
https://patchwork.ozlabs.org/cover/1128799/ which is to support both
i.MX8MM and i.MX8MN.
This patchset only covers i.MX8MM and depends on the following patch
to work,
https://patchwork.ozlabs.org/cover/1144317/
https://patchwork.ozlabs.org/patch/1142686/
Add i.MX8MM clk driver support.
Signed-off-by: Peng Fan
---
drivers/clk/imx/Makefile | 2 +
drivers/clk/imx/clk-imx8mm.c | 414 +++
2 files changed, 416 insertions(+)
create mode 100644 drivers/clk/imx/clk-imx8mm.c
diff --git a/drivers/clk/imx/Make
Add pll14xx driver
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-pll14xx.c | 371 ++
drivers/clk/imx/clk.h | 25 +++
2 files changed, 396 insertions(+)
create mode 100644 drivers/clk/imx/clk-pll14xx.c
diff --git a/drivers/clk/imx/clk-pll14xx.c
Add Kconfig entry for i.MX8MM
Signed-off-by: Peng Fan
---
drivers/clk/Kconfig | 4 ++--
drivers/clk/imx/Kconfig | 16
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/clk/Kconfig b/drivers/clk/Kconfig
index a3f0171b45..fce595b4b3 100644
--- a/drivers/
Import i.MX8M composite clk from Linux Kernel 5.3.0-rc2
Signed-off-by: Peng Fan
---
drivers/clk/imx/clk-composite-8m.c | 170 +
1 file changed, 170 insertions(+)
create mode 100644 drivers/clk/imx/clk-composite-8m.c
diff --git a/drivers/clk/imx/clk-composite
V2:
2/4: fix MASK/SHIFT usage
4/4: ARM clk not use 24M for switch, use pll2_500m
Add R-b/A-b tag
This is to support i.MX8MM clk driver.
i.MX8MM use similar clock design as i.MX7D, but it has
use different PLL, so we need to add pll14xx driver.
And to simplify the clock usage, import the compos
Hi Marek,
On Thu, Aug 8, 2019 at 1:02 AM Marek Behún wrote:
>
> The non-DM version of this driver used to set BAR0 register after the
> calls to pci_set_region.
> I found out that for some strange reason the ath10k driver in kernel
> fails to work if this is done the other way around.
> I know th
On Mon, Aug 05, 2019 at 04:46:43PM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the following watchdog related patches:
>
Applied to u-boot/master, thanks!
--
Tom
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On Thu, Aug 8, 2019 at 10:54 PM Bin Meng wrote:
>
> On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
> >
> > On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
> > >
> > > Add slimbootloader board to run U-boot as a Slim Bootloader payload
> > > - Add new board/intel/slimbootloader directory with
> Subject: Re: [U-Boot] [PATCH 1/3] spl: imx6: Let spl_boot_device return
> USDHC1 or USDHC2
>
> On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti
> wrote:
> >
> > Hi Adam,
> >
> > On Thu, May 23, 2019 at 4:11 PM Adam Ford
> wrote:
> > >
> > > Currently, when the spl_boot_device checks the boot dev
Hi Troy,
> -Original Message-
> From: Troy Kisky
> Sent: 2019年8月9日 3:52
> To: Peng Fan ; sba...@denx.de; feste...@gmail.com
> Cc: u-boot@lists.denx.de; Jacky Bai ; dl-uboot-imx
>
> Subject: Re: [U-Boot] [PATCH 3/4] driver: ddr: Refine the ddr init driver on
> imx8m
>
> On 8/8/2019 2:59
Noncached area at present is being initialized to random space after malloc
area. It works in most the cases as it goes to stack area & stack is not
overwriting it being far from it.
Signed-off-by: Vikas Manocha
---
common/board_f.c | 13 +
1 file changed, 13 insertions(+)
diff --gi
Hi Joe,
On 7/25/2019 9:41 PM, Joe Hershberger wrote:
Hi Alex,
https://patchwork.ozlabs.org/patch/1132514/ was applied to
http://git.denx.de/?p=u-boot/u-boot-net.git
can you please check this commit (d9a9174), I think mdio_mux_i2creg.c
was lost at merge.
Do you want me to send a new patch wit
Am 08.08.2019 um 21:43 schrieb Andreas Dannenberg:
Hi Simon,
On Thu, Aug 08, 2019 at 09:01:03PM +0200, Simon Goldschmidt wrote:
Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg:
Ok back to my specific scenario, hopefully I'm adding at least some new
aspects now rather than repeating what
On 8/8/2019 2:59 AM, Peng Fan wrote:
> From: Jacky Bai
>
> Refine the ddr init driver to make it more reusable for different
> DDR type(LPDDR4, DDR4 & DDR3L). So we can reduce some redundant
> code.
>
> Signed-off-by: Jacky Bai
> Reviewed-by: Ye Li
> Signed-off-by: Peng Fan
> ---
> drivers/d
Hi Simon,
On Thu, Aug 08, 2019 at 09:01:03PM +0200, Simon Goldschmidt wrote:
> Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg:
> > Ok back to my specific scenario, hopefully I'm adding at least some new
> > aspects now rather than repeating what was discussed already in different
> > threads
On 8/8/2019 7:45 PM, Alex Marginean wrote:
The main purpose of this patch series is to allow the AQR driver to run on
a larger number of boards without having to use a custom aquantia FW on each
of them. Configuration points that are exclusively controlled by PHY firmware
are not configured base
On 8/8/2019 7:07 PM, Alex Marginean wrote:
The driver sets up the switch during probe making external and internal ports
available to use. It does not support direct I/O through these switch ports
in this version and I'm not sure that is a feature useful in U-Boot. Instead
ENETC ethernet interf
Am 08.08.2019 um 20:29 schrieb Andreas Dannenberg:
Simon,
On Thu, Aug 08, 2019 at 09:29:03AM +0200, Simon Goldschmidt wrote:
Hi Andreas,
On Wed, Aug 7, 2019 at 11:24 PM Andreas Dannenberg wrote:
Hi Simon,
thanks for your patience waiting for a response. Please see comments inlined...
On Th
On Thu, Aug 8, 2019 at 1:14 PM Robert Hancock wrote:
>
> Previously the SPL size on all iMX6 platforms was restricted to 68KB
> because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the
> other iMX6 variants have 256KB of OCRAM. Add an option
> CONFIG_MX6_OCRAM_256KB which allows using
Simon,
On Thu, Aug 08, 2019 at 09:29:03AM +0200, Simon Goldschmidt wrote:
> Hi Andreas,
>
> On Wed, Aug 7, 2019 at 11:24 PM Andreas Dannenberg wrote:
> >
> > Hi Simon,
> > thanks for your patience waiting for a response. Please see comments
> > inlined...
> >
> > On Thu, Jul 25, 2019 at 11:52:5
Am 08.08.2019 um 19:54 schrieb Andreas Dannenberg:
The earlier commit
commit a5a5d997b41a ("spl: Allow performing BSS init early before
board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and upd
Previously the SPL size on all iMX6 platforms was restricted to 68KB
because the OCRAM size on iMX6SL/DL parts is only 128KB. However, the
other iMX6 variants have 256KB of OCRAM. Add an option
CONFIG_MX6_OCRAM_256KB which allows using the full size on boards which
don't need to support the SL/DL v
The earlier commit
commit a5a5d997b41a ("spl: Allow performing BSS init early before
board_init_f()")
...introduced the ability to use BSS from SPL's board_init_f() as it may
be required in certain exceptional use cases so go ahead and update the
README to reflect this change. Note that as h
Uses the data field in phy_driver structure to identify the PHY generation.
This is useful for custom configuration as non-generic PHY registers are
not 100% compatible between generations.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 11 +++
1 file changed, 11 insertio
This is useful to carry custom information between the driver structure
associated with a specific HW and the driver code.
Signed-off-by: Alex Marginean
---
include/phy.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/phy.h b/include/phy.h
index f4530faeb9..58455d6493 100644
---
Aquantia PHYs have a SMBus interface mostly used for debug. The addresses
on this interface are normally set up by PHY firmware, but depending on the
board they may end up not being unique. Add an optional DT property used
to change SMBus address if needed.
Signed-off-by: Alex Marginean
---
dr
In some cases the link on the system interface of the aquantia PHY comes up
after the link on line interface. The link state loop only checks the line
side, which may result in first packet sent being lost.
Use aquantia_link_is_up instead, which checks both system and line side on
gen 2/3 PHYs to
MDI pins up to the RJ45 connector may be reversed on the board and the
default PHY configuration applied by firmware may or may not match that.
Add an optional DT property to configure MDI reversal for this case.
Signed-off-by: Alex Marginean
---
drivers/net/phy/aquantia.c | 39 +
If PHY is not ready for data by the time _config is called, reconfigure the
PHY system interface to use the proper protocol based on phydev->interface,
just in case the defaults set by PHY firmware don't match current
configuration.
Signed-off-by: Razvan Ionut Cirjan
Signed-off-by: Alex Marginean
The PHY supports XFI and USXGMII, the notable difference being that USX AN
is enabled for USXGMII. Legacy code uses XGMII for any 10G proto and
detects whether USX AN should be enabled or not using a PHY status
register. Keep that functionality too, so we don't break existing drivers.
Signed-off
Apply 10G PCS init for USXGMII, XFI interface types.
Signed-off-by: Alex Marginean
---
drivers/net/fsl_enetc.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/net/fsl_enetc.c b/drivers/net/fsl_enetc.c
index 145d66bb16..a4472c7c50 100644
--- a/drivers/net/fsl_enetc.c
+++ b/drivers/n
It defines that PHY nodes must be children on MDIO bus nodes and defines
the only required property in U-Boot, reg. This property along with the
example provided are copied over from Linux.
Signed-off-by: Alex Marginean
---
doc/device-tree-bindings/net/phy.txt | 24
1 f
A couple of optional properties have been introduced for Aquantia PHY
allowing the driver to set up wiring related configuration points that
are otherwise driven by firmware.
Signed-off-by: Alex Marginean
---
doc/device-tree-bindings/net/aquantia-phy.txt | 25 +++
1 file changed,
Drivers currently use XGMII for XFI and USXGMII and, where needed, use
other information to identify the actual protocol on the board. With these
two defined drivers can now rely on DT phy-mode property.
Signed-off-by: Alex Marginean
---
include/phy_interface.h | 4
1 file changed, 4 inser
The main purpose of this patch series is to allow the AQR driver to run on
a larger number of boards without having to use a custom aquantia FW on each
of them. Configuration points that are exclusively controlled by PHY firmware
are not configured based on phydev->interface as well as new DT node
The driver sets up the switch at probe allowing traffic though. Both the
switch as a whole and the ports are registered as network devices in
U-Boot, although neither supports direct I/O in this version. Traffic can
originate from SoC though one of the internally linked ENETC interfaces,
external
Adds a device tree node to ls1028a dtsi that describes the Ethernet switch
integrated in LS1028A SoC.
Signed-off-by: Alex Marginean
---
arch/arm/dts/fsl-ls1028a.dtsi | 31 +++
1 file changed, 31 insertions(+)
diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/
The driver sets up the switch during probe making external and internal ports
available to use. It does not support direct I/O through these switch ports
in this version and I'm not sure that is a feature useful in U-Boot. Instead
ENETC ethernet interfaces that are internally linked to the switch
Hi Lukas,
On Thu, Aug 8, 2019 at 10:03 PM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Thu, 2019-08-08 at 21:25 +0800, Bin Meng wrote:
> > Hi Lukas,
> >
> > On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas
> > wrote:
> > > Hi Bin,
> > >
> > > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> > > > We shou
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
> >
> > The setting up MTRRs have already been done in previous
> > Slim Bootloader stages.
> >
> > Signed-off-by: Aiden Park
> > Reviewed-by: Bin Meng
> > Reviewed-by: Andy Shevchenko
> > ---
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
> >
> > Add slimbootloader board to run U-boot as a Slim Bootloader payload
> > - Add new board/intel/slimbootloader directory with minimum codes
> > - Add slimbootloader configuration files
> >
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
> >
> > Slim Bootloader already calibrated TSC and provides it to U-Boot.
> > Therefore, U-Boot does not have to re-calibrate TSC.
> > Configuring tsc_base and clock_rate makes x86 tsc_timer driv
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
> >
> > Add a new device tree which has very minimum nodes
> > - x86 reset
> > - x86 tsc_timer
> > - x86 pci
> > - Slim Bootloader serial
> >
> > Signed-off-by: Aiden Park
> > Reviewed-by: Bin M
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
> >
> > Slim Bootloader provides memory map info thru its HOB list pointer.
> > Configure memory size and relocation memory from the HOB data, and
> > provide e820 entries as well.
> > - Get memo
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
> >
> > Slim Bootloader provides serial port info thru its HOB list pointer.
> > All these HOBs are eligible for Slim Bootloader based board only.
> > - Get serial port information from the seria
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> Use existing EFI_GUID and efi_guid_t instead of struct efi_guid.
> This is pre-work before making a common HOB library.
> - Change 'struct efi_guid' to efi_guit_t
> - Remove 'struct efi_guid'
> - Define GUIDs with EFI_GUID() macro
> - Use guidc
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> FSP (CONFIG_HAVE_FSP) and Slim Bootloader (CONFIG_SYS_SLIMBOOTLOADER)
> consume HOB (CONFIG_USE_HOB) data from the each HOB list pointer.
> Add a common HOB library in lib/hob.c and include/asm/hob.h.
>
> Signed-off-by: Aiden Park
> Reviewed-b
On Thu, Aug 8, 2019 at 10:44 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
> >
> > This slimbootloader CPU type is to enable U-Boot as a payload which
> > runs on top of Slim Bootloader (https://github.com/slimbootloader).
> > The Slim Bootloader is designed with multi-
On Thu, Aug 8, 2019 at 9:50 PM Bin Meng wrote:
>
> On Fri, Aug 2, 2019 at 2:38 PM Bernhard Messerklinger
> wrote:
> >
> > With the introduction of the new spi-mem model operations changed
> > slightly. The new spi-mem operations make things a bit easier to
> > handle for ich-spi flash interface.
On Sun, Jul 28, 2019 at 11:14 PM Bin Meng wrote:
>
> With qemu-x86 starting to use config_distro_bootcmd, the pre-defined
> ramboot and nfsboot commands do not work any more. This is caused by
> undefined environment variable 'ramdiskaddr' that was previously set
> in CONFIG_EXTRA_ENV_SETTINGS but
On Thu, Aug 8, 2019 at 9:31 PM Bin Meng wrote:
>
> On Fri, Aug 2, 2019 at 1:37 AM Heinrich Schuchardt wrote:
> >
> > Remove a stray break which suppresses some debug messages.
> >
> > Indicated by cppcheck.
> >
> > Signed-off-by: Heinrich Schuchardt
> > ---
> > @Simon:
> > Please, test on an x86
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> This slimbootloader CPU type is to enable U-Boot as a payload which
> runs on top of Slim Bootloader (https://github.com/slimbootloader).
> The Slim Bootloader is designed with multi-stage architecture for
> the execution from reset vector to O
Hi Aiden,
On Thu, Aug 8, 2019 at 10:35 PM Bin Meng wrote:
>
> On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
> >
> > Add slimbootloader board to run U-boot as a Slim Bootloader payload
> > - Add new board/intel/slimbootloader directory with minimum codes
> > - Add slimbootloader configuration
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
>
> The setting up MTRRs have already been done in previous
> Slim Bootloader stages.
>
> Signed-off-by: Aiden Park
> Reviewed-by: Bin Meng
> Reviewed-by: Andy Shevchenko
> ---
> arch/x86/lib/init_helpers.c | 3 ++-
> 1 file changed, 2 insertio
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
>
> Add slimbootloader board to run U-boot as a Slim Bootloader payload
> - Add new board/intel/slimbootloader directory with minimum codes
> - Add slimbootloader configuration files
> - Add doc/board/intel/slimbootloader.rst
>
> Signed-off-by: Aid
On Sat, Aug 3, 2019 at 4:31 PM Park, Aiden wrote:
>
> Add a new device tree which has very minimum nodes
> - x86 reset
> - x86 tsc_timer
> - x86 pci
> - Slim Bootloader serial
>
> Signed-off-by: Aiden Park
> Reviewed-by: Bin Meng
> Reviewed-by: Andy Shevchenko
> ---
> Changes in v3:
> * Move
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> Slim Bootloader provides serial port info thru its HOB list pointer.
> All these HOBs are eligible for Slim Bootloader based board only.
> - Get serial port information from the serial port info HOB
> - Leverage ns16550 driver with slimbootload
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> Slim Bootloader provides memory map info thru its HOB list pointer.
> Configure memory size and relocation memory from the HOB data, and
> provide e820 entries as well.
> - Get memory size from the memory map info HOB
> - Set available top memo
On Sat, Aug 3, 2019 at 4:30 PM Park, Aiden wrote:
>
> Slim Bootloader already calibrated TSC and provides it to U-Boot.
> Therefore, U-Boot does not have to re-calibrate TSC.
> Configuring tsc_base and clock_rate makes x86 tsc_timer driver bypass
> TSC calibration and use the provided TSC frequenc
On Fri, Aug 2, 2019 at 3:03 PM Park, Aiden wrote:
>
> This slimbootloader CPU type is to enable U-Boot as a payload which
> runs on top of Slim Bootloader (https://github.com/slimbootloader).
> The Slim Bootloader is designed with multi-stage architecture for
> the execution from reset vector to O
Hi Bin,
On Thu, 2019-08-08 at 21:25 +0800, Bin Meng wrote:
> Hi Lukas,
>
> On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas
> wrote:
> > Hi Bin,
> >
> > On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> > > We should not count in hart that is marked as not available in the
> > > device tree in ris
On Thu, Aug 8, 2019 at 10:13 AM Adam Ford wrote:
> On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti wrote:
> > Hi Adam,
> >
> > On Thu, May 23, 2019 at 4:11 PM Adam Ford wrote:
> > >
> > > Currently, when the spl_boot_device checks the boot device, it
> > > will only return MMC1 when it's either s
On Fri, Aug 2, 2019 at 2:38 PM Bernhard Messerklinger
wrote:
>
> With the introduction of the new spi-mem model operations changed
> slightly. The new spi-mem operations make things a bit easier to
> handle for ich-spi flash interface. This patch converts the ich-spi
> driver by using spi-mem oper
On Fri, Aug 2, 2019 at 1:37 AM Heinrich Schuchardt wrote:
>
> Remove a stray break which suppresses some debug messages.
>
> Indicated by cppcheck.
>
> Signed-off-by: Heinrich Schuchardt
> ---
> @Simon:
> Please, test on an x86 Chromebook. I have no access to a test device.
> ---
> drivers/bios_
Hi Lukas,
On Thu, Aug 8, 2019 at 7:22 PM Auer, Lukas
wrote:
>
> Hi Bin,
>
> On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> > We should not count in hart that is marked as not available in the
> > device tree in riscv_cpu_get_count().
> >
>
> I think it might make sense to also exclude harts
On Wed, Aug 7, 2019 at 6:44 PM Ricardo Salveti wrote:
>
> Hi Adam,
>
> On Thu, May 23, 2019 at 4:11 PM Adam Ford wrote:
> >
> > Currently, when the spl_boot_device checks the boot device, it
> > will only return MMC1 when it's either sd or eMMC regardless
> > of whether or not it's MMC1 or MMC2.
Hi Tom
On Thu, Aug 8, 2019 at 3:33 PM Igor Opaniuk wrote:
>
> 1. Add myself as Android A/B and AVB maintainer
> 2. Add Sam Protsenko as Designated reviewer for A/B
>
> Signed-off-by: Igor Opaniuk
>
> ---
>
> MAINTAINERS | 20
> 1 file changed, 20 insertions(+)
>
> diff --gi
1. Add myself as Android A/B and AVB maintainer
2. Add Sam Protsenko as Designated reviewer for A/B
Signed-off-by: Igor Opaniuk
---
MAINTAINERS | 20
1 file changed, 20 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index b443c5af75..5e601b5ff3 100644
--- a/MAINTAIN
Hi Bin,
On Thu, 2019-08-08 at 00:52 -0700, Bin Meng wrote:
> We should not count in hart that is marked as not available in the
> device tree in riscv_cpu_get_count().
>
I think it might make sense to also exclude harts that are not listed
as available in the available_harts mask. So the same lo
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