Hi Tom,
On 04/09/2018 06:35 AM, Tom Rini wrote:
>> I have do a lot of test and re-work in my local branch and at last make
>> it landed in
>> rockchip vendor U-Boot, with testing in most of SoCs(not including
>> rk3066/rk3188).
>> Well, I do try to split it into pieces, but I found that actually
Hi Jaehoon,
I would like to send v3 for this series, Any specific branch that you want me
to rebase the series?
Thanks,
DP
> -Original Message-
> From: Jaehoon Chung [mailto:jh80.ch...@samsung.com]
> Sent: Wednesday, January 17, 2018 8:04 AM
> To: Siva Durga Prasad Paladugu ; u-
> b...@
H Jagan,
Any further comments on this. I am waiting for your reply on some of my replies
to your comment.
Thanks,
Siva
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Siva
> Durga Prasad Paladugu
> Sent: Wednesday, February 07, 2018 3:40 PM
> To: J
This adds a very simple elf64 loader via program headers, similar
to load_elf_image_phdr() that we already have.
Signed-off-by: Bin Meng
---
cmd/elf.c | 34 ++
1 file changed, 34 insertions(+)
diff --git a/cmd/elf.c b/cmd/elf.c
index 501f935..91a04da 100644
---
This adds ELF header, program header and section header structure
defines for the 64-bit ELF image.
Signed-off-by: Bin Meng
---
include/elf.h | 43 +++
1 file changed, 43 insertions(+)
diff --git a/include/elf.h b/include/elf.h
index 6082555..b85dd8d 100
With the introduction of the elf64 loader, now we can load a 64-bit
VxWorks x86 kernel via the 'bootvx' command.
Signed-off-by: Bin Meng
---
doc/README.vxworks | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/doc/README.vxworks b/doc/README.vxworks
index b95a516..3004466
Fix various style violations in elf.h
- use correct comment format if the comment fits in just one line
- remove the ending period for the one-line comment
- use tab for the indention instead of space
- put the opening brace at the same line of a typedef/union
- remove in a 'typedef struct' for co
Hi Guillaume,
On 9 April 2018 at 21:59, Guillaume Gardet wrote:
>
>
> Le 09/04/2018 à 18:02, Guillaume Gardet a écrit :
>>
>>
>>
>> Le 09/04/2018 à 17:18, Jean-Jacques Hiblot a écrit :
>>>
>>>
>>>
>>> On 09/04/2018 16:46, Guillaume Gardet wrote:
Le 09/04/2018 à 16:21, Jean-Jac
At present two environment variables 'e820data'/'e820info' are required
to boot a VxWorks x86 kernel, but this is superfluous. The offset of
these two tables are actually at a fixed offset from the kernel memory
base address and we can provide the kernel memory base address to U-Boot
via only one v
This corrects a typo and updates several places for clarity.
Signed-off-by: Bin Meng
---
doc/README.vxworks | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/doc/README.vxworks b/doc/README.vxworks
index 3433e4f..eb1f458 100644
--- a/doc/README.vxworks
+++ b/doc/README
VxWorks bootloader stores its size at a pre-defined offset @ 0x5004.
Later when VxWorks kernel boots up and system memory information is
retrieved from the E820 table, the bootloader size will be subtracted
from the total system memory size to calculate the size of available
memory for the OS.
Exp
Fix up the memory map on Gen3 to match datasheet properly.
This simplifies the memory map setup as well, since we do
no longer need this massive complexity.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
arch/arm/mach-rmobile/cpu_info.c | 3 -
arch/arm/mach-rmobile/include/ma
Add driver for the RPC block in SPI-flash mode. This driver allows
access to a SPI NOR flash attached to the RPC block and does not
support RPC in Hyperflash mode. Note that this block is extremely
selective when communicating with the SPI NOR.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
--
Add driver for the RPC block in Hyperflash mode. This driver allows
access to a CFI Hyperflash attached to the RPC block and does not
support RPC in SPI mode.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
drivers/mtd/Kconfig | 7 +
drivers/mtd/Makefile | 1 +
drivers
Fix minor rebase omission, the else was missing which triggered
two accesses to the register on 64bit variant of the IP.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/driv
The IP requires some time to recuperate after the IO pin
properties were changed. Add a delay to assure this.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/renesas-sdhi.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mmc/renesas-sdhi.c b/driv
Make sure to wait for the command to complete altogether, including
the trailing 8 clock cycles. This prevents the driver for accidentally
writing the CMD register too fast before the previous command fully
completed.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers
There are only a few registerse used in the 16bit mode which are
32bit internally. Special-case only those in the IO accessors and
always write both halves. Any other register access is protected
from accidentally overwriting neighboring register.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc:
The HOST_MODE register must be set to 0 when the IP is operated in 16bit
mode, otherwise 16bit access to the data FIFO may fail.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/drivers/mmc
On Mon, Apr 9, 2018 at 3:05 AM, Dr. Philipp Tomsich
wrote:
>
>> On 9 Apr 2018, at 10:01, Neil Armstrong wrote:
>>
>> On 30/03/2018 18:52, Joe Hershberger wrote:
>>> Some boards expect to find more than one phy while other boards are old
>>> and need to be limited to a specific phy address. Only l
Hi Gary,
On Mon, Apr 9, 2018 at 11:40 AM, Gary Bisson
wrote:
>> #define CONFIG_EXTRA_ENV_SETTINGS \
>> - "script=boot.scr\0" \
>> - "uimage=uImage\0" \
>> "console=ttymxc1\0" \
>> "fdt_high=0x\0" \
>> "initrd_high=0x\0" \
>> - "fdt_file=imx6q-sabrel
Le 09/04/2018 à 18:02, Guillaume Gardet a écrit :
Le 09/04/2018 à 17:18, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:46, Guillaume Gardet wrote:
Le 09/04/2018 à 16:21, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:03, Guillaume Gardet wrote:
Le 09/04/2018 à 15:58, Jean-Jacques
> I think what you want is to use kernel_noload and then load/entry values
> are ignored and we use the kernel in-place.
Yes, I will try that
Thanks,
Clement
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U-Boot@lists.denx.de
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Le 09/04/2018 à 17:18, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:46, Guillaume Gardet wrote:
Le 09/04/2018 à 16:21, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:03, Guillaume Gardet wrote:
Le 09/04/2018 à 15:58, Jean-Jacques Hiblot a écrit :
On 09/04/2018 14:02, Guillaume G
Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it.
Signed-off-by: Marek Vasut
Cc: Nobuhiro Iwamatsu
---
configs/r8a7795_salvator-x_defconfig | 4
configs/r8a7795_ulcb_defconfig | 4
configs/r8a7796_salvator-x_defconfig | 4
configs/r8a7796_ulcb_defcon
Factor out the regulator handling into set_ios and add support for
selecting pin configuration based on the voltage to support UHS modes.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 52 ++---
drivers
Export the matsu_sd_{read,write}l() common register access
functions, so that they can be used by other drivers sharing
the common code.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 4 ++--
drivers/mmc/matsushita-common.h | 4
2 fi
The Renesas RCar Gen2 chips have a mix of 32bit and 16bit variants
of the IP. There is no DT property which allows discerning those,
so what Linux does is it checks the size of the register area and
if it is 0x100, the IP is 16bit, otherwise the IP is 32bit. Handle
the distinction the same way.
Si
Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/renesas-sdhi.c | 292 -
1 file changed, 290 insertions(+), 2 deletions(-)
diff --git a/driver
Handle the controller version even if quirks are set. The controller in
Renesas Gen3 SoCs does provide the version register, which indicates a
controller v10 and the controller does support internal DMA and /1024
divider.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
dri
Add a quirk to identify that the controller is Renesas RCar variant
of the Matsushita SD IP and another quirk indicating it can support
Renesas RCar HS200/HS400/SDR104 modes.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.h | 5 +
driver
Add support for 16bit mutation of the Matsushita SD IP. Since some
registers are internally 32bit, the matsu_sd_{read,write}l() has
to special-case this 16bit variant a bit.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 42 ++
Certain instances of the SD IP require more elaborate digging
in the DT to figure out which variant of the SD IP is in use.
Allow explicit passing of the quirks into the probe function.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 3 +--
Drop the ad-hoc DT caps parsing in favor of common framework function.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 23 +++
1 file changed, 7 insertions(+), 16 deletions(-)
diff --git a/drivers/mmc/matsushita-common
On the Renesas version of the IP, the /1 divider is realized by
setting the clock register [7:0] to 0xff instead of setting bit
10 of the register. Check the quirk and handle accordingly.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 3 +
Handle bus width 0 as 1-bit bus to assure valid content of
MATSU_SD_OPTION register WIDTH field.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/mmc/matsushita-common.c b/drivers/mm
The DMA READ completion flag position differs on Socionext and Renesas
SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug
and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on
them.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
driv
Add macros to generate the FIFO accessors, since the code is almost
the same with only minor differences. This is done in preparation
for adding 16bit variant of the IP.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 122 +
Drop useless check in matsu_sd_{read,write}q(), this is only ever
called to read the data from FIFO and only when 64bit variant of
the block is used anyway.
Signed-off-by: Marek Vasut
Cc: Jaehoon Chung
Cc: Masahiro Yamada
---
drivers/mmc/matsushita-common.c | 10 ++
1 file changed, 2 i
On 09/04/2018 16:46, Guillaume Gardet wrote:
Le 09/04/2018 à 16:21, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:03, Guillaume Gardet wrote:
Le 09/04/2018 à 15:58, Jean-Jacques Hiblot a écrit :
On 09/04/2018 14:02, Guillaume Gardet wrote:
Hi Jaehoon,
There are problems with SD ca
Le 09/04/2018 à 16:40, Gary Bisson a écrit :
Hi Guillaume,
Thanks for your patch! Switching the upstream nitrogen6x configuration
to distro bootcmd has been in our todo list for some time since we also
use that in our own git repo.
On Fri, Apr 06, 2018 at 12:05:48PM +0200, Guillaume GARDET wr
This patch adds smc and hvc commands, that allow issuing Secure Monitor
Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.
Add Kconfig items to allow each command can be individually enabled.
Signed-off-by: Michalis Pappas
---
cmd/Kconfig | 14 ++
cmd/Makefile |
Make it possible to use gcc code coverage analysis.
v1 -> v2:
- Kconfig: remove not needed 'default n'
- Makefile: use consistent spacing
Signed-off-by: Christian Gmeiner
---
.gitignore | 4
Kconfig| 7 +++
Makefile | 6 ++
3 files changed, 17 insertions(+)
diff --git a/.g
On Sun, Apr 01, 2018 at 09:22:37AM +, Alex Kiernan wrote:
> When compiling without CONFIG_CLOCK_SYNTHESIZER (which is implied by
> CONFIG_DRIVER_TI_CPSW for am335x_evm), exclude the network setup for
> AM335x-ICEv2 to avoid link time failures:
>
> board/ti/am335x/board.c:683: undefined refe
On Sun, Apr 01, 2018 at 09:22:38AM +, Alex Kiernan wrote:
> In order that we can use eth_env_* even when CONFIG_NET isn't set, move
> these functions to environment code from net code.
>
> This fixes failures such as:
>
> board/ti/am335x/built-in.o: In function `board_late_init':
> board
On Sun, Apr 01, 2018 at 04:37:54PM +, Alex Kiernan wrote:
> CONFIG_VERSION_VARIABLE had already been mostly migrated to Kconfig,
> but two headers still referenced it. Also set defaults so that
> most of the defconfigs inherit the default rather than needing it
> to be set explicitly.
>
> Sig
On Sun, Apr 01, 2018 at 09:22:35AM +, Alex Kiernan wrote:
> If DHCP/PXE commands are disabled then the compilation fails due to
> bootargs attempting to use them:
>
> include/config_distro_bootcmd.h:319:2: error: expected ‘}’ before
> ‘BOOT_TARGET_DEVICES_references_PXE_without_CONFIG_CMD_
On Sun, Apr 01, 2018 at 04:37:53PM +, Alex Kiernan wrote:
> Convert CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG to Kconfig
>
> Signed-off-by: Alex Kiernan
> Reviewed-by: Lukasz Majewski
> Reviewed-by: Petr Vorel
> Reviewed-by: Petr Vorel
Applied to u-boot/master, thanks!
--
Tom
signature.as
On Sun, Apr 01, 2018 at 09:22:36AM +, Alex Kiernan wrote:
> In order to compile the USB Ethernet gadget support we require that NET
> is enabled, add that dependency here.
>
> Signed-off-by: Alex Kiernan
> Acked-by: Joe Hershberger
Applied to u-boot/master, thanks!
--
Tom
signature.asc
On Sun, Apr 01, 2018 at 09:22:34AM +, Alex Kiernan wrote:
> This converts CONFIG_DRIVER_TI_CPSW to Kconfig
>
> Signed-off-by: Alex Kiernan
> Acked-by: Joe Hershberger
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: PGP signature
_
Le 09/04/2018 à 16:21, Jean-Jacques Hiblot a écrit :
On 09/04/2018 16:03, Guillaume Gardet wrote:
Le 09/04/2018 à 15:58, Jean-Jacques Hiblot a écrit :
On 09/04/2018 14:02, Guillaume Gardet wrote:
Hi Jaehoon,
There are problems with SD card access on Samsung Chromebook (snow) with late
Hi Guillaume,
Thanks for your patch! Switching the upstream nitrogen6x configuration
to distro bootcmd has been in our todo list for some time since we also
use that in our own git repo.
On Fri, Apr 06, 2018 at 12:05:48PM +0200, Guillaume GARDET wrote:
> Boot tested with boot.scr script and EFI/G
Hi Tom,
please pull these changes to your tree.
Travis looks good.
https://travis-ci.org/michalsimek/u-boot/builds/364047688
And buildman output too.
Thanks,
Michal
The following changes since commit 5bc0543df3079add8152afa041b887d081d71839:
treewide: Convert CONFIG_HOSTNAME to a string op
On 09/04/2018 16:03, Guillaume Gardet wrote:
Le 09/04/2018 à 15:58, Jean-Jacques Hiblot a écrit :
On 09/04/2018 14:02, Guillaume Gardet wrote:
Hi Jaehoon,
There are problems with SD card access on Samsung Chromebook (snow)
with latest master (and also 2018.05-rc1 and 2018.03).
eMMC is
On 04/09/2018 04:25 PM, Tom Rini wrote:
On Mon, Apr 09, 2018 at 04:11:01PM +0300, Michalis Pappas wrote:
This patch adds smc and hvc commands, that allow issuing Secure Monitor
Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.
Add Kconfig items to allow each command can
Le 09/04/2018 à 15:58, Jean-Jacques Hiblot a écrit :
On 09/04/2018 14:02, Guillaume Gardet wrote:
Hi Jaehoon,
There are problems with SD card access on Samsung Chromebook (snow) with latest
master (and also 2018.05-rc1 and 2018.03).
eMMC is ok, but SD card access leads to 'unable to selec
On 09/04/2018 14:02, Guillaume Gardet wrote:
Hi Jaehoon,
There are problems with SD card access on Samsung Chromebook (snow)
with latest master (and also 2018.05-rc1 and 2018.03).
eMMC is ok, but SD card access leads to 'unable to select a mode'
problem. If I disable HS mode, I can access
Hi Jagan,
On Mon, 2018-04-09 at 16:52 +0530, Jagan Teki wrote:
> On Mon, Apr 9, 2018 at 4:27 PM, Eugeniy Paltsev
> wrote:
> > sst26wf flash series block protection implementation differs
> > from other SST series, so add specific implementation
> > flash_lock/flash_unlock/flash_is_locked function
On Mon, Apr 09, 2018 at 01:15:00PM +0100, Peter Robinson wrote:
> Now the A64/H5 SoCs support video output it's useful to enable usb keyboard
> support so console can be used via standard keyboard/video interface.
>
> Tested on Pine64.
Is it usefull on devices without video output(no HDMI, VGA)?
On 04/04/2018 22:40, Beniamino Galvani wrote:
> On Wed, Mar 28, 2018 at 11:54:36AM +0200, Neil Armstrong wrote:
>> Taking into account the Amlogic Family name starts with GX, including
>> the GXBB, GXL and GXM SoCs.
>>
>> Signed-off-by: Neil Armstrong
>
> Hi,
>
> looks good to me, but perhaps ca
On 08/04/2018 15:50, Simon Glass wrote:
> Hi,
>
> On 28 March 2018 at 05:54, Neil Armstrong wrote:
>> The Amlogic SoCs have a registers containing the die revision
>> and packaging type to determine the SoC family and package marketing
>> name like S905X for the GXL SoC Family.
>> This code is ta
On 04/04/2018 22:49, Beniamino Galvani wrote:
> On Wed, Mar 28, 2018 at 11:54:37AM +0200, Neil Armstrong wrote:
>> The Amlogic SoCs have a registers containing the die revision
>> and packaging type to determine the SoC family and package marketing
>> name like S905X for the GXL SoC Family.
>> This
This patch adds smc and hvc commands, that allow issuing Secure Monitor
Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.
Add Kconfig items to allow each command can be individually enabled.
Signed-off-by: Michalis Pappas
---
cmd/Kconfig | 14 ++
cmd/Makefile |
Hi,
I've been trying to bring up a dwc3 usb controller included in 32-bit MIPS chip.
Usb is the one port usb2.0 host module, compliant with xHCI Revision 1.0, UTMI+
Low Pin interface (ULPI) Revision 1.1 and AMBA AXI Protocol specification.
g_snpsid register reports 0x5533290a revision.
It's ve
Thanks for the feedback, I just sent a v2 addressing both issues
On 04/09/2018 04:26 AM, Fabio Estevam wrote:
On Fri, Apr 6, 2018 at 7:06 AM, Michalis Pappas wrote:
+config CMD_HVC
+ bool "Support the 'hvc' command"
+ depends on ARM64
+ default n
No need to pass 'default n
On Mon, Apr 09, 2018 at 04:11:01PM +0300, Michalis Pappas wrote:
> This patch adds smc and hvc commands, that allow issuing Secure Monitor
> Calls and Hypervisor Calls conforming to the ARM SMC Calling Convention.
>
> Add Kconfig items to allow each command can be individually enabled.
>
> Signed
Hi Fabio,
On Sat, 7 Apr 2018 18:06:27 -0300
Fabio Estevam feste...@gmail.com wrote:
...
> Do the same in the U-Boot source tree.
>
> Signed-off-by: Fabio Estevam
> ---
> drivers/video/anx9804.c | 0
> include/configs/blanche.h | 0
> 2 files changed, 0 insertions(+), 0 deletions(-)
> mode c
On Mon, Apr 9, 2018 at 1:53 PM, Maxime Ripard wrote:
> On Mon, Apr 09, 2018 at 01:15:00PM +0100, Peter Robinson wrote:
>> Now the A64/H5 SoCs support video output it's useful to enable usb keyboard
>> support so console can be used via standard keyboard/video interface.
>>
>> Tested on Pine64.
>>
Hi Tom,
Sorry the previous request failed travis checks. This one passes.
This is my current patch queue for efi. Please pull.
Alex
The following changes since commit 645b5afbb8215b3386cd6fc2dc3119bd68e4c760:
Prepare v2018.05-rc1 (2018-04-02 20:31:36 -0400)
are available in the git reposi
On Mon, Apr 09, 2018 at 10:01:59AM +0200, Christian Gmeiner wrote:
> Hi
>
> 2018-04-08 16:30 GMT+02:00 Tom Rini :
> > On Thu, Mar 29, 2018 at 09:49:30AM +0200, Christian Gmeiner wrote:
> >
> >> Make it possible to use gcc code coverage analysis.
> >>
> >> Signed-off-by: Christian Gmeiner
> >> ---
On Mon, Apr 09, 2018 at 01:15:00PM +0100, Peter Robinson wrote:
> Now the A64/H5 SoCs support video output it's useful to enable usb keyboard
> support so console can be used via standard keyboard/video interface.
>
> Tested on Pine64.
>
> Signed-off-by: Peter Robinson
Don't forget any maintain
Hi,
On Mon, 9 Apr 2018 13:42:28 +0200
Maxime Ripard wrote:
> Hi,
>
> On Mon, Apr 09, 2018 at 12:17:26PM +0200, Mylène Josserand wrote:
> > This commit adds a dependency on SATA for SATAPWR because
> > if we do not have SATA enabled, we will not have this pin
> > configured.
> >
> > By default,
Now the A64/H5 SoCs support video output it's useful to enable usb keyboard
support so console can be used via standard keyboard/video interface.
Tested on Pine64.
Signed-off-by: Peter Robinson
---
configs/a64-olinuxino_defconfig | 2 ++
configs/bananapi_m64_defconfig| 2 ++
confi
Hi Jaehoon,
There are problems with SD card access on Samsung Chromebook (snow) with latest
master (and also 2018.05-rc1 and 2018.03).
eMMC is ok, but SD card access leads to 'unable to select a mode' problem. If I
disable HS mode, I can access the SD card without problem:
Hi,
On Mon, Apr 09, 2018 at 12:17:26PM +0200, Mylène Josserand wrote:
> This commit adds a dependency on SATA for SATAPWR because
> if we do not have SATA enabled, we will not have this pin
> configured.
>
> By default, these two configs (SATAPWR and MACPWR) are equals
> to "". Because of that, t
On Mon, Apr 9, 2018 at 4:27 PM, Eugeniy Paltsev
wrote:
> sst26wf flash series block protection implementation differs
> from other SST series, so add specific implementation
> flash_lock/flash_unlock/flash_is_locked functions for sst26wf
> flash ICs.
>
> Signed-off-by: Eugeniy Paltsev
> ---
> Cha
sst26wf flash series block protection implementation differs
from other SST series, so add specific implementation
flash_lock/flash_unlock/flash_is_locked functions for sst26wf
flash ICs.
Signed-off-by: Eugeniy Paltsev
---
Changes v3->v4:
* Make sst26_process_bpr() and sst26_lock_ctl() functions
This commit adds support for the SST sst26wf016, sst26wf032
and sst26wf064 flash IC.
Signed-off-by: Eugeniy Paltsev
---
Changes v3->v4:
* None.
Changes v2->v3:
* None.
Changes v1->v2:
* None.
drivers/mtd/spi/spi_flash_ids.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/mtd
Add support for the SST sst26wf016, sst26wf032 and sst26wf064 flash IC:
sst26wf*** flash series block protection implementation differs from other
SST series, so we add implementation for sst26wf*** lock/unlock/is_locked
functions.
Add sst26wf016, sst26wf032 and sst26wf064 flash IC info to spi_fl
This commit adds a dependency on SATA for SATAPWR because
if we do not have SATA enabled, we will not have this pin
configured.
By default, these two configs (SATAPWR and MACPWR) are equals
to "". Because of that, they are always defined so we need to
check if the variables are not empty to perfor
From: Chris Packham
Make ddr3_calc_mem_cs_size() global scope and use it in
ddr3_new_tip_ecc_scrub to correctly initialize all of DDR memory.
Signed-off-by: Chris Packham
---
This has been reported upstream at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell/pull/6
Changes in v2: N
No in-tree code defines SUPPORT_STATIC_DUNIT_CONFIG or
STATIC_ALGO_SUPPORT. Remove ddr3_a38x_mc_static.h and use unifdef to
remove unused sections in the rest of the ddr/marvell/a38x code.
Signed-off-by: Chris Packham
---
Much of this code is moved/removed in the updated DDR code so this
commit h
This restores support for configuring the timing mode based on the
ddr_topology. This was originally implemented in commit 90bcc3d38d2b
("driver/ddr: Add support for setting timing in hws_topology_map") but
was removed as part of the upstream sync.
Signed-off-by: Chris Packham
---
Changes in v2:
Move sys_env_device_rev_get() from the ddr training code to
sys_env_lib.c (which currently resides with the serdes code). This
brings sys_env_device_rev_get() into line with sys_env_device_id_get()
and sys_env_model_get().
Signed-off-by: Chris Packham
---
Changes in v2:
- remove unused #include
PEX_CFG_DIRECT_ACCESS was defined in ddr3_hws_hw_training_def.h despite
only being used in the serdes code. Move this definition to ctrl_pex.h
where all the other PEX defines are. Also remove the duplicate
definition of PEX_DEVICE_AND_VENDOR_ID which is already defined in
ctrl_pex.h.
Signed-off-by
This series updates the ddr training code in u-boot with the latest
publicly available version from Marvell which can be found at
https://github.com/MarvellEmbeddedProcessors/mv-ddr-marvell.git
(mv_ddr-armada-17.10 branch).
I've tried to make the delta as small as possible without breaking
bisect-
sd_read_ssr returns 0 if it succeed.
Signed-off-by: Guillaume GARDET
Cc: Jaehoon Chung
---
drivers/mmc/mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index c930893300..92ea78b8af 100644
--- a/drivers/mmc/mmc.c
+++ b/drivers/mmc/m
2018-04-09 10:26 GMT+02:00 Bin Meng :
> Hi Christian,
>
> On Mon, Apr 9, 2018 at 3:52 PM, Christian Gmeiner
> wrote:
>> Hi Bin
>>
>> 2018-04-06 10:30 GMT+02:00 Christian Gmeiner :
>>> Hi Bin
>>>
>>> 2018-04-06 9:47 GMT+02:00 Bin Meng :
Hi Christian,
On Fri, Apr 6, 2018 at 2:55 PM, C
From: Patrick Delaunay
This driver binds and manages the following regulator of
SoC's PWR block :
- reg11
- reg18
- usb33
Signed-off-by: Patrick Delaunay
Signed-off-by: Patrice Chotard
---
arch/arm/mach-stm32mp/Makefile | 1 +
arch/arm/mach-stm32mp/include/mach/stm32.h |
This series :
_ adds stmpu157 SoC power regulator driver
_ populates DT with SoC power regulator entry
Patrice Chotard (1):
ARM: dts: stm32mp157: Add SoC pwr regulator entry
Patrick Delaunay (1):
stm32mp: regulator: add SoC pwr regulator support
arch/arm/dts/stm32mp157.dtsi
Add SoC power regulator entry for reg11, reg18 and usb33
regulator.
Signed-off-by: Patrice Chotard
---
arch/arm/dts/stm32mp157.dtsi | 33 +
1 file changed, 33 insertions(+)
diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi
index b84899a1ea
Hi Christian,
On Mon, Apr 9, 2018 at 3:52 PM, Christian Gmeiner
wrote:
> Hi Bin
>
> 2018-04-06 10:30 GMT+02:00 Christian Gmeiner :
>> Hi Bin
>>
>> 2018-04-06 9:47 GMT+02:00 Bin Meng :
>>> Hi Christian,
>>>
>>> On Fri, Apr 6, 2018 at 2:55 PM, Christian Gmeiner
>>> wrote:
Hi
I tried
On 30/03/2018 18:52, Joe Hershberger wrote:
> Some boards expect to find more than one phy while other boards are old
> and need to be limited to a specific phy address. Only limit the phy
> address for boards that opt in.
>
> Signed-off-by: Joe Hershberger
>
> ---
>
> configs/am335x_baltos_de
> On 9 Apr 2018, at 10:01, Neil Armstrong wrote:
>
> On 30/03/2018 18:52, Joe Hershberger wrote:
>> Some boards expect to find more than one phy while other boards are old
>> and need to be limited to a specific phy address. Only limit the phy
>> address for boards that opt in.
>>
>> Signed-off
Hi
2018-04-08 16:30 GMT+02:00 Tom Rini :
> On Thu, Mar 29, 2018 at 09:49:30AM +0200, Christian Gmeiner wrote:
>
>> Make it possible to use gcc code coverage analysis.
>>
>> Signed-off-by: Christian Gmeiner
>> ---
>> .gitignore | 4
>> Kconfig| 8
>> Makefile | 6 ++
>> 3
Kever,
> On 8 Apr 2018, at 03:45, Kever Yang wrote:
>
> Philipp,
>
>
> On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
>>
>>
>> On Tue, 27 Mar 2018, Kever Yang wrote:
>>
>>> We use common board/spl/tpl file for all rockchip SoCs,
>>> - all the SoC spec setting should move into SoC file like
Hi Bin
2018-04-06 10:30 GMT+02:00 Christian Gmeiner :
> Hi Bin
>
> 2018-04-06 9:47 GMT+02:00 Bin Meng :
>> Hi Christian,
>>
>> On Fri, Apr 6, 2018 at 2:55 PM, Christian Gmeiner
>> wrote:
>>> Hi
>>>
>>> I tried my luck on the u-boot irc channel but nobody cared so I am
>>> asking this here again.
Kever,
> On 9 Apr 2018, at 00:35, Tom Rini wrote:
>
> On Sun, Apr 08, 2018 at 09:45:22AM +0800, Kever Yang wrote:
>> Philipp,
>>
>>
>> On 04/02/2018 05:28 AM, Philipp Tomsich wrote:
>>>
>>>
>>> On Tue, 27 Mar 2018, Kever Yang wrote:
>>>
We use common board/spl/tpl file for all rockchip
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