[U-Boot] [PATCH] ARM: omap3: evm: Add kernel image loading from UBIFS and EXT4

This commit adds UBIFS_NAND to BOOT_TARGET_DEVICES. This will allow the kernel zImage to be loaded from '/boot/zImage' in UBIFS (ubi0:rootfs). Additionally update the *_MMC devices to also load kernel image from the MMC 0:2 EXT4 file system. DISTRO_DEFAULTS Setup = [primary]

[U-Boot] [PATCH 1/1] board_r: remove superfluous #ifdef CONFIG_PRAM

initr_mem() is already enclosed by #if defined(CONFIG_PRAM) #endif So there is no need to check CONFIG_PRAM again inside the function. Signed-off-by: Heinrich Schuchardt --- common/board_r.c | 2 -- 1 file changed, 2 deletions(-) diff --git a/common/board_r.c b/common/board_r.c

[U-Boot] [BUG] x86: incorrect dram definition in dram_init_banksize().

Function efi_add_known_memory uses the configured DRAM banks (gd->bd->bi_dram) to define the memory that an EFI application may use. For qemu-x86_defconfig this will result in the first 1 MB of physical memory being available. Here we find the BIOS, interrupt vectors and the VGA memory (0xA-0x

Re: [U-Boot] [PATCH V2] imx: mx7: psci: add system reset support

Hi Anson, On Fri, Jan 5, 2018 at 4:25 AM, Anson Huang wrote: > Thanks for the comments, the current reboot command works is just > because wdog driver is enabled and when system reboot, the reboot notification > callback in wdog driver will do reset. But if wdog is disabled in dtb, the > reboot

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

On 1/6/2018 1:29 PM, Marek Vasut wrote: > On 01/06/2018 07:46 PM, Jason Rush wrote: >> On 1/6/2018 9:42 AM, Marek Vasut wrote: >> There was a minor upstream change to one of the files since I submitted v4 >> of my >> cadence device-tree patchset, so I rebased and resent the patchset as a v5. 

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

On 01/06/2018 07:46 PM, Jason Rush wrote: > On 1/6/2018 9:42 AM, Marek Vasut wrote: >> On 01/06/2018 02:39 PM, Goldschmidt Simon wrote: >>> On Fri, 05/01/2018, Marek Vasut wrote: On 01/05/2018 08:31 PM, Goldschmidt Simon wrote: > On Fri, 05/01/2018 Marek Vasut wrote: >> On 01/05/2018 0

Re: [U-Boot] [PATCH 1/7] mmc: uniphier-sd: Use mmc_of_parse()

On 01/06/2018 08:29 PM, Marek Vasut wrote: > Drop the ad-hoc DT caps parsing in favor of common framework function. > > Signed-off-by: Marek Vasut > Cc: Jaehoon Chung > Cc: Masahiro Yamada Just for completeness, this all applies to u-boot/next , since the HS200 patches which are in next are ne

[U-Boot] [PATCH] ARM: rmobile: Enable HS200 mode on RCar Gen3

Enable the HS200 on RCar Gen3 platforms, since the SDHI core supports it. Signed-off-by: Marek Vasut Cc: Nobuhiro Iwamatsu --- configs/r8a7795_salvator-x_defconfig | 1 + configs/r8a7795_ulcb_defconfig | 1 + configs/r8a7796_salvator-x_defconfig | 1 + configs/r8a7796_ulcb_defconfig

[U-Boot] [PATCH 7/7] mmc: uniphier-sd: Always check controller version

Handle the controller version even if quirks are set. The controller in Renesas Gen3 SoCs does provide the version register, which indicates a controller v10 and the controller does support internal DMA and /1024 divider. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- dri

[U-Boot] [PATCH 6/7] mmc: uniphier-sd: Handle DMA completion flag differences

The DMA READ completion flag position differs on Socionext and Renesas SoCs. It is bit 20 on Socionext SoCs and using bit 17 is a hardware bug and forbidden. It is bit 17 on Renesas SoCs and bit 20 does not work on them. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- driv

[U-Boot] [PATCH 5/7] mmc: uniphier-sd: Add Renesas SDR104/HS200 tuning support

Add code for PHY tuning required for SDR104/HS200 support on Renesas RCar. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 290 ++ 1 file changed, 290 insertions(+) diff --git a/drivers/mmc/uniphier-s

[U-Boot] [PATCH 3/7] mmc: uniphier-sd: Add Renesas RCar quirks

Add a quirk to identify that the controller is Renesas RCar variant of the Matsushita SD IP and another quirk indicating it can support Renesas RCar HS200/HS400/SDR104 modes. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 13 + 1 fi

[U-Boot] [PATCH 4/7] mmc: uniphier-sd: Handle Renesas div-by-1

On the Renesas version of the IP, the /1 divider is realized by setting the clock register [7:0] to 0xff instead of setting bit 10 of the register. Check the quirk and handle accordingly. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 4 +++- 1

[U-Boot] [PATCH 2/7] mmc: uniphier-sd: Properly handle pin voltage configuration

Factor out the regulator handling into set_ios and add support for selecting pin configuration based on the voltage to support UHS modes. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 33 - 1 file changed, 24 in

[U-Boot] [PATCH 1/7] mmc: uniphier-sd: Use mmc_of_parse()

Drop the ad-hoc DT caps parsing in favor of common framework function. Signed-off-by: Marek Vasut Cc: Jaehoon Chung Cc: Masahiro Yamada --- drivers/mmc/uniphier-sd.c | 23 +++ 1 file changed, 7 insertions(+), 16 deletions(-) diff --git a/drivers/mmc/uniphier-sd.c b/drivers

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

On 1/6/2018 9:42 AM, Marek Vasut wrote: > On 01/06/2018 02:39 PM, Goldschmidt Simon wrote: >> On Fri, 05/01/2018, Marek Vasut wrote: >>> On 01/05/2018 08:31 PM, Goldschmidt Simon wrote: On Fri, 05/01/2018 Marek Vasut wrote: > On 01/05/2018 04:49 PM, Goldschmidt Simon wrote:

[U-Boot] [PATCH v5 4/5] dts: k2g: Clean-up indentation

Fix indentation of the QSPI node. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off-by: Jason Rush Cc: Marek Vasut --- Changes for v5: - Rebased Changes for v4: - Rebased Changes for v3: - Additional patch for

[U-Boot] [PATCH v5 5/5] dts: cadence_spi: Update documentation for DT bindings

Update documentation to reflect adopting the Linux DT bindings. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off-by: Jason Rush Cc: Marek Vasut --- Changes for v5: - Rebased Changes for v4: - Updated documentati

[U-Boot] [PATCH v5 3/5] config: cadence_spi: Remove defines read from DT

Cleanup unused #define values that are read from the DT. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off-by: Jason Rush Cc: Marek Vasut --- Changes for v5: - Rebased Changes for v4: - Rebased Changes for v3:

[U-Boot] [PATCH v5 2/5] dts: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings and clean-up duplicate and unused values. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off-by: Jason Rush Cc: Marek Vasut --- Changes for v5: - Rebased Changes for v4: - Rebased Chang

[U-Boot] [PATCH v5 1/5] spi: cadence_spi: Sync DT bindings with Linux

Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off

[U-Boot] [PATCH v5 0/5] spi: cadence_spi: Adopt Linux DT bindings

Adopt the Linux DT bindings. This also fixes an issue with the indaddrtrig register on the Cadence QSPI device being programmed with the wrong value for the socfpga arch. Tested on TI K2G platform: Tested-by: Vignesh R Tested on a socfpga-cyclonev board: Tested-by: Simon Goldschmidt Signed-off

Re: [U-Boot] [PATCH V2 2/3] imx: mx7: psci: add system reset support

Hi Anson, On Sat, Jan 6, 2018 at 12:17 AM, Anson Huang wrote: > } > + > +__secure void imx_system_reset(void) > +{ > + writew(1 << 2, WDOG1_BASE_ADDR); It would be safer to turn on the wdog1 clock prior to writing to this register. Better not assume that is already turned on. Also this

Re: [U-Boot] [PATCH V2 1/3] mx7_common: use psci 1.0 instead of 0.1

Hi Anson, On Sat, Jan 6, 2018 at 12:17 AM, Anson Huang wrote: > Use PSCI 1.0 instead of 0.1 to support more power > management feature like system reset, power off etc.. > > Signed-off-by: Anson Huang Thanks for this patch series. Do you also plan to add suspend/resume support for i.MX7 via PS

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

On 01/06/2018 02:39 PM, Goldschmidt Simon wrote: > On Fri, 05/01/2018, Marek Vasut wrote: >> On 01/05/2018 08:31 PM, Goldschmidt Simon wrote: >>> On Fri, 05/01/2018 Marek Vasut wrote: On 01/05/2018 04:49 PM, Goldschmidt Simon wrote: >>> >>> >>> >>> OK, so I need these patches to get qspi

[U-Boot] [PATCH 2/2] libfdt: fix

I do not remember why, but this is copy-paste mistake. The file name is libfdt.h, but its content is that of libfdt_env.h Sync it with upstream Linux. Signed-off-by: Masahiro Yamada --- include/linux/libfdt.h | 22 +++--- 1 file changed, 7 insertions(+), 15 deletions(-) diff

[U-Boot] [PATCH 1/2] libfdt: migrate fdt_rw.c to a wrapper of scripts/dtc/libfdt/fdt_rw.c

The only difference between scripts/dtc/libfdt/fdt_rw.c and lib/libfdt/fdt_rw.c is fdt_remove_unused_strings(). It is only used fdtgrep, so we do not need to compile it for U-Boot image. Move it to tools/libfdt/fdw_rw.c, then lib/libfdt/fdt_rw.c can be a wrapper. Signed-off-by: Masahiro Yamada

[U-Boot] [PATCH V2 1/3] mx7_common: use psci 1.0 instead of 0.1

Use PSCI 1.0 instead of 0.1 to support more power management feature like system reset, power off etc.. Signed-off-by: Anson Huang --- no changes since v1. include/configs/mx7_common.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/configs/mx7_common.h b/include/configs/mx7_common

Re: [U-Boot] [PATCH 3/3] imx: mx7: psci: add system power off support

Best Regards! Anson Huang > -Original Message- > From: Troy Kisky [mailto:troy.ki...@boundarydevices.com] > Sent: 2018-01-06 2:49 AM > To: Anson Huang ; sba...@denx.de; Fabio Estevam > ; albert.u.b...@aribaud.net; > christian.gmei...@gmail.com; Peng Fan ; u- > b...@lists.denx.de > Subje

[U-Boot] [PATCH V2 3/3] imx: mx7: psci: add system power off support

Add i.MX7 PSCI system power off support, linux kernel can use "poweroff" command to power off system via SNVS, PMIC power will be disabled. Signed-off-by: Anson Huang --- changes since v1: use "bl" instead of "b" as we need the call to return back. arch/arm/mach-imx/mx7/psci-mx7.c | 18 +

[U-Boot] [PATCH V2 2/3] imx: mx7: psci: add system reset support

Add i.MX7 PSCI system reset support, linux kernel can use "reboot" command to reset system even wdog driver is disabled in kernel. Signed-off-by: Anson Huang --- changes since v1: use "bl" instead of "b" as we need the call to return back. arch/arm/mach-imx/mx7/psci-mx7.c | 5 + arch

[U-Boot] [PATCH 0/3] ARM: uniphier: updates for v2017.03 MW

Masahiro Yamada (3): ARM: uniphier: do not use RAM that exceeds 32 bit address range ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCs ARM: uniphier: hide memory top by platform hook instead of CONFIG arch/arm/mach-uniphier/dram_init.c | 24 configs/uniphi

[U-Boot] [PATCH 1/3] ARM: uniphier: do not use RAM that exceeds 32 bit address range

LD20 / PXs3 boards are equipped with a large amount of memory beyond the 32 bit address range. U-Boot relocates itself to the end of the available RAM. This is a problem for DMA engines that only support 32 bit physical address, like the SDMA of SDHCI controllers. In fact, U-Boot does not need t

[U-Boot] [PATCH 3/3] ARM: uniphier: hide memory top by platform hook instead of CONFIG

I do not see a good reason to do this by a CONFIG option that affects all SoCs. The ram_size can be adjusted by dram_init() at run-time. Signed-off-by: Masahiro Yamada --- arch/arm/mach-uniphier/dram_init.c | 7 +++ include/configs/uniphier.h | 2 -- 2 files changed, 7 insertions(+

[U-Boot] [PATCH 2/3] ARM: uniphier: enable CONFIG_MMC_SDHCI_SDMA for ARMv8 SoCs

I did not enable SDMA when I added sdhci-cadence support because LD20 boards are equipped with a large amount memory beyond 32 bit address range, but SDMA does not support the 64bit address. U-Boot relocates itself to the end of effectively available RAM. This would make the MMC enumeration fail

Re: [U-Boot] QSPI "sf probe ...", "sf read ..." on Altera SoC FPGA

On Fri, 05/01/2018, Marek Vasut wrote: > On 01/05/2018 08:31 PM, Goldschmidt Simon wrote: >> On Fri, 05/01/2018 Marek Vasut wrote: >>> On 01/05/2018 04:49 PM, Goldschmidt Simon wrote: >> >> >> >> OK, so I need these patches to get qspi work on socfpga: >> >> - Series "spi: cadence_spi: