On 05/25/2017 10:51 PM, Jaehoon Chung wrote:
> On 05/16/2017 07:16 AM, Philipp Tomsich wrote:
>> Adding documentation on the new config properties:
>>'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
>>'u-boot,mmc-env-offset-redundant'
>>- overrid
On 05/25/2017 10:51 PM, Jaehoon Chung wrote:
> Hi Philipp,
>
> On 05/16/2017 07:16 AM, Philipp Tomsich wrote:
>> This introduces the ability to override the environment offets from the
>> device tree by setting the following nodes in '/config':
>> 'u-boot,mmc-env-offset' - overrides CONFIG_EN
On 05/25/2017 11:14 PM, Phil Edworthy wrote:
> Hi Jaehoon Chung,
>
> On 25 May 2017 15:10 Jaehoon Chung wrote:
>> On 05/25/2017 11:02 PM, Phil Edworthy wrote:
>>> On 25 May 2017 14:50 Jaehoon Chung wrote:
On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> The code currently defaults to the sl
Hi Tom,
On 25 May 2017 at 11:42, Tom Rini wrote:
> On Thu, May 25, 2017 at 11:27:10AM -0600, Simon Glass wrote:
>> Hi Tom,
>>
>> On 25 May 2017 at 05:19, Tom Rini wrote:
>> >
>> > On Wed, May 24, 2017 at 06:15:25PM -0600, Simon Glass wrote:
>> >
>> > > Hi Tom,
>> > >
>> > > This incorporates the
On Kha, 2017-05-25 at 11:18 +0200, Marek Vasut wrote:
> On 05/25/2017 10:53 AM, Chee, Tien Fong wrote:
> >
> > On Rab, 2017-05-24 at 09:56 -0500, Dinh Nguyen wrote:
> > >
> > >
> > > On 05/23/2017 09:24 PM, tien.fong.c...@intel.com wrote:
> > > >
> > > >
> > > > From: Tien Fong Chee
> > > >
On 05/17/2017 11:22 PM, Simon Glass wrote:
> This is no-longer used in U-Boot. Drop it.
>
> Signed-off-by: Simon Glass
Reviewed-by: Jaehoon Chung
> ---
>
> drivers/mmc/Makefile | 1 -
> drivers/mmc/s3c_sdi.c| 323
> ---
> scripts/con
On 05/25/2017 10:52 PM, Keerthy wrote:
>
>
> On Thursday 25 May 2017 07:18 PM, Jaehoon Chung wrote:
>> On 05/24/2017 01:49 PM, Keerthy wrote:
>>> Currently while setting the vsel value for dcdc1 and dcdc2
>>> the driver is wrongly masking the entire 8 bits in the process
>>> clearing PFM (bit7) f
On 05/25/2017 11:34 PM, Tom Rini wrote:
> On Thu, May 25, 2017 at 10:48:55PM +0900, Jaehoon Chung wrote:
>> On 05/24/2017 01:49 PM, Keerthy wrote:
>>> Currently while setting the vsel value for dcdc1 and dcdc2
>>> the driver is wrongly masking the entire 8 bits in the process
>>> clearing PFM (bit7
On 05/25/2017 11:40 PM, Jean-Jacques Hiblot wrote:
> Hi,
>
>
> On 25/05/2017 14:25, Jaehoon Chung wrote:
>> On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
>>> The MMC startup process currently handles 4 modes. To make it easier to
>>> add support for more modes, let's make the process more ge
Hi Phil,
> -Original Message-
> From: Phil Edworthy [mailto:phil.edwor...@renesas.com]
> Sent: Thursday, May 25, 2017 6:58 AM
> To: Vikas MANOCHA ; Albert Aribaud
>
> Cc: Tom Rini ; Kamil Lulko ;
> u-boot@lists.denx.de
> Subject: RE: [PATCH] armv7m: Fix larger builds
>
> Hi Vikas,
>
>
On 25/05/17 20:35, Jagan Teki wrote:
> From: Jagan Teki
>
> Orangepi Zero Plus 2 is an open-source single-board computer
> using the Allwinner h5 SOC.
>
> H5 Orangepi Zero Plus 2 has
> - Quad-core Cortex-A53
> - 512MB DDR3
> - Debug TTL UART
> - HDMI
> - Wifi + BT
> - OTG+power supply
What abou
On 25/05/17 20:35, Jagan Teki wrote:
> From: Jagan Teki
>
> The Allwinner H5 SoC is pin-compatible to the H3 SoC,
> but uses Cortex-A53 cores instead.
>
> So move the shared cpu based and peripherals nodes into
> sun50i-h5.dtsi so, that it can shared among the sun50i-h5
> board dts files.
That
On 25/05/17 20:35, Jagan Teki wrote:
> From: Jagan Teki
>
> Orangepi Win/WinPlus is an open-source single-board computer
> using the Allwinner A64 SOC.
>
> A64 Orangepi Win/WinPlus has
> - A64 Quad-core Cortex-A53 64bit
> - 1GB(Win)/2GB(Win Plus) DDR3 SDRAM
> - Debug TTL UART
> - Four USB 2.0
>
On Thu, May 25, 2017 at 03:21:04PM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 25 May 2017 at 15:12, Tom Rini wrote:
> > On Thu, May 25, 2017 at 10:58:20PM +0200, Jorge Ramirez wrote:
> >> On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
> >> >On 05/25/2017 10:31 PM, Tom Rini wrote:
> >> >>On Thu, May
On Thu, May 25, 2017 at 11:16:42PM +0200, Jorge Ramirez wrote:
> On 05/25/2017 11:12 PM, Tom Rini wrote:
> >On Thu, May 25, 2017 at 10:58:20PM +0200, Jorge Ramirez wrote:
> >>On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
> >>>On 05/25/2017 10:31 PM, Tom Rini wrote:
> On Thu, May 25, 2017 at 08:3
Hi Tom,
On 25 May 2017 at 15:12, Tom Rini wrote:
> On Thu, May 25, 2017 at 10:58:20PM +0200, Jorge Ramirez wrote:
>> On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
>> >On 05/25/2017 10:31 PM, Tom Rini wrote:
>> >>On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
>> >>>On 05/18/2017 12:
On 05/25/2017 11:12 PM, Tom Rini wrote:
On Thu, May 25, 2017 at 10:58:20PM +0200, Jorge Ramirez wrote:
On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
On 05/25/2017 10:31 PM, Tom Rini wrote:
On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
On 05/18/2017 12:06 AM, Tom Rini wrote:
h
On Thu, May 25, 2017 at 10:58:20PM +0200, Jorge Ramirez wrote:
> On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
> >On 05/25/2017 10:31 PM, Tom Rini wrote:
> >>On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
> >>>On 05/18/2017 12:06 AM, Tom Rini wrote:
> >>>having platform data.
> >
On 05/25/2017 10:55 PM, Jorge Ramirez wrote:
On 05/25/2017 10:31 PM, Tom Rini wrote:
On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
On 05/18/2017 12:06 AM, Tom Rini wrote:
having platform data.
No, I think we're going for overkill here by not doing
serial_pl01x.c as
platform
On 05/25/2017 10:31 PM, Tom Rini wrote:
On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
On 05/18/2017 12:06 AM, Tom Rini wrote:
having platform data.
No, I think we're going for overkill here by not doing serial_pl01x.c as
platform data. ns16550 does platform data for this alre
On Thu, May 25, 2017 at 08:38:47PM +0200, Jorge Ramirez wrote:
> On 05/18/2017 12:06 AM, Tom Rini wrote:
> having platform data.
> >>>No, I think we're going for overkill here by not doing serial_pl01x.c as
> >>>platform data. ns16550 does platform data for this already. This
> >>>sounds like
From: Jagan Teki
Orangepi Prime is an open-source single-board computer
using the Allwinner h5 SOC.
H5 Orangepi Prime has
- Quad-core Cortex-A53
- 2GB DDR3
- Debug TTL UART
- 1000M/100M Ethernet RJ45
- Three USB 2.0
- HDMI
- Audio and MIC
- Wifi + BT
- IR receiver
- HDMI
- Wifi + BT
http://www.
From: Jagan Teki
Orangepi Zero Plus 2 is an open-source single-board computer
using the Allwinner h5 SOC.
H5 Orangepi Zero Plus 2 has
- Quad-core Cortex-A53
- 512MB DDR3
- Debug TTL UART
- HDMI
- Wifi + BT
- OTG+power supply
http://www.orangepi.org/OrangePiZeroPlus2/
Boot from MMC:
---
From: Jagan Teki
Instead of defining numerical value on GPIO flag
better to use existing binding macro.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sun50i-h5-orangepi-pc2.dts | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/sun50i-h5-orangepi-pc2.dts
b/arch/a
From: Jagan Teki
The Allwinner H5 SoC is pin-compatible to the H3 SoC,
but uses Cortex-A53 cores instead.
So move the shared cpu based and peripherals nodes into
sun50i-h5.dtsi so, that it can shared among the sun50i-h5
board dts files.
Signed-off-by: Jagan Teki
---
arch/arm/dts/sun50i-h5-ora
From: Jagan Teki
Orangepi Win/WinPlus is an open-source single-board computer
using the Allwinner A64 SOC.
A64 Orangepi Win/WinPlus has
- A64 Quad-core Cortex-A53 64bit
- 1GB(Win)/2GB(Win Plus) DDR3 SDRAM
- Debug TTL UART
- Four USB 2.0
- HDMI
- LCD
- Audio and MIC
- Wifi + BT
- IR receiver
- 5V
From: Jagan Teki
This series add Allwinner Cortex A-53 boards from OrangePI.
- Orangepi Win/WinPlus
- Orangepi Prime
- Orangepi Zero Plus 2
thanks!
Jagan.
Jagan Teki (5):
sun50i: a64: Add initial Orangepi Win/WinPlus support
arm64: dts: sun50i: Add sun50i-h5.dtsi
arm64: dts: sun50i: h5:
On 05/18/2017 12:06 AM, Tom Rini wrote:
having platform data.
No, I think we're going for overkill here by not doing serial_pl01x.c as
platform data. ns16550 does platform data for this already. This
sounds like the lowest overhead way to get the clock populated and not
have some DT data that'
On Thu, May 25, 2017 at 07:23:58PM +0300, Pantelis Antoniou wrote:
> The dtb blob section must always be present in the resulting image.
> Either if OF_EMBEDED is used or if unit tests include dtb blobs.
>
> Signed-off-by: Pantelis Antoniou
Reviewed-by: Tom Rini
--
Tom
signature.asc
Descri
On Thu, May 25, 2017 at 07:24:06PM +0300, Pantelis Antoniou wrote:
> Unit tests require mallinfo which in turn requires DEBUG on
> dlmalloc to be enabled.
>
> The dependancy on CONFIG_SANDBOX is wrong.
>
> Signed-off-by: Pantelis Antoniou
Reviewed-by: Tom Rini
--
Tom
signature.asc
Descrip
On 05/17/2017 07:01 AM, yinbo.zhu wrote:
> From: Rajat Srivastava
>
> Adds helper functions to enable snooping and outstanding burst beat
> settings.
>
> Signed-off-by: Rajat Srivastava
> Signed-off-by: Rajesh Bhagat
> ---
> drivers/usb/dwc3/core.c | 45 ++
On Thu, May 25, 2017 at 11:27:10AM -0600, Simon Glass wrote:
> Hi Tom,
>
> On 25 May 2017 at 05:19, Tom Rini wrote:
> >
> > On Wed, May 24, 2017 at 06:15:25PM -0600, Simon Glass wrote:
> >
> > > Hi Tom,
> > >
> > > This incorporates the v2 patch for 'fdt: Build the new python libfdt
> > > module'
Hi Tom,
On 25 May 2017 at 05:19, Tom Rini wrote:
>
> On Wed, May 24, 2017 at 06:15:25PM -0600, Simon Glass wrote:
>
> > Hi Tom,
> >
> > This incorporates the v2 patch for 'fdt: Build the new python libfdt
> > module' which should fix the problem with the original pull request.
> >
> >
> > The fol
On Wed, May 10, 2017 at 10:25 AM, wrote:
> From: Yuiko Oshino
>>-Original Message-
>>From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
>>Sent: Friday, May 5, 2017 4:59 PM
>>To: Yuiko Oshino - C18177
>>Cc: u-boot; Marek Vasut
>>Subject: Re: [U-Boot] [PATCH] Add support for Microchi
The dtb blob section must always be present in the resulting image.
Either if OF_EMBEDED is used or if unit tests include dtb blobs.
Signed-off-by: Pantelis Antoniou
---
arch/arm/config.mk | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/config.mk b/arch/arm/con
Unit tests require mallinfo which in turn requires DEBUG on
dlmalloc to be enabled.
The dependancy on CONFIG_SANDBOX is wrong.
Signed-off-by: Pantelis Antoniou
---
common/dlmalloc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/dlmalloc.c b/common/dlmalloc.c
index a
Am 08.05.2017 um 18:36 schrieb Jorge Ramirez-Ortiz:
> This port adds support for:
> 1) Serial
> 2) eMMC
> 3) USB
>
> It has been tested with ARM TRUSTED FIRMWARE running u-boot as the
> BL33 executable [see board's README]
>
> eMMC has been tested for reading and booting t
On 05/02/2017 05:16 AM, Udit Agarwal wrote:
> This patch adjusts memory map for secure boot headers on LS2080AQDS
> and LS2080ARDB platforms.
>
> Secure boot headers are placed on NOR flash at offset 0x0060.
>
> Signed-off-by: Udit Agarwal
> ---
> https://emea01.safelinks.protection.outlook.co
On 05/15/2017 08:01 PM, Alison Wang wrote:
> This patch is to adjust the memory mapping for FLash/SD card on
> LS1043AQDS and LS1043ARDB, such as PPA firmware load address, FMAN
> firmware load address, QE firmware load address, U-Boot start address on
> serial flash and environment address.
>
> Si
On 05/15/2017 08:01 PM, Alison Wang wrote:
> This patch is to adjust the memory mapping for FLash/SD card on
> LS1046AQDS and LS1046ARDB, such as FMAN firmware load address, U-Boot
> start address on serial flash and environment address.
>
> Signed-off-by: Alison Wang
> ---
> Changes:
> - Update t
On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> The QorIQ LS2081A SoC has eight 64-bit ARM v8 Cortex A-72 CPUs and
> is built on layerscape architecture.
>
> It is 40-pin derivative of LS2084A (non-AIOP personality of LS2088A).
> So feature-wise it is same as LS2084A.
>
> LS2081A has one more simila
On 04/28/2017 12:14 AM, Santan Kumar wrote:
> This patch adjusts memory map for images on LS2080ARDB,
> LS2080AQDS as per below memory map for NOR flash:
> Image Flash Offset
> RCW+PBI 0x
> Boot firmware (U-Boot)0x001
On 04/27/2017 10:11 PM, Priyanka Jain wrote:
> QSPI-boot is verified on LS2088ARDB RevF board
> with LS2088A SoC.
> LS2088ARDB RevF Board has limitation that QIXIS
> can not be access, so QIXIS flag is kept disabled
>
> Signed-off-by: Priyanka Jain
> Signed-off-by: Suresh Gupta
> ---
> Changes fo
On 04/27/2017 02:38 AM, Priyanka Jain wrote:
> LS2081ARDB board is similar to LS2080ARDB board
> with few differences like
> It hosts LS2081A SoC
> Default boot source is QSPI-boot
> It does not have IFC interface
> RTC and QSPI flash device are different
> It provides QIXIS access via I2C
>
>
On 05/15/2017 08:01 PM, Alison Wang wrote:
> This patch is to adjust the memory mapping for FLash/SD card on LS1021AQDS
> and LS1021ATWR, such as U-Boot start address on serial Flash, QE firmware
> load address and environment address.
>
> Signed-off-by: Alison Wang
> ---
> Changes:
> - None
>
>
On 04/27/2017 10:11 PM, Priyanka Jain wrote:
> Update QIXIS related code to be executed
> only if CONFIG_FSL_QIXIS flag is enabled
>
> As per board documentation, default sysclk is 100MHz.
> In case QIXIS code is not enabled,
> update default sysclk value to 100MHz
>
> Signed-off-by: Priyanka Jain
On 04/26/2017 09:44 PM, Yogesh Gaur wrote:
> Earlier when MC is loaded but DPL is not deployed results in FDT fix-up
> code execution hang.
> For this case now print message on console and returns success instead of
> return -ENODEV.
> This update allows to continue fdt fixup execution.
>
> Signed-
On 05/23/2017 10:52 PM, Suresh Gupta wrote:
>
>
>> -Original Message-
>> From: york sun
>> Sent: Tuesday, May 23, 2017 9:50 PM
>> To: Suresh Gupta ; u-boot@lists.denx.de
>> Cc: ja...@openedev.com
>> Subject: Re: [PATCH] LS1012A: change the size of flash
>>
>> On 04/25/2017 02:20 AM, Sures
On 04/25/2017 08:40 AM, York Sun wrote:
> This allows using PCIe NIC without enabling DPAA FMan.
>
> Signed-off-by: York Sun
> CC: Mingkai Hu
> ---
> board/freescale/ls1043ardb/Makefile | 2 +-
> include/configs/ls1043ardb.h| 13 -
> 2 files changed, 9 insertions(+), 6 delet
On 04/24/2017 09:42 PM, Priyanka Jain wrote:
> LS2080ARDB/LS2088ARDB RevF board has smart voltage translator
> which needs to be programmed to enable high speed SD interface
> by setting GPIO4_10 output to zero
>
> Signed-off-by: Priyanka Jain
> Signed-off-by: Santan Kumar
> ---
> Changes for v2:
On 04/25/2017 08:40 AM, York Sun wrote:
> This allows using PCIe NIC without enabling DPAA FMan.
>
> Signed-off-by: York Sun
> CC: Mingkai Hu
> ---
> board/freescale/ls1046ardb/Makefile | 2 +-
> include/configs/ls1046ardb.h| 15 +--
> 2 files changed, 10 insertions(+), 7 de
On 04/25/2017 02:20 AM, Suresh Gupta wrote:
> ls1012ardb, ls1046ardb, ls2080ardb has S25FS512S
> flash which do not support Bank Address Register commands
>
> Signed-off-by: Suresh Gupta
> ---
> include/configs/ls1012a_common.h | 1 -
> include/configs/ls1046ardb.h | 1 -
> include/configs/ls
On 04/14/2017 02:03 AM, Zhiqiang Hou wrote:
> From: Hou Zhiqiang
>
> Signed-off-by: Hou Zhiqiang
> ---
> include/configs/ls1046a_common.h | 10 ++
> 1 file changed, 10 insertions(+)
>
Applied to fsl-qoriq master, awaiting upstream. Thanks.
York
Tom,
The following changes since commit 22f3368e71321db1e0e15dfbf54b052367890ec7:
Merge branch 'master' of git://git.denx.de/u-boot-mips (2017-05-13
16:45:35 -0400)
are available in the git repository at:
git://git.denx.de/u-boot-fsl-qoriq.git
for you to fetch changes up to 7676074ac756
On 25/05/2017 14:37, Jaehoon Chung wrote:
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
Tuning is a mandatory step in the initialization of SDR104 and HS200 modes.
This callback execute the tuning process.
Signed-off-by: Jean-Jacques Hiblot
---
drivers/mmc/mmc-uclass.c | 14 ++
On 25/05/2017 14:35, Jaehoon Chung wrote:
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
mmc/sd specification requires vdd to be disabled for 1 ms
and then enabled again during power cycle. Add a
function in mmc core to perform power cycle and set
the io signal to it's initial state.
Sign
On 25/05/2017 09:41, Jaehoon Chung wrote:
Hi,
On 05/24/2017 12:24 AM, Jean-Jacques Hiblot wrote:
Hi,
On 18/05/2017 06:27, Jaehoon Chung wrote:
Hi,
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
This series brings support for HS200 and UHS modes to the mmc core.
It has been tested wit
On Thu, May 25, 2017 at 03:37:34PM +0530, Keerthy wrote:
> Update vcores for am571-idk board.
>
> Reported-by: Steve Kipisz
> Signed-off-by: Keerthy
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
signature.asc
Description: Digital signature
___
Hi,
On 25/05/2017 14:25, Jaehoon Chung wrote:
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
The MMC startup process currently handles 4 modes. To make it easier to
add support for more modes, let's make the process more generic and use a
list of the modes to try.
The major functional chan
On Thu, May 25, 2017 at 10:48:55PM +0900, Jaehoon Chung wrote:
> On 05/24/2017 01:49 PM, Keerthy wrote:
> > Currently while setting the vsel value for dcdc1 and dcdc2
> > the driver is wrongly masking the entire 8 bits in the process
> > clearing PFM (bit7) field as well. Hence describe an appropri
Hi Jaehoon Chung,
On 25 May 2017 15:10 Jaehoon Chung wrote:
> On 05/25/2017 11:02 PM, Phil Edworthy wrote:
> > On 25 May 2017 14:50 Jaehoon Chung wrote:
> >> On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> >>> The code currently defaults to the slowest clock speed that can be
> >>> achieved, which
On 05/25/2017 11:02 PM, Phil Edworthy wrote:
> Hi Jaehoon Chung,
>
> On 25 May 2017 14:50 Jaehoon Chung wrote:
>> Hi,
>>
>> On 05/24/2017 10:54 PM, Phil Edworthy wrote:
>>> The code currently defaults to the slowest clock speed that can be
>>> achieved, which can be significantly lower than the SD
Hi,
On 05/24/2017 10:47 AM, Andes wrote:
> From: rick
>
> Support Andestech ftsdc010 SD/MMC device tree flow
> on AG101P/AE3XX platforms.
> Verification : boot linux kernel from sd card
Split the patch...
>
> NDS32 # mmc rescan
> NDS32 # fatls mmc 0:1
> 13938796 boomimage-310y-ag101p.bin
>
Hi Jaehoon Chung,
On 25 May 2017 14:50 Jaehoon Chung wrote:
> Hi,
>
> On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> > The code currently defaults to the slowest clock speed that can be
> > achieved, which can be significantly lower than the SD spec.
>
> Is there any problem..As i know, it shoul
On 05/25/2017 01:14 AM, Masahiro Yamada wrote:
> 2017-05-19 21:24 GMT+09:00 Masahiro Yamada :
>> The MMC framework in U-Boot does not support a systematic API for
>> timing switch like mmc_set_timing() in Linux.
>>
>> U-Boot just provides a hook to change the clock frequency via
>> mmc_set_clock().
Hi Vikas,
On 25 May 2017 10:16 Phil Edworthy wrote:
> > On 24 May 2017 18:32 Vikas MANOCHA wrote:
> > Hi Phil,
> >
> > > On Wednesday, May 24, 2017 7:34 AM Phil Edworthy wrote:
> > > The branch instruction only has an 11-bit relative target address, which
> > > is
> > sometimes not enough.
> > >
On 04/14/2017 05:10 PM, Heiner Kallweit wrote:
> Number of blocks is a 9 bit field where 0 stands for a unlimited
> number of blocks. Therefore the max number of blocks which can
> be set is 511.
>
> Signed-off-by: Heiner Kallweit
Applied to u-boot-mmc. Thanks! Sorry for late.
Best Regards,
Jae
On Thursday 25 May 2017 07:18 PM, Jaehoon Chung wrote:
> On 05/24/2017 01:49 PM, Keerthy wrote:
>> Currently while setting the vsel value for dcdc1 and dcdc2
>> the driver is wrongly masking the entire 8 bits in the process
>> clearing PFM (bit7) field as well. Hence describe an appropriate
>> ma
On 05/16/2017 07:16 AM, Philipp Tomsich wrote:
> Adding documentation on the new config properties:
>'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
>'u-boot,mmc-env-offset-redundant'
>- overrides CONFIG_ENV_OFFSET_REDUND
>
> Signed-off-by: Phi
Hi Philipp,
On 05/16/2017 07:16 AM, Philipp Tomsich wrote:
> This introduces the ability to override the environment offets from the
> device tree by setting the following nodes in '/config':
> 'u-boot,mmc-env-offset' - overrides CONFIG_ENV_OFFSET
> 'u-boot,mmc-env-offset-redundant'
>
Hi,
On 05/24/2017 10:54 PM, Phil Edworthy wrote:
> The code currently defaults to the slowest clock speed that can be
> achieved, which can be significantly lower than the SD spec.
Is there any problem..As i know, it should be changed from 1 to min_clk.
>
> Signed-off-by: Phil Edworthy
> ---
>
On 05/24/2017 01:49 PM, Keerthy wrote:
> Currently while setting the vsel value for dcdc1 and dcdc2
> the driver is wrongly masking the entire 8 bits in the process
> clearing PFM (bit7) field as well. Hence describe an appropriate
> mask for vsel field and modify only those bits in the vsel
> mask
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> From: Kouei Abe
>
> R-Car Gen3 series have four SD card interfaces (SDHI0 to SDHI3),
> two of which can also be used as MMC interfaces (SDHI2 and SDHI3).
> This adds High-speed mode SD clock frequency between 25MHz and 50MHz,
> 8bit/4bit bus width, hig
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> From: Kouei Abe
>
> Renesas SDHI SD/MMC driver did not support MMC version 5.0 devices.
> This adds MMC version 5.0 device support.
>
> Signed-off-by: Kouei Abe
> Signed-off-by: Hiroyuki Yokoyama
> Signed-off-by: Marek Vasut
> Cc: Hiroyuki Yokoyama
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> From: Kouei Abe
>
> Renesas SDHI SD/MMC driver has 16-bit width bus access to SD_BUF.
> This adds 64-bit width bus access to SD_BUF.
>
> Signed-off-by: Kouei Abe
> Cc: Hiroyuki Yokoyama
> Cc: Nobuhiro Iwamatsu
> Cc: Jaehoon Chung
Reviewed-by: Jae
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> From: Kouei Abe
>
> When setting interrupt mask after command starting, an unintended
> interrupt status sometimes occurs.
>
> Signed-off-by: Kouei Abe
> Signed-off-by: Hiroyuki Yokoyama
> Cc: Hiroyuki Yokoyama
> Cc: Nobuhiro Iwamatsu
> Cc: Jaehoo
On 05/13/2017 10:51 PM, Marek Vasut wrote:
> The Kconfig entry depends on RMOBILE, but this was renamed
> to ARCH_RMOBILE in commit 1cc95f6e1b38 (ARM: Rmobile: Rename
> CONFIG_RMOBILE to CONFIG_ARCH_RMOBILE) . Fix this omission.
>
> Signed-off-by: Marek Vasut
> Cc: Hiroyuki Yokoyama
> Cc: Nobuhi
On 05/11/2017 11:35 AM, Peng Fan wrote:
> Fix unsigned compared against 0.
Reviewed-by: Jaehoon Chung
>
> Signed-off-by: Peng Fan
> Cc: Jaehoon Chung
> ---
> drivers/power/regulator/pfuze100.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
> diff --git a/drivers/power/regul
On 05/11/2017 11:35 AM, Peng Fan wrote:
> Add SPDX license
>
> Signed-off-by: Peng Fan
> Cc: Jaehoon Chung
Reviewed-by: Jaehoon Chung
> ---
> drivers/power/regulator/pfuze100.c | 8
> 1 file changed, 8 insertions(+)
>
> diff --git a/drivers/power/regulator/pfuze100.c
> b/drivers/p
On 05/11/2017 11:28 AM, Peng Fan wrote:
> Use vs18_enable, and drop CONFIG_SYS_FSL_ESDHC_FORCE_VSELECT.
>
> Signed-off-by: Peng Fan
> Cc: Otavio Salvador
> Cc: Stefano Babic
> Cc: Jaehoon Chung
> ---
>
> V3: none
> V2: none
>
> board/warp/warp.c | 2 +-
> include/configs/warp.h | 1 -
>
On 05/25/2017 03:53 AM, Chee, Tien Fong wrote:
> On Rab, 2017-05-24 at 09:56 -0500, Dinh Nguyen wrote:
>>
>> On 05/23/2017 09:24 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> This is the 6th version of patchset to adds support for Intel Arria
>>> 10 SoC FPGA
>>> driver
On 05/11/2017 11:28 AM, Peng Fan wrote:
> Handle vqmmc supply. Some boards have a fixed I/O voltage
> at 1.8V for emmc, so the usdhc also needs to be configured
> as 1.8V by setting VSELECT bit. The vs18_enable is the one
> that used to checking whether setting VSELECT or not in
> the driver. So if
On 05/11/2017 11:28 AM, Peng Fan wrote:
> When using eMMC with 1.8V I/O, the VSELECT bit need to be set in
> the USDHC controller when init.
>
> This patch adds a parameter "vs18_enable" in fsl_esdhc_cfg
> structure and priv data, so each controller can have different
> settings.
>
> We could not
On 05/11/2017 04:20 AM, Tom Rini wrote:
> Inside of
> max77686_buck_volt2hex/max77686_buck_hex2volt/max77686_ldo_volt2hex we
> check that the value we calculate is >= 0 however we declare 'hex' as
> unsigned int making these always true. Mark these as 'int' instead. We
> also move hex_max to int
Hi Tom,
On 05/11/2017 04:20 AM, Tom Rini wrote:
> In some places we check if part_config is set to MMCPART_NOAVAILABLE
> (0xff). With part_config being a char this is always false. We should
> be using a u8 to store this value instead, after a quick consultation
> with the Linux Kernel. Reporte
Hi Ziyuan,
On 05/25/2017 05:12 PM, Ziyuan wrote:
> hi Jaehoon,
>
> On 05/16/2017 09:55 AM, Jaehoon Chung wrote:
>> Hi Ziyuan,
>>
>> On 05/16/2017 10:15 AM, Ziyuan wrote:
>>> hi Simon & Jaehoon,
>>>
>>> On 05/16/2017 08:18 AM, Simon Glass wrote:
Hi Ziyuan,
On 15 May 2017 at 00:06, Z
On 05/15/2017 03:07 PM, Ziyuan Xu wrote:
> Card devices get into busy status since host request speed mode
> switch, if host controller is able to query whether the device is busy,
> try it instead of sending cmd13.
This patch is similar to one of Jean-Jacques's patches.
>
> Signed-off-by: Ziyua
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> Boot partitions do not support HS200. Changing to a lower performance mode
> is required to access them.
> mmc_select_mode_and_width() and sd_select_mode_and_width() are modified to
> make it easier to call them outside of the initialization cont
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> Add UHS modes to the list of supported modes, get the UHS capabilites of
> the SDcard and implement the procedure to switch the voltage (UHS modes
> use 1v8 IO lines)
> During the voltage switch procedure, DAT0 is used by the card to signal
> whe
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> Add HS200 to the list of supported modes and introduce tuning in the MMC
> startup process.
>
> Signed-off-by: Kishon Vijay Abraham I
> Signed-off-by: Jean-Jacques Hiblot
> ---
> drivers/mmc/mmc.c | 22 --
> include/mmc.h
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> Tuning is a mandatory step in the initialization of SDR104 and HS200 modes.
> This callback execute the tuning process.
>
> Signed-off-by: Jean-Jacques Hiblot
> ---
> drivers/mmc/mmc-uclass.c | 14 ++
> drivers/mmc/mmc.c|
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> mmc/sd specification requires vdd to be disabled for 1 ms
> and then enabled again during power cycle. Add a
> function in mmc core to perform power cycle and set
> the io signal to it's initial state.
>
> Signed-off-by: Kishon Vijay Abraham I
On 05/13/2017 03:16 AM, Jean-Jacques Hiblot wrote:
> The MMC startup process currently handles 4 modes. To make it easier to
> add support for more modes, let's make the process more generic and use a
> list of the modes to try.
> The major functional change is that when a mode fails we try the nex
On Wed, May 24, 2017 at 06:15:25PM -0600, Simon Glass wrote:
> Hi Tom,
>
> This incorporates the v2 patch for 'fdt: Build the new python libfdt
> module' which should fix the problem with the original pull request.
>
>
> The following changes since commit be62fbf376261ab3a4ed5db3bf54d5df9e216d9
On 05/25/2017 05:12 PM, Ziyuan wrote:
> hi Jaehoon,
>
> On 05/16/2017 09:55 AM, Jaehoon Chung wrote:
>> Hi Ziyuan,
>>
>> On 05/16/2017 10:15 AM, Ziyuan wrote:
>>> hi Simon & Jaehoon,
>>>
>>> On 05/16/2017 08:18 AM, Simon Glass wrote:
Hi Ziyuan,
On 15 May 2017 at 00:06, Ziyuan Xu wr
Update vcores for am571-idk board.
Reported-by: Steve Kipisz
Signed-off-by: Keerthy
Signed-off-by: Lokesh Vutla
---
board/ti/am57xx/board.c | 50 +
1 file changed, 50 insertions(+)
diff --git a/board/ti/am57xx/board.c b/board/ti/am57xx/board.c
i
Currently while setting the vsel value for dcdc1 and dcdc2
the driver is wrongly masking the entire 8 bits in the process
clearing PFM (bit7) field as well. Hence describe an appropriate
mask for vsel field and modify only those bits in the vsel
mask.
Source: http://www.ti.com/lit/ds/symlink/tps65
On 05/25/2017 10:53 AM, Chee, Tien Fong wrote:
> On Rab, 2017-05-24 at 09:56 -0500, Dinh Nguyen wrote:
>>
>> On 05/23/2017 09:24 PM, tien.fong.c...@intel.com wrote:
>>>
>>> From: Tien Fong Chee
>>>
>>> This is the 6th version of patchset to adds support for Intel Arria
>>> 10 SoC FPGA
>>> driver.
Hi Vikas,
> On 24 May 2017 18:32 Vikas MANOCHA wrote:
> Hi Phil,
>
> > On Wednesday, May 24, 2017 7:34 AM Phil Edworthy wrote:
> > The branch instruction only has an 11-bit relative target address, which is
> sometimes not enough.
> >
> > Signed-off-by: Phil Edworthy
> > ---
> > arch/arm/cpu/ar
On Wed, 24 May 2017 18:29:50 +0200
Fausto Sessego fausto.sess...@infomob.it wrote:
...
> The Kernel doesn't start.
>
> U-Boot 2016.07 (May 24 2017 - 17:11:18 +0200)
>
> CPU: Freescale i.MX6Q rev1.2 at 792MHz
> CPU: Industrial temperature grade (-40C to 105C) at 20C
> Reset cause: POR
> Board:
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