On 3.4.2017 16:18, Olliver Schinagl wrote:
> The .read_rom_hwaddr net_ops hook does not check the return value, which
> is why it was never caught that we are currently returning 0 if the
> read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.
>
> In this case we can simplify this by just
Signed-off-by: Priyanka Jain
Signed-off-by: Suresh Gupta
---
arch/arm/cpu/armv8/fsl-layerscape/Kconfig |1 +
arch/arm/dts/fsl-ls2080a-rdb.dts | 22 +++
board/freescale/ls2080ardb/ls2080ardb.c | 23 +++-
configs/ls2088ardb_qspi_defconfig | 41 +
2017-04-05 14:05 GMT+09:00 Kever Yang :
> ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation
> about ATF at: https://github.com/ARM-software/arm-trusted-firmware
>
> SPL is considered as BL2 in ATF terminology, it needs to load other parts
> of ATF binary like BL31, BL32, SC
This patch needs work with some patch for SPL support multi
binary in FIT which is from Andre.
The entry point of bl31 and bl33 is still using hard code because we
still can not get them from the FIT image information.
This patch tested on rk3399 platform.
Changes in v3:
- remove no neccessary
ATF(ARM Trusted Firmware) is used by ARM arch64 SoCs, find more infomation
about ATF at: https://github.com/ARM-software/arm-trusted-firmware
SPL is considered as BL2 in ATF terminology, it needs to load other parts
of ATF binary like BL31, BL32, SCP-BL30, and BL33(U-Boot). And needs to
prepare th
Hi,
On 04/01/2017 12:22 PM, Simon Glass wrote:
Hi,
On 28 March 2017 at 08:37, Andre Przywara wrote:
Hi,
On 28/03/17 15:16, Dan Handley wrote:
Hi Kever
-Original Message-
From: Kever Yang [mailto:kever.y...@rock-chips.com]
Sent: 28 March 2017 08:23
Hi Andre,
On 03/23/2017 05:22
Signed-off-by: Santan Kumar
Signed-off-by: Priyanka Jain
---
arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
b/arch/arm/cpu/armv8/fsl-layerscape/ls2080a_serdes.c
index ab83e85..4db3c76 1006
Hi Simon,
On Sat, Apr 1, 2017 at 12:22 PM, Simon Glass wrote:
> Hi,
>
> On 31 March 2017 at 09:45, Bin Meng wrote:
>> On Thu, Mar 30, 2017 at 6:58 PM, Stefan Roese wrote:
>>> Now that we have added file names from Kconfig in x86 u-boot.dtsi,
>>> update binman to avoid using hard-coded names.
>>
On Fri, Mar 31, 2017 at 11:45 PM, Bin Meng wrote:
> On Thu, Mar 30, 2017 at 6:58 PM, Stefan Roese wrote:
>> Now that we have added file names from Kconfig in x86 u-boot.dtsi,
>> update binman to avoid using hard-coded names.
>>
>> Signed-off-by: Stefan Roese
>> Cc: Bin Meng
>> Cc: Simon Glass
On Wed, Apr 5, 2017 at 10:38 AM, Bin Meng wrote:
> On Fri, Mar 31, 2017 at 2:09 PM, Stefan Roese wrote:
>> Checking 'is_zimage' at this time will always fail and therefore booting
>> a FIT style image will always lead to this error message:
>>
>> "## Kernel loading failed (missing x86 kernel setu
On Fri, Mar 31, 2017 at 11:45 PM, Bin Meng wrote:
> On Thu, Mar 30, 2017 at 6:58 PM, Stefan Roese wrote:
>> Since we now have the file names configurable via Kconfig for the flash
>> descriptor and intel-me files, add these from Kconfig in the corresponding
>> dts nodes.
>>
>> Signed-off-by: Stef
On Fri, Mar 31, 2017 at 11:45 PM, Bin Meng wrote:
> On Thu, Mar 30, 2017 at 6:58 PM, Stefan Roese wrote:
>> This introduces two Kconfig options to enable board specific filenames
>> for the Intel binary blobs to be used to generate the SPI flash image.
>>
>> Signed-off-by: Stefan Roese
>> Cc: Bi
With recent changes, some x86-specific rom tests of binman fail to
run. Fix it by adding missing filenames in corresponding entries.
Signed-off-by: Bin Meng
---
tools/binman/test/30_x86-rom-me-no-desc.dts | 1 +
tools/binman/test/31_x86-rom-me.dts | 2 ++
tools/binman/test/32_intel-vga.
Hi Tom,
I think we finally have the problems sorted out with the 'rock' board
so this is included here along with two other derivative boards and
various improvements.
The following changes since commit 11db152246607868f0e74db958947fbf79f28119:
Prepare v2017.05-rc1 (2017-04-04 17:53:24 -0400)
Hi eric,
2017-04-01 22:42 GMT+08:00 :
> From: "eric.gao"
>
> Signed-off-by: eric.gao
> ---
>
> arch/arm/dts/rk3399-evb.dts | 33 ++
> arch/arm/dts/rk3399.dtsi | 72 +
> arch/arm/include/asm/arch-rockchip/cru_rk3399.h | 2 +-
> arch/arm/incl
On 31 March 2017 at 22:22, Simon Glass wrote:
> On 24 March 2017 at 15:47, Vikas Manocha wrote:
>> This patch replaces SPL_PINCTRL_FULL with SPL_PINCNTRL. It is to avoid
>> removal
>> of pin control properties in case of SPL_PINCTRL. No impact in case of
>> SPL_PINCTRL_FULL as it depends on SPL_
On 27 March 2017 at 03:02, Stefan Roese wrote:
> Add a test for the correct device removal. Currently two different ways
> for device removal are supported:
>
> - Normal device removal via the device_remove() API
> - Removal via selective device driver flags (DM_FLAG_ACTIVE_DMA)
>
> This new test
On 25 March 2017 at 19:17, Simon Glass wrote:
> On 20 March 2017 at 05:51, Stefan Roese wrote:
>> This patch adds the flags parameter to device_remove() and changes all
>> calls to this function to provide the default value of DM_REMOVE_NORMAL
>> for "normal" device removal.
>>
>> This is in prep
On 20 March 2017 at 05:51, Stefan Roese wrote:
> This patch adds a call to dm_remove_devices_flags() to
> announce_and_cleanup() so that drivers that have one of the removal flags
> set (e.g. DM_FLAG_ACTIVE_DMA_REMOVE) in their driver struct, may do some
> last-stage cleanup before the OS is start
On 27 March 2017 at 02:58, Stefan Roese wrote:
> The new function dm_remove_devices_flags() is intented for driver specific
> last-stage cleanup operations before the OS is started. This patch adds
> this functionality and hooks it into the common device_remove()
> function.
>
> Drivers wanting to
Hi Vikas,
On 4 April 2017 at 15:59, Vikas Manocha wrote:
> Address translation is not working at present even if SPL_OF_TRANSLATE is
> enabled which makes this configuration useless. This patch enables address
> translation for SPL U-Boot when SPL_OF_TRANSLATE is selected.
>
> Signed-off-by: Vika
On Fri, Mar 31, 2017 at 2:09 PM, Stefan Roese wrote:
> Checking 'is_zimage' at this time will always fail and therefore booting
> a FIT style image will always lead to this error message:
>
> "## Kernel loading failed (missing x86 kernel setup) ..."
>
> This change now removes this check and booti
From: Ye Li
The num/denom is a float value, but in the calculation it is convert
to integer 0, and wrong result.
Signed-off-by: Ye Li
Signed-off-by: Peng Fan
Cc: Stefano Babic
---
arch/arm/cpu/armv7/mx7ulp/scg.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/arch
According to the Cortex-A7 TRM, for ACTLR.SMP bit "You must ensure
this bit is set to 1 before the caches and MMU are enabled, or any
cache and TLB maintenance operations are performed".
ROM sets this bit in normal boot flow, but when in serial download
mode, it is not set. Here we add it in u-boo
Hi,
On 4 April 2017 at 19:26, Kever Yang wrote:
> Hi Eddie,
>
>
> We should only need to do only one time cache operation for a buffer
>
> ready to do DMA transfer, so you need to remove another cache invalidate
>
> operation for the same buffer in the same function.
I think this is a more g
Hi,
On 4 April 2017 at 20:02, Simon Glass wrote:
> At present if the return to bootrom fails (e.g. because you are not using
> the Rockchip's bootrom's pointer table in MMC) then the board prints
> SPL message and hangs. Print a message first if we can, to help in
> understanding what happened wh
At present if the return to bootrom fails (e.g. because you are not using
the Rockchip's bootrom's pointer table in MMC) then the board prints
SPL message and hangs. Print a message first if we can, to help in
understanding what happened when it hangs.
Signed-off-by: Simon Glass
---
arch/arm/in
Hi Eddie,
We should only need to do only one time cache operation for a buffer
ready to do DMA transfer, so you need to remove another cache invalidate
operation for the same buffer in the same function.
Thanks,
- Kever
On 04/01/2017 02:51 PM, Eddie Cai wrote:
We should invalidate the d
Hey all,
It's the day after the normal release day for v2017.05-rc1 but it's out
now. I've been on vacation[1] and my wireless access was less than I
expected so the PRs piled up and I was just on vacation. The merge
window is now closed and I've updated git and the tarballs are also up
now.
I
On Tue, Apr 04, 2017 at 10:56:00AM -0700, Tom Warren wrote:
> Tom,
>
> Please pull u-boot-tegra/master into U-Boot/master. Thanks!
>
> All Tegra builds are OK, and Stephen's automated test system reports that
> all tests pass.
>
> The following changes since commit 5cf618ee60a752d058a767372ca1e
On 31 March 2017 at 22:24, Simon Glass wrote:
> On 29 March 2017 at 13:19, Philipp Tomsich
> wrote:
>> The (shared) rk3399.dtsi had defined the 'rockchip,vbus-gpio'
>> properties for each USB 3.0 controller.
>>
>> As the GPIO usage will vary (e.g. one of those GPIOs shuts down one of
>> the regul
On 4 April 2017 at 03:38, Heiko Stübner wrote:
>
> Am Sonntag, 2. April 2017, 09:50:28 CEST schrieb Simon Glass:
> > Most of the time the optimised memset() is what we want. For extreme
> > situations such as TPL it may be too large. For example on the 'rock'
> > board, using a simple loop saves a
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 29 March 2017 at 05:31, Philipp Tomsich
> wrote:
>> From: Jakob Unterwurzacher
>>
>> On the RK3399-Q7 we need to enable a number of configuration options
>> (e.g. CONFIG_SPI_FLASH_WINBND) dependent on Kconfig seeing CONFIG_SPI
>> and CONFIG_SPI_
On 4 April 2017 at 11:06, Heiko Stuebner wrote:
> Am Dienstag, 4. April 2017, 12:29:53 CEST schrieb Tom Rini:
>> On Fri, Mar 31, 2017 at 10:24:07PM -0600, Simon Glass wrote:
>> > On 26 March 2017 at 16:38, Heiko Stuebner wrote:
>> > > I've added Tom for comments, executive summary:
>> > > - rk318
On 31 March 2017 at 22:24, Simon Glass wrote:
> On 28 March 2017 at 10:48, Philipp Tomsich
> wrote:
>> This commit adds the baseline defconfig for the RK3399-Q7 (Puma) SoM
>> (under the name 'puma-rk3399_defconfig') featuring the Rockchip RK3399
>> in a Qseven compatible module.
>>
>> This subsum
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 29 March 2017 at 17:23, Jernej Skrabec wrote:
>> MiQi is rk3288 based development board with 1 or 2 GB SDRAM, 16 GB eMMC,
>> micro SD card interface, 4 USB 2.0 ports, HDMI, gigabit Ethernet and
>> expansion ports.
>>
>> Signed-off-by: Jernej Skra
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 28 March 2017 at 10:48, Philipp Tomsich
> wrote:
>> The RK3399-Q7 is a system-on-module featuring the Rockchip RK3399
>> in a Qseven-compatible form-factor.
>>
>> These changes add a device-tree describing the board and its
>> interfaces for basi
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 29 March 2017 at 17:23, Jernej Skrabec wrote:
>> Sort rk3288 boards in alphabetical order.
>>
>> Signed-off-by: Jernej Skrabec
>> ---
>> Changes in v3:
>> - new patch
>>
>> arch/arm/dts/Makefile | 10 ++--
>> arch/arm/mach-rockc
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 28 March 2017 at 10:48, Philipp Tomsich
> wrote:
>> For the initial validation of the RK3399-Q7 (Puma), the DDR3 has been
>> clocked at 666MHz (i.e. DDR3-1333) using the same (safe) settings as
>> used in Rockchip's MiniLoader.
>>
>> Signed-off-b
On 31 March 2017 at 22:23, Simon Glass wrote:
> On 28 March 2017 at 03:03, Philipp Tomsich
> wrote:
>> The RK3399 does not have any boot selection pins and the BootROM probes
>> the boot interfaces using the following boot-order:
>> 1. SPI
>> 2. eMMC (sdhci in DTS)
>> 3. SD card (sdmm
Hi Jaehoon,
On 2017/3/30 12:30, Jaehoon Chung wrote:
Hi Wenyou,
On 03/23/2017 01:48 PM, Wenyou Yang wrote:
Add the driver model support for Atmel mci while retaining the
existing legacy code. This allows the driver to support boards
that have converted to driver model as well as those that ha
This patch is required for correct SPL device tree creation by fdtgrep
as fdtgrep looks for u-boot,dm-pre-reloc property of the node to include
it in the spl device tree.
Not adding it in these subnodes ignores the pin muxing of peripherals
which is almost always in the subnodes.
Signed-off-by: V
Hi Jagan,
On Tue, Apr 4, 2017 at 2:27 PM, Jagan Teki wrote:
> No, this isn't issue, just want to understand how you create reg init
> in SPL in mx6q_dcd_table, means did you follow any order. because I'm
> planning move *dl.cfg DCD to SPL
Ok, got it. I thought you were asking about mx6qp sabrea
Address translation is not working at present even if SPL_OF_TRANSLATE is
enabled which makes this configuration useless. This patch enables address
translation for SPL U-Boot when SPL_OF_TRANSLATE is selected.
Signed-off-by: Vikas Manocha
Reviewed-by: Simon Glass
---
Changes in v3: changed "u-
Address translation is not working at present even if SPL_OF_TRANSLATE is
enabled which makes this configuration useless. This patch enables address
translation for SPL U-Boot when SPL_OF_TRANSLATE is selected.
Signed-off-by: Vikas Manocha
Reviewed-by: Simon Glass
---
Changes in v2: changed "u-b
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746.dtsi | 1 +
drivers/spi/stm32_qspi.c| 16 +++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/arch/arm/dts/stm32f746.dtsi b/arch/arm/dts/stm32f746.dtsi
index b2b0b
This patch also removes the sdram/fmc clock enable from board specific
code.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746.dtsi| 1 +
board/st/stm32f746-disco/stm32f746-disco.c | 2 --
drivers/ram/stm32_sdram.c
The number of pins to be configured could be more than 50 e.g. in case
of sdram controller, there are about 56 pins (32 data lines, 12 address
& some control signals).
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
drivers/pinctrl/pinctrl_stm32.c | 3 ++-
1 file ch
With this gpio driver supporting DM, there is no need to enable clocks
for different gpios (for pin muxing) in the board specific code.
Need to increase the allocatable area required before relocation from 0x400 to
0xC00 becuase of 10 new gpio devices(& new gpio class) added in device tree.
Signe
Actually the sdram memory on stm32f746 discovery board is micron part
MT48LC_4M32_B2B5_6A. This patch does the modification required in the
device tree node & driver for the same.
Also we are passing here all the timing parameters in terms of clock
cycles, so no need to convert time(ns or ms) to c
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
include/configs/stm32f746-disco.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/stm32f746-disco.h
b/include/configs/stm32f746-disco.h
index 3bea513..b6ad8d2 100644
--- a/include/configs/stm32f746-
This board support stm32f7 family device stm32f769-I with 2MB internal Flash &
512KB RAM.
STM32F769 lines offer the performance of the Cortex-M7 core (with double
precision floating point unit) running up to 216 MHz.
To compile for stm32f769 board, use same defconfig as stm32f746-disco,
the only d
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746-disco.dts | 90
arch/arm/dts/stm32f746.dtsi | 86 --
2 files changed, 90 insertions(+), 86 deletions(-)
diff --gi
All discovery boards have one user button & one user LED. Here we are
just reading the button status & switching ON the user LED.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746-disco.dts | 10
board/st/stm32f746-disco/stm32
This patch adds gpio driver supporting driver model for stm32f7 gpio.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changes in v2:
- included files in correct order.
- moved the pinctrl specific routine from gpio driver to pinctrl
- used dev_get_addr() instead of fdtdec_get_addr_size_
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
drivers/ram/stm32_sdram.c | 31 +++
1 file changed, 31 insertions(+)
diff --git a/drivers/ram/stm32_sdram.c b/drivers/ram/stm32_sdram.c
index 13f8964..67be61f 100644
--- a/drivers/ram/stm32_
Also created alias for gpios for stm32f7 discovery board. Based on these
aliases, it would be possible to get gpio devices by sequence.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746-disco.dts | 12 +
arch/arm/dts/stm32f746.dtsi | 1
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746-disco.dts | 10 +++
drivers/ram/stm32_sdram.c| 144 +++
include/dt-bindings/memory/stm32-sdram.h | 34
3 files changed, 135 insertion
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
board/st/stm32f746-disco/stm32f746-disco.c | 42 +-
drivers/ram/stm32_sdram.c | 1 -
include/configs/stm32f746-disco.h | 6 +
3 files changed, 30 insertions(+)
This patch removes:
- CONFIG_CMD_MEM: enabled by default
- CONFIG_DESIGNWARE_ETH : not being used anywhere.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
include/configs/stm32f746-disco.h | 2 --
1 file changed, 2 deletions(-)
diff --git a/include
Also added DT binding doc for stm32 fmc(flexible memory controller).
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
arch/arm/dts/stm32f746-disco.dts | 7
arch/arm/dts/stm32f746.dtsi | 56 +++
doc/device-t
As driver model takes care of pin control configuraion, this patch also
removes the sdram/fmc pin configuration.
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
board/st/stm32f746-disco/stm32f746-disco.c | 89 +++---
1 file changed, 19 insert
Signed-off-by: Vikas Manocha
cc: Christophe KERELLO
---
Changed in v2: None
board/st/stm32f746-disco/stm32f746-disco.c | 113 +--
configs/stm32f746-disco_defconfig | 2 +
drivers/ram/Kconfig| 8 ++
drivers/ram/Makefile
This patchset :
- adds stm32 sdram driver based on DM
- adds stm32 gpio driver based on DM
- uses clock & pin control drivers to replace board specific
configurations from code
- corrects sdram parameters as per correct sdram part
- adds support for
ERR_remove_thread_state is deprecated in OpenSSL 1.1.x and does not do
anything anymore. Thread initialisation and deinitialisation is now
handled by the OpenSSL library.
Signed-off-by: Jelle van der Waa
Reviewed-by: Simon Glass
---
lib/rsa/rsa-sign.c | 4 ++--
1 file changed, 2 insertions(+),
The rsa_st struct has been made opaque in 1.1.x, add forward compatible
code to access the n, e, d members of rsa_struct.
EVP_MD_CTX_cleanup has been removed in 1.1.x and EVP_MD_CTX_reset should be
called to reinitialise an already created structure.
Signed-off-by: Jelle van der Waa
---
tools/k
The rsa_st struct has been made opaque in 1.1.x, add forward compatible
code to access the n, e, d members of rsa_struct.
EVP_MD_CTX_cleanup has been removed in 1.1.x and EVP_MD_CTX_reset should be
called to reinitialise an already created structure.
Tested-by: Peter Robinson
---
lib/rsa/rsa-si
On 2017-04-04 13:17, Marek Vasut wrote:
> On 04/04/2017 09:45 PM, Stefan Agner wrote:
>> On 2017-04-04 11:38, Marek Vasut wrote:
>>> On 04/04/2017 07:57 PM, Stefan Agner wrote:
On 2017-04-04 02:22, Marek Vasut wrote:
> On 04/04/2017 02:02 AM, Stefan Agner wrote:
> [...]
> Admit
> On 04 Apr 2017, at 22:09, Marek Vasut wrote:
>
>> The DWC3 flush expands to a clean+invalidate. It is not wrong, as long as
>> it is used as in my patch:
>> a. before the first time data is expected to be written by the peripheral
>> (i.e.
>> before the peripheral is started)—to ensure that t
On 04/04/2017 09:45 PM, Stefan Agner wrote:
> On 2017-04-04 11:38, Marek Vasut wrote:
>> On 04/04/2017 07:57 PM, Stefan Agner wrote:
>>> On 2017-04-04 02:22, Marek Vasut wrote:
On 04/04/2017 02:02 AM, Stefan Agner wrote:
[...]
Admitedly, I didn't look at the patch, but if you wan
On 04/04/2017 09:56 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 21:01, Marek Vasut wrote:
>>
>>> Good point on the “long”, especially as I just copied this from other
>>> occurrences and it’s consistently wrong throughout DWC3 in U-Boot:
>>
>> Hrm, I thought the driver was ported over
On Wed, Mar 29, 2017 at 05:51:04PM -0600, Simon Glass wrote:
> Hi Tom,
>
> Herewith some fairly minor changes from my patchwork queue.
>
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
> Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
>
> ar
On Thu, Mar 30, 2017 at 02:29:54PM -0500, Robert Nelson wrote:
> BeagleBone Blue is next grenation of boards from BeagleBoard.org, focusing
> on robotics with a TI wl1835 wireless module for connectivity.
>
> This board can be indentified by the BLAx value after A335BNLT (BBB)
> in the at24 eepro
On Thu, Mar 30, 2017 at 02:29:53PM -0500, Robert Nelson wrote:
> SeeedStudio BeagleBone Green Wireless (BBGW) is an expansion of the
> SeeedStudio Green (BBG) with the Ethernet replaced by a TI wl1835
> wireless module.
>
> This board can be indentified by the GW1x value after A335BNLT (BBB)
> in
On Thu, Mar 30, 2017 at 02:21:39PM +0900, Jaehoon Chung wrote:
> Dear Tom,
>
> Could pull these patches into u-boot/master?
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
> Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
>
> are available in
On Wed, Mar 29, 2017 at 05:51:04PM -0600, Simon Glass wrote:
> Hi Tom,
>
> Herewith some fairly minor changes from my patchwork queue.
>
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
> Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
>
> ar
On Fri, Mar 31, 2017 at 07:12:18PM +, Alexey Brodkin wrote:
> Hi Tom,
>
> In this patch-set we add support of new AXS103 firmware as well
> as troubleshoot unexpected execution by multiple cores simultaneously.
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
On Thu, Mar 30, 2017 at 02:29:52PM -0500, Robert Nelson wrote:
> BeagleBone Black Wireless is clone of the BeagleBone Black (BBB) with
> the Ethernet replaced by a TI wl1835 wireless module.
>
> This board can be indentified by the BWAx value after A335BNLT (BBB)
> in the at24 eeprom:
> BWAx [aa
On Wed, Mar 29, 2017 at 11:24:23AM +0200, Stefan Roese wrote:
> Hi Tom,
>
> please pull the Marvell mvpp2 patches with the ethernet
> support for the ARMv8 Armada 7k/8k platforms. The
> ethernet patches are all acked by Joe and he is okay with
> me pushing them via the Marvell tree.
>
> Thanks,
On Tue, Mar 28, 2017 at 06:02:35PM +, york sun wrote:
> Tom,
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
>Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
>
> are available in the git repository at:
>
>git://git.denx.de/u-boot-fs
On Tue, Mar 28, 2017 at 09:31:54AM +0200, Heiko Schocher wrote:
> Hello Tom,
>
> please pull from u-boot-i2c.git master
>
> checked this branch on travis, no errors found.
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
> Merge git://git.denx.de/u-boot-arc
On Mon, Mar 27, 2017 at 11:50:12AM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
>
> Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400)
>
> are available in the git repository at:
>
>
> git://git.denx.d
> On 04 Apr 2017, at 21:01, Marek Vasut wrote:
>
>> Good point on the “long”, especially as I just copied this from other
>> occurrences and it’s consistently wrong throughout DWC3 in U-Boot:
>
> Hrm, I thought the driver was ported over from Linux, so is this broken
> in Linux too ?
Apparent
On 2017-04-04 11:38, Marek Vasut wrote:
> On 04/04/2017 07:57 PM, Stefan Agner wrote:
>> On 2017-04-04 02:22, Marek Vasut wrote:
>>> On 04/04/2017 02:02 AM, Stefan Agner wrote:
>>> [...]
>>> Admitedly, I didn't look at the patch, but if you want to boot ad-hoc
>>> cores, you can very well a
On Tue, Mar 28, 2017 at 11:37:45AM +0530, Lokesh Vutla wrote:
> + more folks.
>
> On Tuesday 28 March 2017 03:14 AM, Nishanth Menon wrote:
> > Hi,
> >
> > we've kind of run into an interesting situation recently, but might be
> > of interest for various folks trying to reduce the image sizes.
> >
On 04/04/2017 07:46 PM, Dr. Philipp Tomsich wrote:
>
>> On 04 Apr 2017, at 18:15, Marek Vasut wrote:
>>
>> On 04/03/2017 07:49 PM, Philipp Tomsich wrote:
>>> Merely using dma_alloc_coherent does not ensure that there is no stale
>>> data left in the caches for the allocated DMA buffer (i.e. that
There is a strange interaction with drivers which use DMA if the cache
starts off in a dirty state. Buffer space which the driver reads (but has
not previously written) can contain zero bytes from alloc_priv(). This can
cause corruption of the memory used by DMA for incoming data.
Fix this and add
On 2017-04-04 01:23, Lukasz Majewski wrote:
> Hi Stefan,
>
>> Hi Lukasz,
>>
>> On 2017-04-03 04:20, Lukasz Majewski wrote:
>> > Hi Stefan,
>> >
>> > Thanks for your patch. Please allow me to share some ideas for
>> > improvements.
>> >
>> >> From: Stefan Agner
>> >>
>> >> This patchset enables to
On 2017-04-04 01:53, Stefano Babic wrote:
> Hi Stefan,
>
> On 03/04/2017 23:02, Stefan Agner wrote:
>
>> But then, I don't expect that "/usr/bin/env python" is looking at
>> PYTHON.
>>
>> As far as I understand env, it just looks up the current environment to
>> run its COMMAND argument.
>
> Agr
On 04/04/2017 07:57 PM, Stefan Agner wrote:
> On 2017-04-04 02:22, Marek Vasut wrote:
>> On 04/04/2017 02:02 AM, Stefan Agner wrote:
>> [...]
>> Admitedly, I didn't look at the patch, but if you want to boot ad-hoc
>> cores, you can very well also boot secondary cores on the current CPU
>>>
On 2017-04-04 02:22, Marek Vasut wrote:
> On 04/04/2017 02:02 AM, Stefan Agner wrote:
> [...]
> Admitedly, I didn't look at the patch, but if you want to boot ad-hoc
> cores, you can very well also boot secondary cores on the current CPU
> complex with the same command. Why not ?
>
Tom,
Please pull u-boot-tegra/master into U-Boot/master. Thanks!
All Tegra builds are OK, and Stephen's automated test system reports that
all tests pass.
The following changes since commit 5cf618ee60a752d058a767372ca1ecb8d9c09b16:
Merge git://git.denx.de/u-boot-arc (2017-03-24 08:19:30 -0400
On Mon, Apr 3, 2017 at 9:18 AM, Olliver Schinagl wrote:
>
> The .read_rom_hwaddr net_ops hook does not check the return value, which
> is why it was never caught that we are currently returning 0 if the
> read_rom_hwaddr function return -ENOSYS and -ENOSYS otherwise.
>
> In this case we can simpli
> On 04 Apr 2017, at 18:15, Marek Vasut wrote:
>
> On 04/03/2017 07:49 PM, Philipp Tomsich wrote:
>> Merely using dma_alloc_coherent does not ensure that there is no stale
>> data left in the caches for the allocated DMA buffer (i.e. that the
>> affected cacheline may still be dirty).
>>
>> The
uclass_find_device_by_seq() prints seq and req_seq when debugging is
enabled, but this information is not very useful by itself. Add the
name of he driver to this information. This improves debugging as it
shows which devices are being considered.
Signed-off-by: Alexandru Gagniuc
---
drivers/cor
Under the plethora of #ifdefs, the xyzModem code hid this pearl:
static char *zm_out = (char *) 0x0038;
This was only enabled when DEBUG is defined, so it's probably why it
went unnoticed for so long. No idea what platform had memory at that
exact location, but the this approach is extremely ha
Signed-off-by: Alexandru Gagniuc
---
common/xyzModem.c | 103 -
include/xyzModem.h | 7
2 files changed, 110 deletions(-)
diff --git a/common/xyzModem.c b/common/xyzModem.c
index e0d87db..6ded958 100644
--- a/common/xyzModem.c
+++ b/com
> -Original Message-
> From: york sun
> Sent: Tuesday, April 04, 2017 9:29 PM
> To: Ruchika Gupta ; u-boot@lists.denx.de
> Cc: Vini Pillai ; Sumit Garg
> Subject: Re: [PATCH 3/3][v3] [RESEND] arm: ls1046ardb: Add SD secure boot
> target
>
> On 04/04/2017 12:06 AM, Ruchika Gupta wrote:
> >
- Add SD secure boot target for ls1046ardb.
- Change the u-boot size defined by a macro for copying the main U-Boot by SPL
to also include the u-boot Secure Boot header size as header is appended to
u-boot image. So header will also be copied from SD to DDR.
- CONFIG_MAX_SPL_SIZE is limited to
Add NAND secure boot target for ls1043ardb.
- Change the u-boot size defined by a macro for copying the main
U-Boot by SPL to also include the u-boot Secure Boot header size as
header is appended to u-boot image. So header will also be copied from SD to
DDR.
- MACRO for CONFIG_BOOTSCRIPT_COPY
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