On 6.3.2017 23:13, Joe Hershberger wrote:
> On Sun, Mar 5, 2017 at 8:36 AM, Nathan Rossi wrote:
>> When the zynq_gem driver initializes the phy it sets the supported
>> features that the phy can support and advertise. However instead of
>> masking the supported features such that it limits the ava
Hi Prabhakar,
Thanks for your comments!
> -Original Message-
> From: Prabhakar Kushwaha
> Sent: Tuesday, March 07, 2017 11:17 AM
> To: Z.Q. Hou ; u-boot@lists.denx.de;
> o...@buserror.net; york sun ;
> mingkai...@freescale.com; s...@chromium.org; Xiaobo Xie
>
> Cc: Z.Q. Hou
> Subject: R
Hi Heiko,
That patch break all the Rockchip SoCs SPL which using spl_init().
Eddie send one patch for rk3288 by add a spl_early_init(), which is
under review, I also look forward for better solution.
Thanks,
- Kever
On 03/07/2017 08:42 AM, Heiko Stübner wrote:
Hi,
I just realized patch b3d286
Hi Marek,
On 03/07/2017 10:55 AM, Marek Vasut wrote:
On 03/06/2017 01:54 PM, Kever Yang wrote:
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
Signed-off-by:
On 03/07/2017 05:31 AM, york sun wrote:
On 03/06/2017 07:59 PM, Marek Vasut wrote:
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing wi
Enable PPA on LS2080A, LS2088A boards:
-LS2080ARDB, LS2080AQDS
-LS2088ARDB, LS2088AQDS
Signed-off-by: Santan Kumar
Signed-off-by: Abhimanyu Saini
Signed-off-by: Priyanka Jain
---
Changes for v2:
Changed the subject
Made changes based on latest ppa config
arch/arm/cpu/armv8/fsl-layerscape/Kc
RK3288 using the dwc2 USB host controller, enable it and other usb host
funtion like storage and ethernet.
Signed-off-by: Eddie Cai
---
configs/fennec-rk3288_defconfig | 3 +++
configs/firefly-rk3288_defconfig | 3 +++
configs/tinker-rk3288_defconfig | 3 +++
3 files changed, 9 insertions(+)
Tinker board have a usb host. add dts node to provide power supply.
Signed-off-by: Eddie Cai
---
arch/arm/dts/rk3288-tinker.dts | 11 +++
arch/arm/dts/rk3288-tinker.dtsi | 12
2 files changed, 23 insertions(+)
diff --git a/arch/arm/dts/rk3288-tinker.dts b/arch/arm/dts/rk32
On 03/06/2017 07:59 PM, Marek Vasut wrote:
> On 03/06/2017 06:02 PM, York Sun wrote:
>> Early MMU improves performance especially on emulators. However, the
>> early MMU is left enabled after the first stage of SPL boot. Instead
>> of flushing D-cache and dealing with re-enabling MMU for the second
On 03/06/2017 08:39 AM, Ley Foon Tan wrote:
On Sab, 2017-02-25 at 22:36 +0100, Marek Vasut wrote:
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
Add system manager support for Arria 10.
But these are just headers, there's no system manager code here ?
Yes. Mainly for system manager's register s
On 03/06/2017 08:10 AM, Ley Foon Tan wrote:
On Sab, 2017-02-25 at 22:35 +0100, Marek Vasut wrote:
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
Add clock driver support for Arria 10 and update Gen5 clock driver.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
[...]
diff --gi
On 03/06/2017 03:25 AM, Dalon Westergreen wrote:
On Sun, 2017-03-05 at 18:49 +0100, Marek Vasut wrote:
On 03/05/2017 06:38 PM, Dalon Westergreen wrote:
On Tue, 2017-02-28 at 06:45 -0800, Dalon Westergreen wrote:
On Mon, 2017-02-20 at 06:35 -0800, Dalon Westergreen wrote:
On Mon, 2017-02-2
On 03/06/2017 09:00 AM, Ley Foon Tan wrote:
On Sab, 2017-02-25 at 22:40 +0100, Marek Vasut wrote:
On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
Add misc support for Arria 10 and minor fix on misc Gen5.
Signed-off-by: Tien Fong Chee
Signed-off-by: Ley Foon Tan
---
arch/arm/mach-socfpga/Makefi
On 03/06/2017 06:02 PM, York Sun wrote:
Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing with re-enabling MMU for the second
stage U-Boot, disabling it for SPL build simplifies
On 03/06/2017 01:54 PM, Kever Yang wrote:
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
Signed-off-by: Simon Glass
---
Changes in v4:
- Drop no use code com
On 03/06/2017 05:45 AM, Chee, Tien Fong wrote:
On Ahd, 2017-03-05 at 01:57 +0100, Marek Vasut wrote:
On 03/03/2017 01:50 PM, Chee Tien Fong wrote:
From: Tien Fong Chee
This patch removes the unused passing parameter of
socfpga_bridges_reset
function in Arria10.
Signed-off-by: Tien Fong Chee
On 03/06/2017 01:36 PM, Kever Yang wrote:
Hi Simon,
On 12/04/2016 02:27 AM, Simon Glass wrote:
Hi Marek, Kever,
On 3 December 2016 at 06:15, Marek Vasut wrote:
On 12/03/2016 05:29 AM, Simon Glass wrote:
From: Kever Yang
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gp
On 03/06/2017 11:21 PM, Steve Rae wrote:
The "chunks" in the "fastboot sparse image" are not aligned,
resulting in many "cached misaligned" messages from
check_cache_range(). Implement a runtime flag to suppress this
message, and use this flag when processing the "fastboot sparse
image".
Let me
On 03/05/2017 07:37 PM, Frank Kunz wrote:
Am 05.03.2017 um 18:17 schrieb Marek Vasut:
On 03/05/2017 01:54 PM, Frank Kunz wrote:
Those features are used by distro boot with efi boot.
Signed-off-by: Frank Kunz
---
:100644 100644 b122135690... c22b54b48d... M
configs/socfpga_de0_nano_soc_defconf
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhiqiang
> Hou
> Sent: Friday, March 03, 2017 7:01 PM
> To: u-boot@lists.denx.de; o...@buserror.net; york sun ;
> mingkai...@freescale.com; s...@chromium.org; Xiaobo Xie
>
> Cc: Z.Q. Hou
> Subject: [U-
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Zhiqiang
> Hou
> Sent: Friday, March 03, 2017 7:01 PM
> To: u-boot@lists.denx.de; o...@buserror.net; york sun ;
> mingkai...@freescale.com; s...@chromium.org; Xiaobo Xie
>
> Cc: Z.Q. Hou
> Subject: [U-
On Isn, 2017-02-27 at 17:06 +0100, Michal Simek wrote:
> On 25.2.2017 22:44, Marek Vasut wrote:
> >
> > On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> > >
> > > Arria 10 SPL needs the drivers/fpga.
> > >
> > > Signed-off-by: Tien Fong Chee
> > > Signed-off-by: Ley Foon Tan
> > > ---
> > > driv
On Sab, 2017-02-25 at 22:43 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> >
> > Add SPL support for Arria 10.
> >
> > Signed-off-by: Tien Fong Chee
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/mach-socfpga/spl.c | 92
> > +
On Tue, Mar 07, 2017 at 03:02:05AM +0200, Siarhei Siamashka wrote:
> On Mon, 6 Mar 2017 17:54:17 -0500
> Tom Rini wrote:
>
> > On Tue, Mar 07, 2017 at 12:44:59AM +0200, Siarhei Siamashka wrote:
> > > Hi Tom,
> > >
> > > On Mon, 6 Mar 2017 13:50:10 -0500
> > > Tom Rini wrote:
> > >
> > > > T
On Mon, 6 Mar 2017 17:54:17 -0500
Tom Rini wrote:
> On Tue, Mar 07, 2017 at 12:44:59AM +0200, Siarhei Siamashka wrote:
> > Hi Tom,
> >
> > On Mon, 6 Mar 2017 13:50:10 -0500
> > Tom Rini wrote:
> >
> > > Today, we have cases where we wish to build all of U-Boot in Thumb2 mode
> > > for
> >
Hi Bruno,
Your email did reach the mailing list, it's just looks like, unfortunately,
nobody can help you with this at the moment.
Try Cc'ing or directly emailing somebody who works on U-Boot for STM32
SoCs, I definitely saw some patches recently.
On Sun, Mar 5, 2017 at 11:21 PM, bruno schwander
Hi,
I just realized patch b3d2861eb20a ("spl: Remove overwrite of relocated malloc
limit") introduces breakage in my rk3188 uboot code (and should most likely
also affect the very similar other rockchip spl boards).
The boards call spl_init in their board_init_f functions because they need the
Hello,
On Fri, 23 Oct 2015 19:53:28 +0900
Minkyu Kang wrote:
> Dear Siarhei Siamashka,
>
> On 20/10/15 08:39, Siarhei Siamashka wrote:
> > ODROID-X uses a slightly older revision of the same base board
> > as the ODROID-X2. But the CPU module in ODROID-X uses an older
> > 1.4GHz revision of Exy
On Fri, 3 Mar 2017 15:29:35 -0700 (MST)
xiaojimmychen <807065...@qq.com> wrote:
> Hello everyone!
>
> I am working with my Tiny4412 board, and the u-boot version is U-Boot
> 2016.11. After burning the u-boot to sd card, and boot my board from it.
> There are some error ouput to the console. It se
On Tue, Mar 07, 2017 at 12:44:59AM +0200, Siarhei Siamashka wrote:
> Hi Tom,
>
> On Mon, 6 Mar 2017 13:50:10 -0500
> Tom Rini wrote:
>
> > Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
> > various reasons. We also have cases where we only build SPL in Thumb2 mode
On Mon, Mar 06, 2017 at 03:16:52AM +0200, Siarhei Siamashka wrote:
> Boards with OMAP3530 SoC fail to boot since commit bd2c4522c26d5
> ("ti: armv7: enable EXT support in SPL (using ti_armv7_common.h)")
> because it enabled the use of Thumb2 for the SPL.
>
> Experiments have shown that the deadlo
Hi Tom,
On Mon, 6 Mar 2017 13:50:10 -0500
Tom Rini wrote:
> Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
> various reasons. We also have cases where we only build SPL in Thumb2 mode
> due
> to size constraints and wish to build the rest of the system in ARM mod
The "chunks" in the "fastboot sparse image" are not aligned, resulting
in many "cached misaligned" messages from check_cache_range().
Implement a runtime flag to suppress this message, and use this flag
when processing the "fastboot sparse image".
Signed-off-by: Steve Rae
Reported-by: Gary Bisson
On Fri, Mar 3, 2017 at 9:27 AM, Gary Bisson wrote:
> Hi Steve,
>
> On Fri, Mar 3, 2017 at 12:03 AM, Steve Rae
> wrote:
> >
> > Hi Gary,
> >
> > On Thu, Mar 2, 2017 at 3:12 AM, Lukasz Majewski wrote:
> >>
> >> Hi,
> >>
> >> > Hi Fabio, Lukasz,
> >> >
> >> > On Wed, Feb 15, 2017 at 02:24:40PM -02
On Sun, Mar 5, 2017 at 8:36 AM, Nathan Rossi wrote:
> When the zynq_gem driver initializes the phy it sets the supported
> features that the phy can support and advertise. However instead of
> masking the supported features such that it limits the available
> features it sets the phy to have the e
On Mon, Mar 6, 2017 at 11:02 AM, York Sun wrote:
> Since the reserved RAM is tracked by gd->arch.resv_ram, calculation
> of MC memory blocks can be simplified. The MC RAM is guaranteed to be
> aligned by the reservation process.
>
> Signed-off-by: York Sun
> CC: Priyanka Jain
Seems reasonable.
On Tue, Feb 21, 2017 at 1:47 AM, Ashish Kumar wrote:
> Hello Joe,
>
> Please see inline.
>
> Regards
> Ashish
>
> -Original Message-
> From: Joe Hershberger [mailto:joe.hershber...@gmail.com]
> Sent: Thursday, February 16, 2017 5:22 AM
> To: Ashish Kumar
> Cc: u-boot
> Subject: Re: [U-Bo
This tool does not work with Python 3. Change the shebang to make sure the
script is run by a Python 2 interpreter.
Signed-off-by: Jörg Krause
---
tools/binman/binman.py | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tools/binman/binman.py b/tools/binman/binman.py
index e1cb
Commit 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from
board parameters") accidentally unset the DRAM_SPARSE flag, and
changed the physical map of the DRAM channels. Revive the original
behavior.
Fixes: 04cd4e7215d3 ("ARM: uniphier: remove DRAM base address from board
parameters")
Si
Hello Joe,
Could you please ack if there are no further queries.
Regards
Ashish
-Original Message-
From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Ashish Kumar
Sent: Tuesday, February 21, 2017 1:17 PM
To: Joe Hershberger
Cc: u-boot
Subject: Re: [U-Boot] [PATCH v2] driver
Today, we have cases where we wish to build all of U-Boot in Thumb2 mode for
various reasons. We also have cases where we only build SPL in Thumb2 mode due
to size constraints and wish to build the rest of the system in ARM mode. So
in this migration we introduce a new symbol as well, SPL_SYS_THU
This patch follows the break-before-make process when making changes
to MMU table. MMU is disabled before changing TTBR to avoid any
potential race condition.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4:
Revert the change of C bit in v3 patch.
Changes in v3:
Instead of fl
In early MMU table, DDR has to be mapped as device memory to avoid
speculative access. After DDR is initialized, it needs to be updated
to normal memory to allow code execution. To simplify the code,
dram_init() is moved into a common file as a weak function.
Signed-off-by: York Sun
---
Changes
Function mmu_change_region_attr() is added to change existing mapping
with updated PXN, UXN and memory type. This is a break-before-make
process during which the mapping becomes fault (invalid) before final
attributres are set.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
For ARMv8 Layerscape SoCs, secure memory and MC memorey are reserved
at the end of DDR. DDR is spit into two or three banks. This patch
reverts commit aabd7ddb and simplifies the calculation of reserved
memory, and moves the code into common SoC file. Secure memory is
carved out first. DDR bank siz
Early MMU improves performance especially on emulators. However, the
early MMU is left enabled after the first stage of SPL boot. Instead
of flushing D-cache and dealing with re-enabling MMU for the second
stage U-Boot, disabling it for SPL build simplifies the process. The
performance penalty is u
Use Kconfig option instead of config macro in header file.
Clean up existing usage.
Signed-off-by: York Sun
---
Changes in v5:
Rename RESV_RAM_TOP to RESV_RAM.
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
include/config
Since the reserved RAM is tracked by gd->arch.resv_ram, calculation
of MC memory blocks can be simplified. The MC RAM is guaranteed to be
aligned by the reservation process.
Signed-off-by: York Sun
CC: Priyanka Jain
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Use Kconfig option instead of config macro in header file.
Signed-off-by: York Sun
---
Changes in v5:
Rename RESV_RAM_TOP to RESV_RAM.
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 8
include/configs/ls2080a_common.h
Update mapping with actual DDR size. Non-existing memory should not
be mapped as "normal" memory to avoid speculative access.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 42 +++
Instead of adding all memory banks, add a hook so individual SoC/board
can has its own implementation.
Signed-off-by: York Sun
CC: Alexander Graf
Reviewed-by: Alexander Graf
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Add change to efi mapping
lib/efi_lo
Use gd->arch.resv_ram to track reserved memory allocation.
Signed-off-by: York Sun
---
Changes in v5:
Rename RESV_RAM_TOP to RESV_RAM in Kconfig
Revise "help" message and add comment to explain how RESV_RAM is used.
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu
On Mon, Mar 06, 2017 at 03:11:29PM +, Andre Przywara wrote:
> Hi,
>
> On 06/03/17 10:00, Maxime Ripard wrote:
> > On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote:
> >> Hi,
> >>
> >> On 03/03/17 09:22, Maxime Ripard wrote:
> >>> On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Z
Hi,
On 06/03/17 10:00, Maxime Ripard wrote:
> On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote:
>> Hi,
>>
>> On 03/03/17 09:22, Maxime Ripard wrote:
>>> On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote:
2017年3月1日 23:51于 Maxime Ripard 写道：
>
> Hi Andre,
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
Signed-off-by: Simon Glass
---
Changes in v4:
- Drop no use code comment by Marek.
Changes in v3:
- Drop use of
Currently nandecc returns zero even if underlaying
omap_nand_switch_ecc function fails. Fix that by
propagating error returned to command return value.
Signed-off-by: Ladislav Michl
---
Changes:
- v2: Add changelog text.
arch/arm/include/asm/arch-am33xx/sys_proto.h | 2 +-
arch/arm/include/as
Hi Simon,
On 12/04/2016 02:27 AM, Simon Glass wrote:
Hi Marek, Kever,
On 3 December 2016 at 06:15, Marek Vasut wrote:
On 12/03/2016 05:29 AM, Simon Glass wrote:
From: Kever Yang
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add i
Bind usb host and otg vbus to its source.
Signed-off-by: Kever Yang
---
arch/arm/dts/rk3036-sdk.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/dts/rk3036-sdk.dts b/arch/arm/dts/rk3036-sdk.dts
index bdc7b98..6754625 100644
--- a/arch/arm/dts/rk3036-sdk.dts
+++ b/arch/arm/dts/
Some board do not use the dwc2 internal VBUS_DRV signal, but
use a gpio pin to enable the 5.0V VBUS power, add interface to
enable the power in dwc2 driver.
Signed-off-by: Kever Yang
Signed-off-by: Simon Glass
---
Changes in v4:
- Drop no use code comment by Marek.
Changes in v3:
- Drop use of
On 16/02/2017 19:32, Maxime Ripard wrote:
> On Thu, Feb 16, 2017 at 11:46:42AM +0100, Florent Jacquet wrote:
>> This enables the support for the Allwinner A23 Evaluation Board (EVB),
>> that already had a device tree (from Linux) but no defconfig.
>>
>> This board has an AXP223 PMIC, some NAND, Aud
There is option which is not used:
CONFIG_ZBOOT_32
Remove it from default x86 config and from whitelist.
Signed-off-by: Andy Shevchenko
---
include/configs/x86-common.h | 1 -
scripts/config_whitelist.txt | 1 -
2 files changed, 2 deletions(-)
diff --git a/include/configs/x86-common.h
Hi Andre,
I have test this patch set on rk3399 with ATF support.
For patch 2~5, you can add:
Tested-by: Kever Yang
Thanks,
- Kever
On 03/01/2017 10:25 AM, Andre Przywara wrote:
This is an updated and slightly extended version of the SPL FIT loading
series I posted as an RFC some weeks ago
ARM64 is using 64bit address which address cell is 2 instead of 1,
update to support it when of-platdata enabled.
Signed-off-by: Kever Yang
---
drivers/core/regmap.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/drivers/core/regmap.c b/drivers/core/re
u-boot/2015-October/231061.html
Basically, a voltage regulator is not getting initialized because
a call to the board_usb_init() function was lost during the DM
conversion. You can try to compile U-Boot from my branch, it contains
the rebased fixes which I have been using all this time on my ODROID-X
board:
On Fri, Mar 03, 2017 at 09:55:25AM +, Andre Przywara wrote:
> Hi,
>
> On 03/03/17 09:22, Maxime Ripard wrote:
> > On Thu, Mar 02, 2017 at 12:03:20AM +0800, Icenowy Zheng wrote:
> >>
> >> 2017年3月1日 23:51于 Maxime Ripard 写道：
> >>>
> >>> Hi Andre,
> >>>
> >>> On Wed, Mar 01, 2017 at 02:25:26AM +0
On Mon, Feb 27, 2017 at 2:24 PM, Masahiro Yamada
wrote:
> DTC 1.4.2 or later checks DT unit-address without reg property and
> vice-versa, and generates lots of warnings. Fixing DT files will
> take for a while. Until then, let's turn off the check unless
> building with W=*.
>
> Introduce a new
Hi,
On Saturday 04 March 2017 10:39 PM, Tom Rini wrote:
> On Sat, Mar 04, 2017 at 06:17:30PM +0530, Vignesh R wrote:
>
>> SPI U-Boot image for K2 boards have now exceeded 512K partition
>> allocated to it and no longer fit the partitions defined in kernel DTS
>> file. Therefore, pass an updated M
Hi Tom
As kernel maintainer of STi machine (STMicroelectronics STiH407 family
SoC), i am currently adding STiH407 support on U-boot
(https://www.mail-archive.com/u-boot@lists.denx.de/msg239825.html).
I am wondering if i need to get a custodian git tree for this machine in
order to do pull-reque
Andre,
> On 06 Mar 2017, at 03:08, André Przywara wrote:
>
> On 01/03/17 21:19, Philipp Tomsich wrote:
>> Hi everyone,
>>
>> here's the the new version of CLK, RESET and PINCTRL drivers to
>> configure sunxi from the device-tree. This adds support for the
>> upstream CCU node (for reset and pi
Hi Simon,
On 02/17/2017 04:43 AM, Simon Glass wrote:
Hi Kever,
On 13 February 2017 at 01:28, Kever Yang wrote:
ARM64 is using 64bit address which address cell is 2 instead of 1,
update to support it when of-platdata enabled.
Signed-off-by: Kever Yang
---
drivers/core/regmap.c | 20 ++
Anyway I can ask this on the list ? My message is still awaiting moderation
or fell in the spam folder...
> Hi all,
>
> I am bringing up u-boot on a new custom board with STM32F429 cpu. To
start, I modified the stm32f429 discovery board files by adding the proper
gpio, size and address for the ext
In some cases this is absolutely required, so select this for some secure
features. This also requires migration of RSA_FREESCALE_EXP
Cc: Ruchika Gupta
Cc: Poonam Aggrwal
Cc: Naveen Burmi
Cc: Po Liu
Cc: Shengzhou Liu
Cc: Priyanka Jain
Cc: Sumit Garg
Cc: Shaohui Xie
Cc: Chunhe Lan
Cc: Fen
Hey Jagan,
FYI,
I used the wrong e-mail address, I think it is still listed in some of
the u-boot sources.
Olliver
On 01-03-17 15:06, Olliver Schinagl wrote:
Hey Maxime, Jagan,
On 01-03-17 14:00, Maxime Ripard wrote:
Hi Oliver,
On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl w
Hey Maxime, Jagan,
On 01-03-17 14:00, Maxime Ripard wrote:
Hi Oliver,
On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote:
Hi list,
When powering up an AXP209, the default value for LDO3 output is enabled. This
works fine. However if for whatever reason, LDO3 is disabled, for exa
Hey Marcus,
On 01-03-17 16:10, Marcus Weseloh wrote:
Hi Oliver,
2017-03-01 13:52 GMT+01:00 Olliver Schinagl mailto:oli...@schinagl.nl>>:
+#define AXP209_VRC_LDO3_EN BIT(3)
+#define AXP209_VRC_DCDC2_ENBIT(2)
+#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | A
Hey Maxime,
On 01-03-17 14:00, Maxime Ripard wrote:
Hi Oliver,
On Wed, Mar 01, 2017 at 01:52:16PM +0100, Olliver Schinagl wrote:
Hi list,
When powering up an AXP209, the default value for LDO3 output is enabled. This
works fine. However if for whatever reason, LDO3 is disabled, for example by
Hi all,
I am bringing up u-boot on a new custom board with STM32F429 cpu. To start,
I modified the stm32f429 discovery board files by adding the proper gpio,
size and address for the external DRAM, also the dram timings and USART
gpio pins used
I use the "bare" gcc 5.4 toolchain from ARM from
http
A recent debug revealed MMU for DDR shouldn't be enabled before
DDR is initialized. Otherwise, a "normal memory" mapping may cause
speculative access which may hang the system if accessing to DDR
is not allowed at time. For Layerscape platforms, we have early
MMU setup to speed up execution on emu
On Wed, Feb 8, 2017 at 5:35 PM, Yung-Ching LIN wrote:
> On Wed, Feb 8, 2017 at 10:47 AM, Joe Hershberger
> wrote:
>> On Wed, Feb 8, 2017 at 12:26 AM, Sekhar Nori wrote:
>>> On Wednesday 08 February 2017 12:36 AM, Yung-Ching LIN wrote:
On Tue, Feb 7, 2017 at 12:50 AM, Sekhar Nori wrote:
>>>
Hello everyone!
I am working with my Tiny4412 board, and the u-boot version is U-Boot
2016.11. After burning the u-boot to sd card, and boot my board from it.
There are some error ouput to the console. It seems like that my sd card
doesn't initialize completely.
I have enabled the MMC Debug conf
Hi Oliver,
2017-03-01 13:52 GMT+01:00 Olliver Schinagl :
> +#define AXP209_VRC_LDO3_EN BIT(3)
> +#define AXP209_VRC_DCDC2_ENBIT(2)
> +#define AXP209_VRC_LDO3_800uV_uS (BIT(1) | AXP209_VRC_LDO3_EN)
> +#define AXP209_VRC_LDO3_1600uV_uS AXP209_VRC_LDO3_EN
>
Does t
DT binding documentation for atmel HLCDC driver.
Signed-off-by: Songjun Wu
---
Changes in v2: None
doc/device-tree-bindings/video/atme-hlcdc.txt | 38 +++
1 file changed, 38 insertions(+)
create mode 100644 doc/device-tree-bindings/video/atme-hlcdc.txt
diff --git a/do
Add driver-model support to this driver.
Signed-off-by: Songjun Wu
---
Changes in v2:
- Due to the peripheral clock driver improvement, remove
the unneccessary clock calling.
board/atmel/at91sam9n12ek/at91sam9n12ek.c | 2 +
board/atmel/at91sam9x5ek/at91sam9x5ek.c | 2 +
boa
The i2c driver includes two parts.
1) Driver code to implement the HLCD function.
2) Device tree binding documentation, it describes how
to add the HLCD in device tree.
Changes in v2:
- Due to the peripheral clock driver improvement, remove
the unneccessary clock calling.
Songjun Wu (2):
a
OK York, will send new patch..
> -Original Message-
> From: york sun
> Sent: Tuesday, February 28, 2017 9:56 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Scott Wood ; Leo Li
> ; Sriram Dash ; Rajesh Bhagat
>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-0090
Hello,
Here is a list of things I have tried: The raw zImage (which is compressed
with XZ), various addresses from indeed load address 0x2300, entry
at 0x23008000
(and the same), I've tried setting the FTD address since it sets itself
neatly at 0x22f and change, which will probably get itself
Hello,
Still for some reason - there is an issue with booting from the FIT. With
a version of Uboot without the FIT related CONFIGs enabled; everything
works.
Here is me taking my zImage and converting it to a u-image ( I am not sure
on the addresses)
mkimage -A arm -O linux -C none -T kernel -
Hi Markus,
Hi Maria,
On Mon, 2017-02-20 at 12:33 +0100, Maria Sepulveda wrote:
The reason to store the public key on an external device is to verify
that it is our hardware.
Do you want to verify it is your hardware or do you want to verify the Software
is the one you designated to run on th
> -Original Message-
> From: york sun
> Sent: Friday, February 24, 2017 10:31 PM
> To: Suresh Gupta
> Cc: u-boot@lists.denx.de; Scott Wood ; Leo Li
> ; Sriram Dash ; Rajesh Bhagat
>
> Subject: Re: [PATCH v3 4/8] armv8: Add workaround for USB erratum A-009007
>
> On 02/23/2017 11:19 PM,
Looks like far more progress:
#> setenv my_bootcount 0; bootm 0xD0084000
Initial value for argc=3
Final value for argc=3
## Current stack ends at 0x23f11db8 * kernel: cmdline image address =
0xd0084000
Reading image header from dataflash address d0084000 to RAM address
2200
FIT/FDT form
Okay - it seems, after working my way through a bunch of the documentation
and examples in /doc/uImage.FIT - I noticed a discrepancy
/dts-v1/;
/{
description = "Configuration to load a Basic Kernel";
#address-cells = <1>;
images {
linux_kernel@1 {
description = "Linux zImage";
data = /incbin/("zIm
Add support for the Broadcom Northstar2 SoC and SVK (bcm958712k). The
BCM5871X is a series of quad-core 64-bit 2GHz ARMv8 Cortex-A57
processors targeting a broad range of networking applications.
Signed-off-by: Jon Mason
---
arch/arm/Kconfig | 9 ++
board/broadcom/bcm9
On Mon, Mar 06, 2017 at 04:05:07PM +0800, Chen-Yu Tsai wrote:
> The R40 is the successor to the A20. It is a hybrid of the A20, A33
> and the H3.
>
> The R40's PIO controller is compatible with the A20,
> Reuse the A20 UART and I2C muxing code by adding the R40's macro.
>
> The display pipeline i
On Mon, Mar 06, 2017 at 04:05:06PM +0800, Chen-Yu Tsai wrote:
> Currently we have some lines in board/sunxi/Kconfig that are very long.
> These line either provide default values for a set of SoCs, or limit
> some option to a subset of sunxi SoCs.
>
> Fortunately Kconfig makes it easy to split the
On Sab, 2017-02-25 at 22:41 +0100, Marek Vasut wrote:
> On 02/22/2017 10:47 AM, Ley Foon Tan wrote:
> >
> > Add pinmux support for Arria 10.
> >
> > Signed-off-by: Tien Fong Chee
> > Signed-off-by: Ley Foon Tan
> > ---
> > arch/arm/mach-socfpga/Makefile | 1 +
> > arch/arm/mach-s
The R40 seems to have a variant of the memory controller found in
the H3 and A64 SoCs. Adapt the code for use on the R40. The changes
are based on released DRAM code and comparing register dumps from
boot0.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/
The R40 has the CPUCFG block at the same address as the A20.
Fix it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/include/asm/arch-sunxi/cpu_sun4i.h | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun4i.h
b/arch/
The R40 SoC uses the AXP221s in I2C mode to supply power.
Some regulator's common usages have changed, and also the recommended
voltage for existing usages have changed. Update the defaults to match.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
arch/arm/mach-sunxi/pmic_bus.c | 7 ++
Now that we can do DRAM initialization for the R40, we can enable
SPL support for it.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/Kconfig | 1 +
1 file changed, 1 insertion(+)
diff --git a/board/sunxi/Kconfig b/board/sunxi/Kconfig
index be9f6922fa2f..333872006918 100644
The PIO is generally compatible with the A20, except that it routes the
full 8 bits and eMMC reset pins for mmc2.
Signed-off-by: Chen-Yu Tsai
Acked-by: Maxime Ripard
---
board/sunxi/board.c | 17 +++--
1 file changed, 15 insertions(+), 2 deletions(-)
diff --git a/board/sunxi/board.
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