Hi Tom,
On 09/06/2016 07:15 AM, Tom Rini wrote:
> On Tue, Sep 06, 2016 at 07:00:56AM -0700, Eric Nelson wrote:
>> On 09/06/2016 06:40 AM, Tom Rini wrote:
>>> On Fri, Sep 02, 2016 at 10:53:58PM +0200, Petr Kulhavy wrote:
>>>
>>> Would it be possible to implement having the next stage also be sen
On Sat, Sep 10, 2016 at 1:48 PM, Marek Vasut wrote:
> On 09/10/2016 07:24 PM, Joe Hershberger wrote:
>> Hi Marek,
>>
>> On Sat, Sep 10, 2016 at 11:51 AM, Marek Vasut wrote:
>>> On 09/10/2016 06:28 PM, Joe Hershberger wrote:
Hi Marek,
On Sat, Sep 10, 2016 at 5:01 AM, Marek Vasut wr
form data
> from include/generated/dt-structs.h which is generated according to dts
> file.
> Please try above change.
With this change, it builds, but it hangs at boot:
U-Boot SPL 2016.09-rc2+dfsg1-2~20160910~6 (Sep 10 2016 - 18:51:28)
Trying to boot from MMC1
U-Boot 2016.09
On 09/10/2016 07:24 PM, Joe Hershberger wrote:
> Hi Marek,
>
> On Sat, Sep 10, 2016 at 11:51 AM, Marek Vasut wrote:
>> On 09/10/2016 06:28 PM, Joe Hershberger wrote:
>>> Hi Marek,
>>>
>>> On Sat, Sep 10, 2016 at 5:01 AM, Marek Vasut wrote:
On 09/10/2016 03:34 AM, Marcel Ziswiler wrote:
Hi Marek,
On Sat, Sep 10, 2016 at 11:51 AM, Marek Vasut wrote:
> On 09/10/2016 06:28 PM, Joe Hershberger wrote:
>> Hi Marek,
>>
>> On Sat, Sep 10, 2016 at 5:01 AM, Marek Vasut wrote:
>>> On 09/10/2016 03:34 AM, Marcel Ziswiler wrote:
On Sat, 2016-09-10 at 02:18 +0200, Marcel Ziswiler wrote:
On 10/09/16 17:55, Daniel Schwierzeck wrote:
> Am 09.09.2016 um 15:44 schrieb Paul Burton:
>> This patch adds support for initialising & maintaining L2 caches on MIPS
>> systems. The L2 cache configuration may be advertised through either
>> coprocessor 0 or the MIPS Coherence Manager depending upo
Am 09.09.2016 um 15:44 schrieb Paul Burton:
> This patch adds support for initialising & maintaining L2 caches on MIPS
> systems. The L2 cache configuration may be advertised through either
> coprocessor 0 or the MIPS Coherence Manager depending upon the system,
> and support for both is included
On 09/10/2016 03:54 AM, Marcel Ziswiler wrote:
> From: Alban Bedel
>
> Commit 147271209a9d ("net: asix: fix operation without eeprom")
> added a special handling for ASIX 88772B that enable another
> type of header. This break the driver in DM mode as the extra handling
> needed in the receive pa
On 09/10/2016 06:28 PM, Joe Hershberger wrote:
> Hi Marek,
>
> On Sat, Sep 10, 2016 at 5:01 AM, Marek Vasut wrote:
>> On 09/10/2016 03:34 AM, Marcel Ziswiler wrote:
>>> On Sat, 2016-09-10 at 02:18 +0200, Marcel Ziswiler wrote:
On Sat, 2016-09-10 at 01:23 +0200, Marek Vasut wrote:
>
>
On 09/10/2016 04:20 AM, Marcel Ziswiler wrote:
> Since commit aa7a648747d8c704a9a81c9e493d386930724e9d
> ("net: Stop including NFS overhead in defragment max") the following
> has been reproducibly observed while trying to transfer data over TFTP:
>
> Load address: 0x80408000
> Loading: EHCI timed
On Fri, Sep 9, 2016 at 8:54 PM, Marcel Ziswiler
wrote:
> From: Alban Bedel
>
> Commit 147271209a9d ("net: asix: fix operation without eeprom")
> added a special handling for ASIX 88772B that enable another
> type of header. This break the driver in DM mode as the extra handling
> needed in the re
Am 09.09.2016 um 15:44 schrieb Paul Burton:
> Enable use of the instruction cache immediately after it has been
> initialised. This will only take effect if U-Boot was linked to run from
> kseg0 rather than kseg1, but when this is the case the data cache
> initialisation code will run cached & th
Hi Marcel,
On Fri, Sep 9, 2016 at 9:20 PM, Marcel Ziswiler
wrote:
> Since commit aa7a648747d8c704a9a81c9e493d386930724e9d
> ("net: Stop including NFS overhead in defragment max") the following
> has been reproducibly observed while trying to transfer data over TFTP:
>
> Load address: 0x80408000
>
Hi Marek,
On Sat, Sep 10, 2016 at 5:01 AM, Marek Vasut wrote:
> On 09/10/2016 03:34 AM, Marcel Ziswiler wrote:
>> On Sat, 2016-09-10 at 02:18 +0200, Marcel Ziswiler wrote:
>>> On Sat, 2016-09-10 at 01:23 +0200, Marek Vasut wrote:
On 09/10/2016 01:13 AM, Marcel Ziswiler wrote:
>
On Sat, 2016-09-10 at 01:23 +0200, Marek Vasut wrote:
> On 09/10/2016 01:13 AM, Marcel Ziswiler wrote:
> >
> > On Sat, 2016-09-10 at 01:04 +0200, Marek Vasut wrote:
> > >
> > > On 09/09/2016 11:06 PM, Marcel Ziswiler wrote:
> > > >
> > > >
> > > > On Fri, 2016-09-09 at 13:57 -0500, Joe Hershber
hi Vagrant,
On 2016年09月09日 03:28, Vagrant Cascadian wrote:
On 2016-09-08, Kever Yang wrote:
The rk3288 spl size is very close to 32KB while the rk3288 bootrom
has the limitation of maximum size of SPL is 32KB. After apply this
patch, the SPL size will exceed 32KB if we do not enable macro
CONF
On 10/09/16 13:17, Daniel Schwierzeck wrote:
>
>
> Am 08.09.2016 um 08:47 schrieb Paul Burton:
>> This patch introduces support for building U-Boot to run on the MIPS
>> Boston development board. This is a board built around an FPGA & an
>> Intel EG20T Platform Controller Hub, used largely as par
Am 08.09.2016 um 08:47 schrieb Paul Burton:
> This patch introduces support for building U-Boot to run on the MIPS
> Boston development board. This is a board built around an FPGA & an
> Intel EG20T Platform Controller Hub, used largely as part of the
> development of new CPUs and their software
On 09/10/2016 03:34 AM, Marcel Ziswiler wrote:
> On Sat, 2016-09-10 at 02:18 +0200, Marcel Ziswiler wrote:
>> On Sat, 2016-09-10 at 01:23 +0200, Marek Vasut wrote:
>>>
>>> On 09/10/2016 01:13 AM, Marcel Ziswiler wrote:
On Sat, 2016-09-10 at 01:04 +0200, Marek Vasut wrote:
>
>
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