Hi Simon,
On Wed, 2016-06-15 at 18:39 -0600, Simon Glass wrote:
> Hi Alexey,
>
> On 14 June 2016 at 01:15, Alexey Brodkin wrote:
> >
> > Hi Heiko,
> >
> > On Tue, 2016-06-14 at 07:07 +0200, Heiko Schocher wrote:
> > >
> > > Hello Sjoerd,
> > >
> > > as I just write a tbot testcase, which che
Here is that patch again. Rebased, multiline comments fixed, some
whitespace trimmed. One header file with non-SPDX license is not
changed because the entire file has been stolen verbatim with no
changes at all. No other changes so far... This is against today's
git tree.
Signed-off-by: Sergey Ku
The DRAM PHY on PH1-LD20 is able to calibrate PHY parameters
periodically. This improves PHY adjustment against the voltage and
temperature deviation. Instead, it requires 64 byte scratch memory
in each DRAM channel for the dynamic training. The memory regions
must be reserved in DT before jumpi
On Tuesday 14 June 2016 04:55 AM, Andreas Dannenberg wrote:
> Enable FIT support for AM57xx platforms using the high-security (HS)
> device variant.
>
> Signed-off-by: Andreas Dannenberg
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
> ---
>
> This patch is based on the the patch se
On Saturday 11 June 2016 02:02 AM, Madan Srinivas wrote:
> Adds missing NAND option to CONFIG_SYS_EXTRA_OPTIONS for
> AM437x HS EVMs. This syncs up the config options between
> GP and HS EVMs.
>
> Signed-off-by: Madan Srinivas
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
> ---
> co
On Saturday 11 June 2016 02:02 AM, Madan Srinivas wrote:
> Adds FIT support to the SPL and u-boot for AM437x HS devices.
>
> Signed-off-by: Madan Srinivas
Reviewed-by: Lokesh Vutla
Thanks and regards,
Lokesh
> ---
>
> Changes in v2:
> configs/am437x_hs_evm_defconfig:
> Removes NAND t
> -Original Message-
> From: Marek Vasut [mailto:ma...@denx.de]
> Sent: Thursday, June 16, 2016 3:33 AM
> To: Rajesh Bhagat ; u-boot@lists.denx.de
> Cc: s...@chromium.org; york sun ; Sriram Dash
>
> Subject: Re: [PATCH v6 1/2] common: usb_storage: Make common function for
> usb_stor_read
Add script for retrieving the kernel via TFTP and mounting the
rootfs via NFS.
Signed-off-by: Diego Dorta
---
include/configs/pico-imx6ul.h | 26 +-
1 file changed, 25 insertions(+), 1 deletion(-)
diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h
> On Jun 15, 2016, at 4:23 AM, Pantelis Antoniou
> wrote:
> The correct way is to get cracking on the machine readable yaml based bindings
> and enforce it through there.
Machine readable bindings with enforcement would be enabling technology to solve
a lot of different problems (both technica
Hi Nikita,
On 06/15/2016 05:15 PM, Nikita Kiryanov wrote:
> Hi CHristopher,
>
> On Wed, Jun 08, 2016 at 09:02:36PM +0200, Christopher Spinrath wrote:
>> Old revisions of Utilite (based on cmfx6) do not have a dedicated
>> card detect pin. But the card is removable by the user and card
>> detectio
Hi,
On 06/14/2016 04:24 PM, Tom Rini wrote:
With updated moveconfig.py and an better default, re-generate
the migration of BOOTDELAY to the defconfig.
Signed-off-by: Tom Rini
Series looks good to me, thank you for fixing this:
Reviewed-by: Hans de Goede
Regards,
Hans
---
configs/A10
Hi Wenyou,
On 15 June 2016 at 19:08, Yang, Wenyou wrote:
>
>
>> -Original Message-
>> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
>> Sent: 2016年6月10日 8:34
>> To: Yang, Wenyou
>> Cc: U-Boot Mailing List ; Andreas Bießmann
>>
>> Subject: Re: [PATCH v2 1/2] clk:
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: 2016年6月10日 8:34
> To: Yang, Wenyou
> Cc: U-Boot Mailing List ; Andreas Bießmann
>
> Subject: Re: [PATCH v2 1/2] clk: clk-uclass: Add post binding for CLK uclass
>
> Hi Wenyou,
>
> On
On 14 June 2016 at 02:02, Bin Meng wrote:
> At present should_load_oprom() calls board_should_run_oprom() to
> determine whether oprom should be loaded. But sometimes we just
> want to load oprom without running. Make them independent.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pci/pci_rom.c
On 15 June 2016 at 16:00, Andreas Dannenberg wrote:
> The comments in the source file are riddled with spelling mistakes. Be
> a good citizen and take a stab at cleaning up some of the more obvious
> ones.
>
> Signed-off-by: Andreas Dannenberg
> ---
> common/image-fit.c | 30 +++-
On 14 June 2016 at 02:02, Bin Meng wrote:
> For consistency with board_should_run_oprom(), do the same to
> should_load_oprom(). Board support codes can provide this one
> to override the default weak one.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pci/pci_rom.c | 4 ++--
> 1 file changed, 2
Hi Michael,
On 13 June 2016 at 13:53, Michael Trimarchi
wrote:
>
> We can support dts load from the second address of android image.
> This let us to boot board (aka freescale)
>
> Signed-off-by: Michael Trimarchi
> ---
> Changes:
> v2 -> v3: Move variable fdt_data and fdt_len in main bo
On 14 June 2016 at 02:02, Bin Meng wrote:
> This option is defined at nowhere. Remove it.
>
> Signed-off-by: Bin Meng
> ---
>
> drivers/pci/pci_rom.c | 2 --
> 1 file changed, 2 deletions(-)
Reviewed-by: Simon Glass
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Hi Maxime,
On 13 June 2016 at 03:28, Maxime Ripard
wrote:
> Hi David,
>
> On Sat, Jun 11, 2016 at 08:30:35PM +1000, David Gibson wrote:
>> On Fri, Jun 10, 2016 at 05:03:36PM +0300, Pantelis Antoniou wrote:
>> > Hi Maxime,
>> >
>> > > On May 27, 2016, at 12:13 , Maxime Ripard
>> > > wrote:
>> >
Hi Alexey,
On 14 June 2016 at 01:15, Alexey Brodkin wrote:
> Hi Heiko,
>
> On Tue, 2016-06-14 at 07:07 +0200, Heiko Schocher wrote:
>> Hello Sjoerd,
>>
>> as I just write a tbot testcase, which checks patches, which moves
>> a config option to Kconfig, I tested also to compile arc boards, and
>>
On 06/15/2016 12:06 PM, Christian Didriksson wrote:
> Trying again.
Hi!
> I have reverted back to a vanilla u-boot-2016.05, added the
> not-enter-quad-mode patch
What's this patch ? Can you share it ?
> and changed the SPI address where the SPL should load the u-boot from
Can you share this c
On 06/15/2016 09:00 AM, Rajesh Bhagat wrote:
> Performs code cleanup by making common function for usb_stor_read/
> usb_stor_write. Currently only difference in these fucntions is call
> to usb_read_10/usb_write_10 scsi commands.
>
> Signed-off-by: Rajesh Bhagat
> ---
> Changes in v6:
> - Remove
On 06/15/2016 07:15 AM, Peng Fan wrote:
> If the usb controller is not running, no need to shutdown it,
> otherwise `usb stop` complains about:
> "EHCI failed to shut down host controller".
>
> To i.MX7D SDB, there are two usb ports, one Host, one OTG.
> If we only plug one udisk to the Host port
The comments in the source file are riddled with spelling mistakes. Be
a good citizen and take a stab at cleaning up some of the more obvious
ones.
Signed-off-by: Andreas Dannenberg
---
common/image-fit.c | 30 +++---
1 file changed, 15 insertions(+), 15 deletions(-)
dif
On Wed, 15 Jun 2016, Stefano Babic wrote:
Hi,
Hi Sergey,
On 14/06/2016 20:32, Sergey Kubushyn wrote:
Here is the initial support for writing i.MX6 NAND U-Boot into NAND
with all FCB and DBBT stuff as required.
This is a very interesting feature missing in U-Boot. Up now we are
constrained
This is an RFC for a method that uses a "weak" post-process function call
that's injected into the SPL FIT loading process after each blob has been
extracted (U-Boot firmware, selected DTB) which is populated with a platform
specific function. In case of TI high-security (HS) device variants a ROM
From: Daniel Allred
Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention.
Signed-off-by: Daniel Allred
Signed-off-by: Andreas Dan
From: Daniel Allred
The next stage boot loader image and the selected FDT can be
post-processed by board/platform/device-specific code, which can include
modifying the size and altering the starting source address before
copying these binary blobs to their final desitination. This might be
desire
From: Daniel Allred
Adds commands so that when a secure device is in use and the SPL is
built to load a FIT image (with combined u-boot binary and various
DTBs), these components that get fed into the FIT are all processed to
be signed/encrypted/etc. as per the operations performed by the
secure-
From: Daniel Allred
Adds an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible devices.
Signed-off-by: Daniel Allred
Signed-off-by: Andreas Dannenberg
---
arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 47 ++
arch/arm/include/asm/omap_co
From: Madan Srinivas
Adds an API that verifies a signature attached to an image (binary
blob). This API is basically a entry to a secure ROM service provided by
the device and accessed via an SMC call, using a particular calling
convention. This API is common across AM3x HS and AM4x HS devices.
From: Daniel Allred
Adds missing flush_dcache_range and invalidate_dcache_range dummy
(empty) placeholder functions to the #else portion of the #ifndef
CONFIG_SYS_DCACHE_OFF, where full implementations of these functions
are defined.
Signed-off-by: Daniel Allred
Signed-off-by: Andreas Dannenber
From: Daniel Allred
Adds a generic C-callable API for making secure ROM calls on OMAP and
OMAP-compatible devices. This API provides the important function of
flushing the ROM call arguments to memory from the cache, so that the
secure world will have a coherent view of those arguments. Then is
s
From: Madan Srinivas
Adds a board specific FIT image post processing function when u-boot is
compiled for the high-secure (HS) device variant.
Signed-off-by: Madan Srinivas
Signed-off-by: Andreas Dannenberg
---
board/ti/am43xx/board.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a
From: Daniel Allred
Adds a board specific FIT image post processing function for when
CONFIG_SECURE_BOOT is defined. Also update the omap common config
header to enable CONFIG_SECURE_BOOT always for secure TI devices
(CONFIG_TI_SECURE_DEVICE is defined).
Signed-off-by: Daniel Allred
Signed-off
Hi,
On 15-06-16 21:09, Boris Brezillon wrote:
Hello,
This patch series is adding the normal sunxi NAND controller driver to
u-boot.
It's based on the Linux driver, with a few adaptions to make it work
in Linux.
Hans, Scoot, this series contains 2 new patches to support the NAND
flash we have
We need some macros to manipulate the NAND controller clock.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-sunxi/clock_sun4i.h
b/arch/arm/include/asm/ar
On Mon, 6 Jun 2016 10:16:55 +0200
Boris Brezillon wrote:
> Hello,
>
> This patch series aims at adding support for NAND auto-detection to
> the sunxi SPL NAND driver.
>
> As explained in patch 7, this auto-detection is nothing more than a
> dumb "trial and error" logic, but it allows one to us
On some sunxi boards we have NANDs exposing 1664 OOB bytes per page.
Define the CONFIG_SYS_NAND_MAX_ECCPOS value accordingly.
Signed-off-by: Boris Brezillon
---
include/configs/sunxi-common.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/configs/sunxi-common.h b/include/configs/sun
Enable the NAND controller in the sun5i-r8-chip.dts.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
arch/arm/dts/sun5i-a10s.dtsi | 14 ++
arch/arm/dts/sun5i-a13-olinuxino.dts | 15 +++
arch/arm/dts/sun5i-r8-chip.dts | 15 +++
3 files
Some NANDs are now exposing 1664 OOB bytes per page. Adjust the
NAND_MAX_OOBSIZE value accordingly.
Signed-off-by: Boris Brezillon
---
include/linux/mtd/nand.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/linux/mtd/nand.h b/include/linux/mtd/nand.h
index 29aae43..8
Add a full-id entry for the H27QCG8T2E5R‐BCF NAND.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
drivers/mtd/nand/nand_ids.c | 4
1 file changed, 4 insertions(+)
diff --git a/drivers/mtd/nand/nand_ids.c b/drivers/mtd/nand/nand_ids.c
index 561d2cd..ce0a14e 100644
--- a/drivers
From: Brian Norris
These are already-documented common bindings for NAND chips. Let's
handle them in nand_base.
If NAND controller drivers need to act on this data before bringing up
the NAND chip (e.g., fill out ECC callback functions, change HW modes,
etc.), then they can do so between calling
Hello,
This patch series is adding the normal sunxi NAND controller driver to
u-boot.
It's based on the Linux driver, with a few adaptions to make it work
in Linux.
Hans, Scoot, this series contains 2 new patches to support the NAND
flash we have on the CHIP. The patches simply increase MAX_OOB_
From: Maxime Ripard
Add the NAND controller definition to sun5i.dtsi.
Signed-off-by: Maxime Ripard
Signed-off-by: Boris Brezillon
---
arch/arm/dts/sun5i.dtsi | 49 +
1 file changed, 49 insertions(+)
diff --git a/arch/arm/dts/sun5i.dtsi b/arch/a
We already have an SPL driver for the sunxi NAND controller, now add
the normal/standard one.
The source has been copied from Linux 4.6 with a few changes to make
it work in u-boot.
Signed-off-by: Boris Brezillon
Acked-by: Hans de Goede
---
board/sunxi/board.c|5 +-
drivers/mtd
Some drivers are still directly accessing the chip->mtd field. Patch
them to use nand_to_mtd() instead.
Signed-off-by: Boris Brezillon
---
doc/README.nand | 2 +-
drivers/mtd/nand/am335x_spl_bch.c | 2 +-
drivers/mtd/nand/atmel_nand.c | 2 +-
drivers/mtd/nand/lpc32xx_
On Wed, 15 Jun 2016 12:39:50 -0500
Scott Wood wrote:
> On Wed, 2016-06-15 at 10:07 +0200, Boris Brezillon wrote:
> > On Wed, 15 Jun 2016 09:59:15 +0200
> > Boris Brezillon wrote:
> >
> > > Hi Scott,
> > >
> > > On Thu, 09 Jun 2016 21:07:00 -0500
> > > Scott Wood wrote:
> > >
> > > > On M
On Wed, 2016-06-15 at 10:07 +0200, Boris Brezillon wrote:
> On Wed, 15 Jun 2016 09:59:15 +0200
> Boris Brezillon wrote:
>
> > Hi Scott,
> >
> > On Thu, 09 Jun 2016 21:07:00 -0500
> > Scott Wood wrote:
> >
> > > On Mon, 2016-06-06 at 18:02 +0200, Boris Brezillon wrote:
> > > > On Mon, 30 May
On Wed, Jun 15, 2016 at 12:48 PM, Vanessa Maegima
wrote:
> Add a README file to help users to install U-boot binary into the eMMC.
>
> Signed-off-by: Vanessa Maegima
Reviewed-by: Fabio Estevam
___
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http://lists.
On Wed, Jun 15, 2016 at 12:48 PM, Vanessa Maegima
wrote:
> DFU is a convenient way to program U-boot binary into the eMMC.
>
> Add support for it.
>
> Signed-off-by: Vanessa Maegima
Reviewed-by: Fabio Estevam
___
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U-Boot@lists.denx.
DFU is a convenient way to program U-boot binary into the eMMC.
Add support for it.
Signed-off-by: Vanessa Maegima
---
configs/pico-imx6ul_defconfig | 8
include/configs/pico-imx6ul.h | 8 +++-
2 files changed, 15 insertions(+), 1 deletion(-)
diff --git a/configs/pico-imx6ul_defco
Add a README file to help users to install U-boot binary into the eMMC.
Signed-off-by: Vanessa Maegima
---
board/technexion/pico-imx6ul/README | 57 +
1 file changed, 57 insertions(+)
create mode 100644 board/technexion/pico-imx6ul/README
diff --git a/board/
Hello Peng,
Am 15.06.2016 um 08:15 schrieb Peng Fan:
Add CONFIG_{SD|NOR|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries.
SoCs supports loading U-Boot from different medias to DRAM, such as
i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
and etc. For i.MX, imximage will
Hi CHristopher,
On Wed, Jun 08, 2016 at 09:02:36PM +0200, Christopher Spinrath wrote:
> Old revisions of Utilite (based on cmfx6) do not have a dedicated
> card detect pin. But the card is removable by the user and card
> detection can be realized with polling (e.g. supported by Linux).
>
> Add t
Hi Tim,
On 15/06/2016 15:40, Tim Harvey wrote:
> On Tue, May 24, 2016 at 11:03 AM, Tim Harvey wrote:
>> This series represents a large chunk of patches in my queue for Gateworks
>> Ventana boards based on the IMX6 Soc's.
>>
>> Tim Harvey (18):
>> imx: ventana: config: add env vars for disk and
Hi Peng,
On Wed, Jun 15, 2016 at 1:15 AM, Peng Fan wrote:
> Add CONFIG_{SD|NOR|NAND|ONENAND|SPI|QSPI|SATA}_BOOT kconfig entries.
>
> SoCs supports loading U-Boot from different medias to DRAM, such as
> i.MX6/7 supports loading U-Boot to DRAM from sd/emmc/nand/qspi/spi/sata
> and etc. For i.MX, i
Add support for Advantech SOM-DB5800 with the SOM-6867 installed.
This is very similar to conga-qeval20-qa3-e3845 in that there is a
reference carrier board (SOM-DB5800) with a Baytrail based SoM (SOM-6867)
installed.
Currently supported:
- 2x UART (From ITE EC on SOM-6867) routed to COM3/4 conne
Hi,
On 16 May 2016 at 12:51, Tom Rini wrote:
> Hey all,
>
> Due to some odds and ends, I ended up taking in some code a bit close to
> the original release date, so I ended up just pushing things out a week.
> I think moving forward, I really should say that in public, sorry. But
> things are li
On Wed, Jun 15, 2016 at 10:14:48PM +0900, Masahiro Yamada wrote:
> Hi.
>
> 2016-06-15 13:40 GMT+09:00 Wolfgang Denk :
> > Dear Tom Rini,
> >
> > In message <1465914280-5420-2-git-send-email-tr...@konsulko.com> you wrote:
> >> With updated moveconfig.py and an better default, re-generate
> >> the m
On Wed, Jun 15, 2016 at 9:09 AM, Bin Meng wrote:
> Hi George,
>
> On Wed, Jun 15, 2016 at 9:57 PM, George McCollister
> wrote:
>> On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
>>> If global NVS says internal UART is not enabled, hide it in the ASL
>>> code so that OS won't see it.
>>>
>>> Sig
Hi George,
On Wed, Jun 15, 2016 at 9:57 PM, George McCollister
wrote:
> On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
>> If global NVS says internal UART is not enabled, hide it in the ASL
>> code so that OS won't see it.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> arch/x86/include/asm/ar
On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
> If global NVS says internal UART is not enabled, hide it in the ASL
> code so that OS won't see it.
>
> Signed-off-by: Bin Meng
>
> ---
>
> arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 19 ---
> 1 file changed, 8 insertions(
On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
> Now that platform-specific ACPI global NVS is added, pack it into
> ACPI table and get its address fixed up.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/include/asm/acpi_table.h | 4
> .../x86/include/asm/arch-baytrail
On Wed, Jun 15, 2016 at 3:33 AM, Bin Meng wrote:
> This introduces baytrail-specific ACPI global NVS structure, defined in
> both C header file and ASL file.
>
> Signed-off-by: Bin Meng
> ---
>
> arch/x86/cpu/baytrail/acpi.c | 26
> ++
> .../include/asm
On Tue, May 24, 2016 at 11:03 AM, Tim Harvey wrote:
> This series represents a large chunk of patches in my queue for Gateworks
> Ventana boards based on the IMX6 Soc's.
>
> Tim Harvey (18):
> imx: ventana: config: add env vars for disk and part
> imx: ventana: config: add fixfdt script to app
Hi.
2016-06-15 13:40 GMT+09:00 Wolfgang Denk :
> Dear Tom Rini,
>
> In message <1465914280-5420-2-git-send-email-tr...@konsulko.com> you wrote:
>> With updated moveconfig.py and an better default, re-generate
>> the migration of BOOTDELAY to the defconfig.
>
> There are a number of changes that ar
On Wed, Jun 15, 2016 at 8:15 PM, Stefan Roese wrote:
> This patch adds support to enable and use the internal BayTrail UART
> instead of the one integrated in the Super IO Winbond chip. For this,
> a 2nd defconfig file is added.
>
> This is useful for tests done for the congatec SoM used on basebo
This patch adds support to enable and use the internal BayTrail UART
instead of the one integrated in the Super IO Winbond chip. For this,
a 2nd defconfig file is added.
This is useful for tests done for the congatec SoM used on baseboards
without such a Super IO chip.
Signed-off-by: Stefan Roese
On 15.06.2016 06:33, Bin Meng wrote:
There are quite a number of BayTrail boards that uses an external
SuperIO chipset to provide the legacy UART. For such cases, it's
better to have a Kconfig option to enable the internal UART.
So far BayleyBay and MinnowMax boards are using internal UART as
th
On 15.06.2016 06:33, Bin Meng wrote:
For any FSP enabled boards that want to enable debug UART support,
setup_internal_uart() will be called, but this API is only available
on BayTrail platform. Change to wrap it with CONFIG_INTERNAL_UART.
Signed-off-by: Bin Meng
Reviewed-by: Stefan Roese
T
On Tue, Jun 14, 2016 at 11:53 PM, Peng Fan wrote:
> When booting in eMMC fast boot, MMC host does not exit from
> boot mode after bootrom loading image. So the first command
> 'CMD0' sent in uboot will pull down the CMD line to low and
> cause errors.
>
> This patch cleans the MMC boot register in
On Tue, Jun 14, 2016 at 11:53 PM, Peng Fan wrote:
> From: Ye Li
>
> The USDHC move the 4 clock bits CARD_CLK_SOFT_EN, IPG_PERCLK_SOFT_EN,
> HCLK_SOFT_EN, and IPG_CLK_SOFT_EN from sysctl register to vendorspec
> register. The driver uses RSTA to replace the clock gate off
> operation. But this is
On Wed, Jun 15, 2016 at 3:18 AM, Peng Fan wrote:
> Q901 is PMOS, LCD_nPWREN should be at low voltage then output is 3V3.
> If LCD_nPWREN is high, output is 2.4V which is not correct.
>
> Signed-off-by: Peng Fan
> Cc: Stefano Babic
> Cc: Fabio Estevam
Reviewed-by: Fabio Estevam
___
On Wed, Jun 15, 2016 at 3:18 AM, Peng Fan wrote:
> The current pad DSE for QSPI is 60ohm. This setting cause
> too strong drive to clock and data signals. Need to change
> the DSE to 120ohm for better signal quality.
>
> Signed-off-by: Peng Fan
Reviewed-by: Fabio Estevam
___
On Wed, Jun 15, 2016 at 3:18 AM, Peng Fan wrote:
> From: Ye Li
>
> LCD_PWR_EN controls the G pin of Q13 PMOS which needs low voltage to connect
> D to S for outputting LCD 3.3V. If LCD_PWR_EN is high, we measured the LCD 3v3
> is actually 1.2V.
>
> Signed-off-by: Ye Li
> Signed-off-by: Peng Fan
On Wed, Jun 15, 2016 at 3:18 AM, Peng Fan wrote:
> Fix 74LV OE gpio index. gpio index is wrong,
> so gpio output will not have effect, since we
> use wrong GPIO5_IO18, but not correct GPIO5_IO8.
>
> And at the end of the initialization of 74lv init, should
> keep OE voltage level at LOW to make 74
Hi David,
> On Jun 15, 2016, at 13:19 , David Gibson wrote:
>
> On Wed, Jun 15, 2016 at 12:34:00PM +0300, Pantelis Antoniou wrote:
>> Hi David,
>>
>>> On Jun 15, 2016, at 06:14 , David Gibson
>>> wrote:
>>>
>>> On Tue, Jun 14, 2016 at 12:22:23PM +0300, Pantelis Antoniou wrote:
Hi David,
On Wed, Jun 15, 2016 at 12:34:00PM +0300, Pantelis Antoniou wrote:
> Hi David,
>
> > On Jun 15, 2016, at 06:14 , David Gibson
> > wrote:
> >
> > On Tue, Jun 14, 2016 at 12:22:23PM +0300, Pantelis Antoniou wrote:
> >> Hi David,
> >>> On Jun 14, 2016, at 03:25 , David Gibson
> >>> wrote:
> >>>
Hi Sergey,
On 14/06/2016 20:32, Sergey Kubushyn wrote:
> Here is the initial support for writing i.MX6 NAND U-Boot into NAND
> with all FCB and DBBT stuff as required.
>
This is a very interesting feature missing in U-Boot. Up now we are
constrained to update the bootloader from user space with
Trying again.
I have reverted back to a vanilla u-boot-2016.05, added the not-enter-quad-mode
patch and changed the SPI address where the SPL should load the u-boot from and
it does not work. My question:
Has anyone else tested SPL/u-boot on an Altera CV socdk Rev E1 board recently
(like 2016.
Hi David,
> On Jun 15, 2016, at 06:14 , David Gibson wrote:
>
> On Tue, Jun 14, 2016 at 12:22:23PM +0300, Pantelis Antoniou wrote:
>> Hi David,
>>> On Jun 14, 2016, at 03:25 , David Gibson
>>> wrote:
>>> On Fri, Jun 10, 2016 at 05:28:11PM +0300, Pantelis Antoniou wrote:
> [snip]
> +static
This fixes the following compiler error:
common/fb_mmc.c: In function ‘fb_mmc_erase’:
common/fb_mmc.c:209:17: error: ‘struct blk_desc’ has no member named
‘block_erase’
Signed-off-by: Ziyuan Xu
---
common/fb_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/fb_mmc
+Simon
On Wed, Jun 15, 2016 at 4:42 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Bin,
>
> Thanks for your information.
>
> The SPI address I mentioned was dumped from pch_get_spi_base(). But I have no
> idea where to check my memory mapping.
You need check your SoC datasheet.
> It is possible that
> On 15.06.16 10:08, Huan Wang wrote:
> >>> Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >>>
> >>> Hi, Alex,
> >>>
> > On 06/08/2016 07:14 AM, Alison Wang wrote:
> > To support loading a 32-bit OS, the execution state will change
> > from
> > AArch64 to AArch32 when jumping to kerne
Modern NANDs do not guarantee that data written in raw mode will not
contain bitflips just after writing them. This is fine since the number
of bitflips should be rather low and thus fixable by the ECC engine,
but since we are reading data in raw mode to verify if they match the
input data we canno
This fixes the following compiler error:
common/fb_mmc.c: In function ‘fb_mmc_erase’:
common/fb_mmc.c:209:17: error: ‘struct blk_desc’ has no member named
‘block_erase’
Signed-off-by: Ziyuan Xu
---
common/fb_mmc.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/common/fb_mm
On Tue, Jun 07, 2016 at 11:19:39AM -0700, Steve Rae wrote:
> - increase the size of the fill buffer
> - testing has shown a 10x improvement when the sparse image
> has large CHUNK_TYPE_FILL chunks
>
> Signed-off-by: Steve Rae
> ---
>
> Changes in v2: None
>
> common/image-sparse.c | 37 +
On Tue, Jun 07, 2016 at 11:19:38AM -0700, Steve Rae wrote:
> In order to process the CHUNK_TYPE_DONT_CARE properly, there is
> a requirement to be able to 'reserve' a specified number of blocks
> in the storage media. Because of the special handling of "bad blocks"
> in NAND devices, this is implem
Hi George,
On Tue, Jun 14, 2016 at 8:46 PM, George McCollister
wrote:
> On Mon, Jun 13, 2016 at 8:45 PM, Bin Meng wrote:
>> Hi George,
>>
>> On Tue, Jun 14, 2016 at 12:12 AM, George McCollister
>> wrote:
>>> On Fri, Jun 10, 2016 at 7:25 PM, Bin Meng wrote:
Hi George,
+Simon, Ste
Now that platform-specific ACPI global NVS is added, pack it into
ACPI table and get its address fixed up.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/acpi_table.h | 4
.../x86/include/asm/arch-baytrail/acpi/platform.asl | 3 +++
arch/x86/include/asm/arch-quark/acp
If global NVS says internal UART is not enabled, hide it in the ASL
code so that OS won't see it.
Signed-off-by: Bin Meng
---
arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a/arch/x86/include/asm/arch-baytr
ACPI global NVS is an area in system memory with various platform
defined variables that can be utilized between U-Boot and ACPI ASL
codes. U-Boot set these variables at runtime, so that ASL codes
can test these variables to provide some runtime flexiblity.
Tested on MinnowMax with CONFIG_INTERNAL
This introduces quark-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng
---
arch/x86/cpu/quark/acpi.c | 7 +++
arch/x86/include/asm/arch-quark/acpi/global_nvs.asl | 12
arch/x86/include/asm/arch-qu
This introduces baytrail-specific ACPI global NVS structure, defined in
both C header file and ASL file.
Signed-off-by: Bin Meng
---
arch/x86/cpu/baytrail/acpi.c | 26 ++
.../include/asm/arch-baytrail/acpi/global_nvs.asl | 13 +++
arch/x86/incl
On 15.06.16 10:08, Huan Wang wrote:
>>> Am 15.06.2016 um 05:04 schrieb Huan Wang :
>>>
>>> Hi, Alex,
>>>
> On 06/08/2016 07:14 AM, Alison Wang wrote:
> To support loading a 32-bit OS, the execution state will change from
> AArch64 to AArch32 when jumping to kernel.
>
> The arc
On Tue, Jun 07, 2016 at 11:19:36AM -0700, Steve Rae wrote:
> This file originally came from upstream code.
>
> While retaining the storage abstraction feature, this is the first
> set of the changes required to resync with the
> cmd_flash_mmc_sparse_img()
> in the file
> aboot.c
> from
>
>
On Wed, 2016-06-15 at 05:29 +0200, Emmanuel Vadot wrote:
Please include a short description of the board, in this case
explaining the distinction (and defconfig differences) from the non-
EMMC version would be useful.
Have a look at some of the previous patches which add defconfig (e.g.
those fro
Hi Hilbert,
On Wed, Jun 15, 2016 at 2:30 PM, Hilbert Tu(杜睿哲_Pegatron)
wrote:
> Hi Simon,
>
> I have checked the SPI base address in coreboot and u-boot. They are
> different. I am not sure is it due to the memory remapping.
> In coreboot, the SPI address is 0xfed0100
> In u-boot, the SPI address
> > Am 15.06.2016 um 05:04 schrieb Huan Wang :
> >
> > Hi, Alex,
> >
> >>> On 06/08/2016 07:14 AM, Alison Wang wrote:
> >>> To support loading a 32-bit OS, the execution state will change from
> >>> AArch64 to AArch32 when jumping to kernel.
> >>>
> >>> The architecture information will be got thro
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