From: Daniel Allred <d-all...@ti.com>

Adds an interface for calling secure ROM APIs across a range of OMAP and
OMAP compatible devices.

Signed-off-by: Daniel Allred <d-all...@ti.com>
Signed-off-by: Andreas Dannenberg <dannenb...@ti.com>
---
 arch/arm/cpu/armv7/omap-common/lowlevel_init.S | 47 ++++++++++++++++++++++----
 arch/arm/include/asm/omap_common.h             |  2 ++
 2 files changed, 42 insertions(+), 7 deletions(-)

diff --git a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S 
b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
index 5283135..2a710ce 100644
--- a/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
+++ b/arch/arm/cpu/armv7/omap-common/lowlevel_init.S
@@ -16,6 +16,8 @@
 #include <asm/arch/spl.h>
 #include <linux/linkage.h>
 
+.arch_extension sec
+
 #ifdef CONFIG_SPL
 ENTRY(save_boot_params)
 
@@ -26,14 +28,45 @@ ENDPROC(save_boot_params)
 #endif
 
 ENTRY(omap_smc1)
-       PUSH    {r4-r12, lr}    @ save registers - ROM code may pollute
+       push    {r4-r12, lr}    @ save registers - ROM code may pollute
                                @ our registers
-       MOV     r12, r0         @ Service
-       MOV     r0, r1          @ Argument
-       DSB
-       DMB
-       .word   0xe1600070      @ SMC #0 - hand assembled for GCC versions
+       mov     r12, r0         @ Service
+       mov     r0, r1          @ Argument
+       dsb
+       dmb
+       smc     0               @ SMC #0 to enter monitor mode
                                @ call ROM Code API for the service requested
 
-       POP     {r4-r12, pc}
+       pop     {r4-r12, pc}
 ENDPROC(omap_smc1)
+
+ENTRY(omap_smc_sec)
+       push    {r4-r12, lr}    @ save registers - ROM code may pollute
+
+       mov     r6, #0xFF       @ Indicate new Task call
+
+       mov     r12, #0x00      @ Secure Service ID in R12
+
+       dsb
+       dmb
+
+       smc     0               @ SMC #0 to enter monitor mode
+       b       omap_smc_sec_end /* exit at end of the service execution */
+       nop
+
+       /* In case of IRQ happening in Secure, then ARM will branch here.
+        * At that moment, IRQ will be pending and ARM will jump to Non Secure
+        * IRQ handler
+         */
+       mov     r12, #0xFE
+
+       dsb
+       dmb
+
+       smc     0               @ SMC #0 to enter monitor mode
+
+omap_smc_sec_end:
+       pop     {r4-r12, lr}
+       bx      lr
+
+ENDPROC(omap_smc_sec)
diff --git a/arch/arm/include/asm/omap_common.h 
b/arch/arm/include/asm/omap_common.h
index 07f3848..5943e6f 100644
--- a/arch/arm/include/asm/omap_common.h
+++ b/arch/arm/include/asm/omap_common.h
@@ -627,6 +627,8 @@ void recalibrate_iodelay(void);
 
 void omap_smc1(u32 service, u32 val);
 
+u32 omap_smc_sec(u32 service, u32 proc_id, u32 flag, u32 *params);
+
 void enable_edma3_clocks(void);
 void disable_edma3_clocks(void);
 
-- 
2.6.4

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