Hi Miao,
>
> Are you referring to "Initial fw_cfg support for qemu-x86 targets" ?
> I didn't find any patch in that email you sent to me.
>
YES.
The first thread of the mail contains the patch. Anyways I am
copy-pasting patch below.
> But I did give Seabios a try and it works. So I don't thi
Hi Miao,
On Tue, Dec 29, 2015 at 2:47 PM, Miao Yan wrote:
> Hi Bin,
>
> 2015-12-29 14:19 GMT+08:00 Bin Meng :
>> Hi Miao,
>>
>> nits: please use "x86: qemu" as the tag in the commit title.
>>
>> On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
>>> Document the usage of 'fw' command
>>>
>>> Signe
Hi Saket,
2015-12-28 18:43 GMT+08:00 Saket Sinha :
> Hi Miao,
>
> Find my response inline.
>
>>
>> The main purpose of my patch is:
>> + directly loads kernel from qemu
>> + eliminate the cpu number limits in smp boot
>>
>
> Our patches are similar in case of fw_cfg apis support it brings to
Hi Miao,
On Tue, Dec 29, 2015 at 2:41 PM, Miao Yan wrote:
> Hi Bin,
>
> 2015-12-29 14:19 GMT+08:00 Bin Meng :
>> Hi Miao,
>>
>> On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
>>> The QEMU fw_cfg interface allows the guest to retrieve various
>>> data information from QEMU. For example, APCI/SM
Hi Bin,
2015-12-29 14:19 GMT+08:00 Bin Meng :
> Hi Miao,
>
> nits: please use "x86: qemu" as the tag in the commit title.
>
> On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
>> Document the usage of 'fw' command
>>
>> Signed-off-by: Miao Yan
>> ---
>> doc/README.x86 | 36 ++
On 23 December 2015 at 20:39, Mugunthan V N wrote:
> Resending the patches as I have missed 01/17 patch while sending
> v6 series
>
> This patch series enables ti_qspi to adopt driver model. This has
> been tested on dra72, dra74 and am437x-sk evms (logs [1]).
> Also pushed a branch for testing [2
On 28 December 2015 at 23:02, Jagan Teki wrote:
> Cleanup set on spi_slave{}
>
> Changes for v2:
> - Replaced mode, mode_rx out-of structure members position
> - Added SPI_TX_DUAL patch
>
> Jagan Teki (10):
> spi: Remove SPI_OPM_RX_EXTN
> spi: Remove SPI_OPM_RX_DIO|QIOF
> spi
On 28 December 2015 at 23:08, Jagan Teki wrote:
> From: Mugunthan V N
>
> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
>
> Signed-off-by: Mugunthan
Hi Bin,
2015-12-29 14:19 GMT+08:00 Bin Meng :
> Hi Miao,
>
> On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
>> The QEMU fw_cfg interface allows the guest to retrieve various
>> data information from QEMU. For example, APCI/SMBios tables, number
>> of online cpus, kernel data and command line, e
On Tue, Dec 29, 2015 at 1:32 AM, Jagan Teki wrote:
> SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to
> SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO
>
> Cc: Simon Glass
> Cc: Bin Meng
> Cc: Michal Simek
> Cc: Siva Durga Prasad Paladugu
> Tested-by: Jagan Teki
> Signed-off-by: Jagan Teki
On Mon, Dec 28, 2015 at 8:20 PM, Jagan Teki wrote:
> SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to
> SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO
>
> Cc: Simon Glass
> Cc: Bin Meng
> Cc: Michal Simek
> Cc: Siva Durga Prasad Paladugu
> Tested-by: Jagan Teki
> Signed-off-by: Jagan Teki
Hi Miao,
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Add a function to fixup 'cpus' node in dts files for qemu target.
nits: fixup -> fix up
>
> Signed-off-by: Miao Yan
> ---
> arch/x86/cpu/qemu/fw_cfg.c | 66
> ++
> arch/x86/cpu/qemu/fw_cfg
Hi Miao,
nits: fixup -> fix up in the commit title
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Remove 'cpus' node in dts files for QEMU targets,
> retrieve cpu number through 'fw_cfg' interface and
> fixup device tree blob at runtime.
nits: fixup -> fix up
>
> Signed-off-by: Miao Yan
>
Hi Miao,
nits: please use "x86: qemu" as the tag in the commit title.
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Document the usage of 'fw' command
>
> Signed-off-by: Miao Yan
> ---
> doc/README.x86 | 36 +---
> 1 file changed, 33 insertions(+), 3 deleti
Hi Miao,
Please remove the qemu tag from the commit title, as this is a change
to common x86 codes.
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Use actual CPU number , instead of maximum cpu configured,
nits: remove the space after 'number'
> to allocate stack memory in 'load_sipi_vecto
Hi Miao,
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> The QEMU fw_cfg interface allows the guest to retrieve various
> data information from QEMU. For example, APCI/SMBios tables, number
> of online cpus, kernel data and command line, etc.
>
> This patch adds support for QEMU fw_cfg interfa
Hi Miao,
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Add a cpu uclass driver for qemu. Previously, the qemu
> target gets cpu number from board dts files, which are
> manually created at compile time. This does not scale
> when more cpus are assigned to guest as the dts files
> must be mod
On Mon, Dec 28, 2015 at 5:18 PM, Miao Yan wrote:
> Rename 'find_cpu_by_apid_id' to 'find_cpu_by_apic_id'. This
> should be a typo.
>
> Signed-off-by: Miao Yan
> ---
> arch/x86/cpu/mp_init.c | 6 +++---
> 1 file changed, 3 insertions(+), 3 deletions(-)
>
Reviewed-by: Bin Meng
__
On 12/17/2015 11:28 PM, Marek Vasut wrote:
> On Thursday, December 17, 2015 at 06:30:38 PM, Purna Chandra Mandal wrote:
> [...]
>
>> diff --git a/board/microchip/pic32mzda/config.mk
>> b/board/microchip/pic32mzda/config.mk new file mode 100644
>> index 000..a12e712
>> --- /dev/null
>> +++ b/bo
Hi Tom,
On Wed, Dec 23, 2015 at 9:47 PM, Tom Rini wrote:
> On Tue, Dec 22, 2015 at 11:58:01AM -0600, Joe Hershberger wrote:
>
>> A few patches that came in during the merge window and appear harmless.
>
> so..
Hmm... With the buildman toolchains I'm using nothing broke.
>>
>> These cause no add
On Mon, Dec 28, 2015 at 09:38:19AM +0800, Thomas Chou wrote:
> The following changes since commit 78680314c53a95c0bb25e942662979843b60d7b9:
>
> Merge branch 'master' of http://git.denx.de/u-boot-sunxi (2015-12-27
> 09:15:57 -0500)
>
> are available in the git repository at:
>
> git://git.d
Hi Simon,
On 2015年12月29日 08:22, Simon Glass wrote:
Hi Thomas,
On 27 December 2015 at 19:16, Bin Meng wrote:
On Sun, Dec 27, 2015 at 9:44 PM, Thomas Chou wrote:
Use generic dtb rule with CONFIG_DEFAULT_DEVICE_TREE, so that
there is no need to list all the dtb for different targets/boards.
S
Hi Lukasz,
Friendly Ping!
Could you help to review this series of patches in your free time?
BR.
Frank
On 12/23/2015 08:10 AM, Marek Vasut wrote:
On Tuesday, December 22, 2015 at 09:25:49 AM, Frank Wang wrote:
[PATCH 1/3] Modified the check condition for max packet size of ep_in in
high
Hi Thomas,
On 27 December 2015 at 19:16, Bin Meng wrote:
> On Sun, Dec 27, 2015 at 9:44 PM, Thomas Chou wrote:
>> Use generic dtb rule with CONFIG_DEFAULT_DEVICE_TREE, so that
>> there is no need to list all the dtb for different targets/boards.
>>
>> Signed-off-by: Thomas Chou
>> Cc: Albert Ar
On Thu, 2015-12-24 at 16:40 +0800, Gong Qianyu wrote:
> From: Gong Qianyu
>
> QSPI and IFC are pin-multiplexed on LS1043A. So we use
> ls1043aqds_sdcard_ifc_defconfig to support IFC in SD boot and
> ls1043aqds_sdcard_qspi_defconfig to support QSPI in SD boot. If
> QSPI is enabled, IFC should be d
Hi Michal,
On Mon, Dec 28, 2015 at 10:35 AM, Michal Simek wrote:
> ok then where is the series for converting orgin driver to this DM one?
Umhh, well it would look like:
$ git rm drivers/i2c/zynq-i2c.c
$ git add drivers/i2c/i2c-cdns.c
Do you want me to add that to the v1?
> No problem with r
Hi,
2015-12-28 18:47 GMT+01:00 Moritz Fischer :
> Hi all,
>
> I spent some time moving over the zynq-i2c.c to support dm.
>
ok then where is the series for converting orgin driver to this DM one?
> While doing that I realized that renaming it to cdns-i2c might
> make sense since it now could b
This is a possible drop in replacement for drivers/i2c/zynq-i2c.c
Since this is cadence IP it has been renamed to cdns-i2c,
to make sense with the compatible string.
Signed-off-by: Moritz Fischer
---
drivers/i2c/Kconfig| 7 +
drivers/i2c/Makefile | 1 +
drivers/i2c/i2c-cdns.c | 339 ++
Signed-off-by: Moritz Fischer
---
doc/device-tree-bindings/i2c/i2c-cdns.txt | 20
1 file changed, 20 insertions(+)
create mode 100644 doc/device-tree-bindings/i2c/i2c-cdns.txt
diff --git a/doc/device-tree-bindings/i2c/i2c-cdns.txt
b/doc/device-tree-bindings/i2c/i2c-cdns.tx
Hi all,
I spent some time moving over the zynq-i2c.c to support dm.
While doing that I realized that renaming it to cdns-i2c might
make sense since it now could be used with other SoCs that also use the
the Cadence IP.
This is a first shot, but I'd like to get some early feedback ;-)
Cheers,
From: Mugunthan V N
spi bus can support dual and quad wire data transfers for tx and
rx. So defining dual and quad modes for both tx and rx. Also add
support to parse bus width used for spi tx and rx transfers.
Signed-off-by: Mugunthan V N
Reviewed-by: Jagan Teki
---
Changes for v7:
- Fixed SP
Used BIT macro like 1 << nr as BIT(nr) where nr is 0...n
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Bin Meng
Tested-by: Jagan Teki
Reviewed-by: Bin Meng
Signed-off-by: Jagan Teki
---
include/spi.h | 38 +++---
SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to
SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO
Cc: Simon Glass
Cc: Bin Meng
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 4 ++--
drivers/mtd/spi/spi_fla
This patch moves flags macro's to respective member
position on spi_slave{}, for better readabilty and
finding the respective member macro's easily.
Cc: Simon Glass
Cc: Bin Meng
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Jagan Teki
Signed-off-by: Jaga
Fixed bit assignment with flags members on spi_slave{}
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Bin Meng
Tested-by: Jagan Teki
Reviewed-by: Bin Meng
Signed-off-by: Jagan Teki
---
include/spi.h | 6 +++---
1 file changed, 3 inserti
SPI_OPM_RX_DIO and SPI_OPM_RX_QIOF are rx IO
commands/opmodes for dual and quad. Usually IO
operation's are referred to flash protocol rather
with spi controller protocol, these are still present
in flash side for the usage of spi-nor controllers.
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga
- Add comments on mode_rx
- Tab space's
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Bin Meng
Tested-by: Jagan Teki
Reviewed-by: Bin Meng
Signed-off-by: Jagan Teki
---
include/spi.h | 32
1 file change
Since spi rx mode macro's are renamed to simple and
meaninfull, this patch will rename the respective
structure members.
Cc: Simon Glass
Cc: Bin Meng
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Jagan Teki
Signed-off-by: Jagan Teki
---
drivers/mtd/spi
SPI_OPM_RX_AS - SPI_RX_SLOW
SPI_OPM_RX_AF - SPI_RX_FAST
SPI_OPM_RX_DOUT - SPI_RX_DUAL
SPI_OPM_RX_QOF - SPI_RX_QUAD
Cc: Simon Glass
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Tested-by: Bin Meng
Tested-by: Jagan Teki
Reviewed-by: Bin Meng
Signed-off-by: Jag
Cleanup set on spi_slave{}
Changes for v2:
- Replaced mode, mode_rx out-of structure members position
- Added SPI_TX_DUAL patch
Jagan Teki (10):
spi: Remove SPI_OPM_RX_EXTN
spi: Remove SPI_OPM_RX_DIO|QIOF
spi: Rename SPI_OPM_RX_* to SPI_RX_*
spi: Rename op_mode_rx to mode
SPI_OPM_RX_EXTN is a combination of all rx opmode's
and spi driver shall use any one of the rx mode at
a time not the combination and it is true in case of
flash where spi_flash_table mention combination of
supported read opmodes so-that the required one
will pick based on the rx mode from spi driv
On Monday, December 28, 2015 at 06:08:52 PM, Daniel Schwierzeck wrote:
> Am 28.12.2015 um 16:52 schrieb Marek Vasut:
> > On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote:
> >> On 12/28/2015 09:47 PM, Marek Vasut wrote:
> >>> On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote
Hi Simon,
2015-12-28 13:29 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 22 December 2015 at 20:52, Masahiro Yamada
> wrote:
>> Hi Simon,
>>
>>
>>
BTW, the "Include file order" in
http://www.denx.de/wiki/U-Boot/CodingStyle
Is this your opinion? Or community's opinion.
>>
Hi Mateusz,
2015-12-28 1:51 GMT+09:00 Mateusz Kulikowski :
> Hi Masahiro,
>
> On 23.12.2015 04:52, Masahiro Yamada wrote:
> [..]
>> I guess Linux sorts headers from global to local.
>>
>> #include global in the project
>> #include arch-specific
>> #include "foo.h"local in the dir
Am 28.12.2015 um 16:52 schrieb Marek Vasut:
> On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote:
>> On 12/28/2015 09:47 PM, Marek Vasut wrote:
>>> On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
>>> [...]
>>>
>> "lowlevel_init.S" can't be dropped.
>
> Thank
Hi Simon,
2015-12-28 23:20 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 18 December 2015 at 04:15, Masahiro Yamada
> wrote:
>> This commit intends to implement "fixed-clock" as in Linux.
>> (drivers/clk/clk-fixed-rate.c in Linux)
>>
>> If you need a very simple clock to just provide fixed clock
Hi Simon,
2015-12-28 23:20 GMT+09:00 Simon Glass :
> Hi Masahiro,
>
> On 22 December 2015 at 03:04, Masahiro Yamada
> wrote:
>> The most basic thing for clock is to enable it, but it is missing
>> in this uclass.
>>
>> Signed-off-by: Masahiro Yamada
>> ---
>>
>> include/clk.h | 9 +
>>
Hi Simon,
2015-12-28 23:20 GMT+09:00 Simon Glass :
>>> drivers/clk/clk-fdt.c | 37 +
>>
>> I think clk_fdt.c is better since we mostly avoid hyphens except for the
>> uclass.
OK.
>>> include/clk.h | 20
>>> 3 files changed, 58
Hi Simon,
2015-12-28 23:20 GMT+09:00 Simon Glass :
>> index 371784a..1efbaf2 100644
>> --- a/include/clk.h
>> +++ b/include/clk.h
>> @@ -49,6 +49,16 @@ struct clk_ops {
>> * @return new clock rate in Hz, or -ve error code
>> */
>> ulong (*set_periph_rate)(struct udevice
On Monday, December 28, 2015 at 04:48:41 PM, Wills Wang wrote:
> On 12/28/2015 09:47 PM, Marek Vasut wrote:
> > On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
> > [...]
> >
> "lowlevel_init.S" can't be dropped.
> >>>
> >>> Thank you very much for all the effort you put into i
On 12/28/2015 09:47 PM, Marek Vasut wrote:
On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]
"lowlevel_init.S" can't be dropped.
Thank you very much for all the effort you put into investigating and
explaining why this SRAM area cannot be used ... not. From my side,
conside
On 12/28/2015 09:47 PM, Marek Vasut wrote:
On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]
"lowlevel_init.S" can't be dropped.
Thank you very much for all the effort you put into investigating and
explaining why this SRAM area cannot be used ... not. From my side,
conside
On Friday, December 11, 2015 at 05:36:15 AM, Marek Vasut wrote:
> On Tuesday, December 01, 2015 at 06:23:17 PM, Marek Vasut wrote:
> > On Monday, July 27, 2015 at 10:34:17 PM, Marek Vasut wrote:
> > > Add code to aid tracking down cache alignment issues.
> > > In case DEBUG is defined in the cache.
On 23 December 2015 at 20:39, Mugunthan V N wrote:
> spi bus can support dual and quad wire data transfers for tx and
> rx. So defining dual and quad modes for both tx and rx. Also add
> support to parse bus width used for spi tx and rx transfers.
>
> Signed-off-by: Mugunthan V N
> ---
> drivers
Hi Masahiro,
On 18 December 2015 at 04:15, Masahiro Yamada
wrote:
> This commit intends to implement "fixed-clock" as in Linux.
> (drivers/clk/clk-fixed-rate.c in Linux)
>
> If you need a very simple clock to just provide fixed clock rate
> like a crystal oscillator, you do not have to write a ne
Hi Masahiro,
On 27 December 2015 at 21:23, Simon Glass wrote:
> Hi Masahiro,
>
> On 22 December 2015 at 03:04, Masahiro Yamada
> wrote:
>> Add device tree binding support for the clock uclass. This allows
>> clock consumers to get the peripheral ID based on the "clocks"
>> property in the devic
Hi Masahiro,
On 22 December 2015 at 03:04, Masahiro Yamada
wrote:
> Currently, this framework does not provide the systematic way
> to get the peripheral ID (clock index).
>
> I assume that the functions added by this commit are mainly used to
> get the ID from "clocks" properties in device trees
Hi Masahiro,
On 22 December 2015 at 03:04, Masahiro Yamada
wrote:
> The most basic thing for clock is to enable it, but it is missing
> in this uclass.
>
> Signed-off-by: Masahiro Yamada
> ---
>
> include/clk.h | 9 +
> 1 file changed, 9 insertions(+)
Acked-by: Simon Glass
Thinking a
Hi Simon,
On 28 December 2015 at 09:52, Simon Glass wrote:
> Hi Jagan,
>
> On 19 December 2015 at 07:13, Jagan Teki wrote:
>> This patch add's spi_flash_ids handling into core, instead
>> of maintaining it into separate file like sf_params.c
>>
>> Code taken from the Linux spi-nor core and added
On Monday, December 28, 2015 at 12:17:41 PM, Wills Wang wrote:
[...]
> >> "lowlevel_init.S" can't be dropped.
> >
> > Thank you very much for all the effort you put into investigating and
> > explaining why this SRAM area cannot be used ... not. From my side,
> > consider this patch to be NAKed.
>
currently poking around in drivers/block, adding a driver for
another silicon image drive, and noticed that sata_sil3114.h has some
content that looks more appropriate for a generic ATA/SATA header
file.
for example, this snippet:
/* Missing ata defines */
#define ATA_CMD_STANDBY
On Monday, December 28, 2015 at 09:04:55 AM, Thomas Chou wrote:
> Hi Marek,
Hi!
> On 2015年12月28日 13:35, Marek Vasut wrote:
> > On Monday, December 28, 2015 at 02:17:46 AM, Thomas Chou wrote:
> >> Hi Marek,
> >>
> >> On 2015年12月25日 17:58, Marek Vasut wrote:
> >>> On Friday, December 25, 2015 at 0
On Monday, December 28, 2015 at 09:51:44 AM, Chin Liang See wrote:
> On Thu, 2015-12-24 at 02:30 +0100, Marek Vasut wrote:
> > On Thursday, December 24, 2015 at 12:36:45 AM, Chin Liang See wrote:
> > > On Thu, 2015-12-24 at 00:16 +0100, Marek Vasut wrote:
> > > > On Wednesday, December 23, 2015 at
On 28 December 2015 at 14:30, Jagan Teki wrote:
> While setting quad bit on spansion, macronix code
> is writing only particular quad bit this may give
> wrong functionality with other register bits,
> So this patch fix the issue where it with write
> previous read reg status along particular qua
On 28 December 2015 at 14:30, Jagan Teki wrote:
> One macronix quad bit set using SR, it's good to
> read back and check the written bit and also if
> it's already been set check for the bit and return.
>
> Cc: Vignesh R
> Cc: Simon Glass
> Cc: Bin Meng
> Tested-by: Mugunthan V N
> Signed-off-
On 28 December 2015 at 14:30, Jagan Teki wrote:
> One spansion quad bit set using CR, it's good to
> read back and check the written bit and also if
> it's already been set check for the bit and return.
>
> Cc: Vignesh R
> Cc: Simon Glass
> Cc: Bin Meng
> Cc: Michal Simek
> Cc: Siva Durga Pras
On 28 December 2015 at 14:30, Jagan Teki wrote:
> Setting up quad bit for micron devices need to do the
> same way as other flash devices like spansion, winbond
> etc does using enhanced volatile config register so this
> patch adds this support instead of printing "QEB is volatile"
>
> Cc: Simon
SLOW, FAST, DUAL, DUAL_IO, QUAD, QUAD_IO changed order to
SLOW, FAST, DUAL, QUAD, DUAL_IO, QUAD_IO
Cc: Simon Glass
Cc: Bin Meng
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Jagan Teki
Signed-off-by: Jagan Teki
---
drivers/mtd/spi/sf_internal.h | 4 ++--
drivers/mtd/spi/spi_fla
On 23 December 2015 at 12:53, Bin Meng wrote:
> Hi Jagan,
>
> On Wed, Dec 23, 2015 at 2:36 PM, Jagan Teki wrote:
>> Hi Bin,
>>
>> On 21 December 2015 at 11:58, Bin Meng wrote:
>>> Hi Jagan,
>>>
>>> On Wed, Dec 16, 2015 at 11:40 PM, Jagan Teki wrote:
Since spi rx mode macro's are renamed to
On 12/27/2015 08:27 PM, Marek Vasut wrote:
On Sunday, December 27, 2015 at 12:37:16 PM, Wills Wang wrote:
On 12/27/2015 07:04 PM, Marek Vasut wrote:
On Sunday, December 27, 2015 at 11:18:25 AM, Wills Wang wrote:
On 12/27/2015 06:09 PM, Marek Vasut wrote:
On Sunday, December 27, 2015 at 09:0
Hi Miao,
Find my response inline.
>
> The main purpose of my patch is:
> + directly loads kernel from qemu
> + eliminate the cpu number limits in smp boot
>
Our patches are similar in case of fw_cfg apis support it brings to
u-boot but our use case of using them are different.
My patches ta
2015-12-28 18:05 GMT+08:00 Saket Sinha :
> Hi Miao,
>
> Thanks for the patches.
>
> I made an initial attempt to support the fw_cfg in U-boot for QEMU to
> get acpi tables by fw_cfg for qemu-x86 targets.
>
> The idea was if we find acpi tables in fw_cfg try loading them,
> otherwise fallback to the
Hi Mian,
This was the initial attempt to add fw_cfg interface support for
qemu-x86 targets to mainly support ACPI tables.
The patches were dropped due to the issues discussed in the thread.
If we can collaborate the patches in the sense that we are able to
load ACPI tables(and other tables) succ
Hi Miao,
Thanks for the patches.
I made an initial attempt to support the fw_cfg in U-boot for QEMU to
get acpi tables by fw_cfg for qemu-x86 targets.
The idea was if we find acpi tables in fw_cfg try loading them,
otherwise fallback to the builtin acpi tables.
The patch was dropped mainly beca
Add a function to fixup 'cpus' node in dts files for qemu target.
Signed-off-by: Miao Yan
---
arch/x86/cpu/qemu/fw_cfg.c | 66 ++
arch/x86/cpu/qemu/fw_cfg.h | 1 +
2 files changed, 67 insertions(+)
diff --git a/arch/x86/cpu/qemu/fw_cfg.c b/arch/x86/c
Remove 'cpus' node in dts files for QEMU targets,
retrieve cpu number through 'fw_cfg' interface and
fixup device tree blob at runtime.
Signed-off-by: Miao Yan
---
arch/x86/cpu/qemu/qemu.c | 4
arch/x86/dts/qemu-x86_i440fx.dts | 18 +-
arch/x86/dts/qemu-x86_q35.dts
Add a cpu uclass driver for qemu. Previously, the qemu
target gets cpu number from board dts files, which are
manually created at compile time. This does not scale
when more cpus are assigned to guest as the dts files
must be modified as well.
This patch adds a cpu uclass driver for qemu targets
t
The fw_cfg interface provided by QEMU allow guests to retrieve various
information
about the system, e.g. cpu number, variaous firmware data, kernel setup, etc.
The
fw_cfg interface can be accessed through 3 IO ports (on x86), using x86 in/out
instructions.
- 0x510: select configuration items
Rename 'find_cpu_by_apid_id' to 'find_cpu_by_apic_id'. This
should be a typo.
Signed-off-by: Miao Yan
---
arch/x86/cpu/mp_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 4334f5b..2f34317 100644
--- a/arch/x86/
Use actual CPU number , instead of maximum cpu configured,
to allocate stack memory in 'load_sipi_vector'
Signed-off-by: Miao Yan
---
arch/x86/cpu/mp_init.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/arch/x86/cpu/mp_init.c b/arch/x86/cpu/mp_init.c
index 2f34317..2a
Document the usage of 'fw' command
Signed-off-by: Miao Yan
---
doc/README.x86 | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/doc/README.x86 b/doc/README.x86
index 1271e5e..f39c157 100644
--- a/doc/README.x86
+++ b/doc/README.x86
@@ -295,
The QEMU fw_cfg interface allows the guest to retrieve various
data information from QEMU. For example, APCI/SMBios tables, number
of online cpus, kernel data and command line, etc.
This patch adds support for QEMU fw_cfg interface.
Signed-off-by: Miao Yan
---
arch/x86/cpu/qemu/Makefile | 2 +
One spansion quad bit set using CR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.
Cc: Vignesh R
Cc: Simon Glass
Cc: Bin Meng
Cc: Michal Simek
Cc: Siva Durga Prasad Paladugu
Tested-by: Mugunthan V N
Signed-off-by: Jagan Teki
Setting up quad bit for micron devices need to do the
same way as other flash devices like spansion, winbond
etc does using enhanced volatile config register so this
patch adds this support instead of printing "QEB is volatile"
Cc: Simon Glass
Cc: Bin Meng
Cc: Peter Pan
Cc: Fabio Estevam
Cc: M
One macronix quad bit set using SR, it's good to
read back and check the written bit and also if
it's already been set check for the bit and return.
Cc: Vignesh R
Cc: Simon Glass
Cc: Bin Meng
Tested-by: Mugunthan V N
Signed-off-by: Jagan Teki
---
Changes for v3:
- Fixed if statement f
While setting quad bit on spansion, macronix code
is writing only particular quad bit this may give
wrong functionality with other register bits,
So this patch fix the issue where it with write
previous read reg status along particular quad bit.
Cc: Vignesh R
Cc: Mugunthan V N
Cc: Simon Glass
On Thu, 2015-12-24 at 02:30 +0100, Marek Vasut wrote:
> On Thursday, December 24, 2015 at 12:36:45 AM, Chin Liang See wrote:
> > On Thu, 2015-12-24 at 00:16 +0100, Marek Vasut wrote:
> > > On Wednesday, December 23, 2015 at 11:57:49 PM, Chin Liang See
> > > wrote:
> > > > On Wed, 2015-12-23 at 20:0
Hi Marek,
On 2015年12月28日 13:35, Marek Vasut wrote:
On Monday, December 28, 2015 at 02:17:46 AM, Thomas Chou wrote:
Hi Marek,
On 2015年12月25日 17:58, Marek Vasut wrote:
On Friday, December 25, 2015 at 09:33:52 AM, Thomas Chou wrote:
Hi Marek,
On 2015年12月25日 12:08, Marek Vasut wrote:
Well, it
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