Added support to power on/power off the second USB PHY present in
DRA7xx and AM57xx.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini
---
drivers/usb/dwc3/ti_usb_phy.c | 15 +++
1 file changed, 11 insertions(+), 4 deletions(-)
diff --git a/drivers/usb/dwc3/ti_usb_phy.c
The usbboot environment variable has 'usb start' command but
doesn't have the corresponding 'usb stop' command. This breaks
usb peripheral mode if tried after 'run usbboot' fails to load
the images in usb host mode.
Fix it here by adding 'usb stop' command in usbboot env.
Signed-off-by: Kishon Vi
Writing "0x00" to the USBOTGSS_IRQENABLE_SET_MISC and
USBOTGSS_IRQENABLE_SET_0 doesn't disable the interrupts. Used
USBOTGSS_IRQENABLE_CLR_MISC and USBOTGSS_IRQENABLE_CLR_0 instead.
Signed-off-by: Kishon Vijay Abraham I
Acked-by: Marek Vasut
Reviewed-by: Tom Rini
---
drivers/usb/dwc3/dwc3-omap
Patch series enables the 2nd PHY present in DRA7 SoC so that the
2nd instance of USB DWC3 can be used in peripheral mode.
It also contains minor fixes and cleanups.
Changes from v1:
Added reviewed-by and acked-by I got for the previous version
This patch series is split from [1] to contain only
vbus_id_status is initialized in board_usb_init. So remove it
while creating dwc3_device objects.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini
---
board/ti/am43xx/board.c |2 --
board/ti/dra7xx/evm.c |2 --
2 files changed, 4 deletions(-)
diff --git a/board/ti/am43xx/b
Enabled clocks for the second dwc3 controller and second USB PHY present in
DRA7.
Signed-off-by: Kishon Vijay Abraham I
Reviewed-by: Tom Rini
---
arch/arm/cpu/armv7/omap5/hw_data.c | 16
arch/arm/cpu/armv7/omap5/prcm-regs.c|2 ++
arch/arm/include/asm/arch-omap5/c
Enable SDMMC calibration to determine the best setting for
drvsel and smpsel. It will be triggered whenever there is
a change of card frequency and bus width. This is to ensure
reliable transmission between the controller and the card.
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Pavel Mach
Remove hard-coded SDMMC timing parameter drvsel and smplsel.
This setting now will come from SDMMC calibration
Signed-off-by: Chin Liang See
Cc: Dinh Nguyen
Cc: Pavel Machek
Cc: Marek Vasut
Cc: Wolfgang Denk
Cc: Stefan Roese
Cc: Tom Rini
---
include/configs/socfpga_common.h |2 --
1 fi
Synchronise the config options with Cyclone V SoCDK and other boards.
This enables ethernet on the ArriaV SoCDK.
Signed-off-by: Marek Vasut
---
configs/socfpga_arria5_defconfig | 3 +++
1 file changed, 3 insertions(+)
diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defcon
Pull out the ArriaV SoCDK clock config from ancient Altera U-Boot
"rel_socfpga_v2013.01.01_15.05.01_pr" and implant those values into
mainline to get a booting ArriaV SoCDK.
Signed-off-by: Marek Vasut
---
board/altera/arria5-socdk/qts/pll_config.h | 26 +-
1 file changed,
Add the missing DT nodes, so that ArriaV SoCDK can boot from SD
card. The SD card must be in slot J5 and BSEL must be 0x5.
Signed-off-by: Marek Vasut
---
arch/arm/dts/socfpga_arria5_socdk.dts | 6 ++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/socfpga_arria5_socdk.dts
b/arch/
On Tuesday, August 04, 2015 at 09:33:27 AM, Siva Durga Prasad Paladugu wrote:
> Added USB XHCI driver support for zynqmp.
>
> Signed-off-by: Siva Durga Prasad Paladugu
[...]
Hi,
You'd have much more success if you actually CCed me with the patches.
> +/* Declare global data pointer */
> +DECL
Hi Simon,
On Tue, Aug 18, 2015 at 11:38 PM, Simon Glass wrote:
> Add Kconfig options in preparation for moving boards to use Kconfig.
>
> Signed-off-by: Simon Glass
Acked-by: Joe Hershberger
I think that's all of it, right? I'll pull this series into u-boot-net.git.
Thanks!
-Joe
OK, I will work with Prabhakar on this.
This is freescale specific settings and workaround. Other boards out of
freescale don't use this.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 12:47 PM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B3257
> -Original Message-
> From: Kushwaha Prabhakar-B32579
> Sent: Wednesday, August 19, 2015 12:15 PM
> To: Tang Yuantian-B29983; Sun York-R58495
> Cc: u-boot@lists.denx.de; Wang Huan-B18965
> Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
>
>
> > -Original
No, the old patch still use board files. Even it is a common board file, it is
not common for other than freescale boards.
ls2085 didn't have an soc file to start with. When you have a situation like
this, you create one. I will be out in next few days, please work with
Prabhakar.
York
__
On ls2085 we had a soc file which can put all the soc specific function in it.
But on ls1021, there is no such file unless I create one for SATA.
Please see the patch I first submit. Do you prefer this way?
http://patchwork.ozlabs.org/patch/497983/
Regards,
Yuantian
From: Sun York-R58495
Sent: W
That's exactly what I mean. It is ls1021 soc erratum, not board specific.
York
Original message
From: Tang Yuantian-B29983
Date:08/18/2015 21:36 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists.denx.de, Kushwaha Prabhakar-B32579 , Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls
Add Kconfig options in preparation for moving boards to use Kconfig.
Signed-off-by: Simon Glass
---
Changes in v6:
- Drop CONFIG_E1000_FALLBACK_MAC option from README
Changes in v5: None
Changes in v4: None
Changes in v3:
- Drop CONFIG_E1000_FALLBACK_MAC option
Changes in v2:
- Move the Kconfi
Yes, this is a ls1021 specific errata.
Maybe we need to name the errata micro better.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 11:57 AM
To: Tang Yuantian-B29983
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: Re: [PATCH v2] arm/ls1021
At present buildman can compare configurations between commits but the
feature is less useful than it could be. There is no summary by architecture
and changes are not reported on a per-board basis.
Correct these deficiencies so that it is possible to see exactly what is
changing for any number of
This code is no-longer used. Drop it.
Signed-off-by: Simon Glass
---
Changes in v2: None
arch/arm/include/asm/u-boot.h | 19 --
arch/arm/lib/Makefile | 3 -
arch/arm/lib/board.c | 687 --
3 files changed, 709 deletions(-)
delete mode
> -Original Message-
> From: Tang Yuantian-B29983
> Sent: Wednesday, August 19, 2015 8:01 AM
> To: Sun York-R58495
> Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
> Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
>
> > > +#ifdef CONFIG_SY
On 08/15/2015 07:07 AM, Tom Rini wrote:
> On Fri, Aug 14, 2015 at 09:40:48PM -0600, Stephen Warren wrote:
>> On 08/14/2015 12:47 PM, Tom Rini wrote:
>>> On Tue, Aug 11, 2015 at 08:55:41AM -0600, Stephen Warren
>>> wrote:
Turn on _FS_NORTC: This means we don't have to implement
get_fattim
Yuantian,
In your patch, you are using CONFIG_SYS_FSL_ERRATUM_A008407. Are you saying
this is a board erratum, not an SoC erratum?
York
From: Tang Yuantian-B29983
Sent: Tuesday, August 18, 2015 8:47 PM
To: Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Pr
I don't understand. This workaround is our board specific and actually ls1021
specific. I thought about merging all the LS SATA initialization into one file,
but that didn't reduce many code. So I add this one by one board.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 201
The soc workarounds belongs to soc file, not board file, so you don't have to
copy the code to every board. Our boards are not the only boards with this SoC.
York
Original message
From: Tang Yuantian-B29983
Date:08/18/2015 20:34 (GMT-08:00)
To: Sun York-R58495
Cc: u-boot@lists
On Wednesday, August 19, 2015 at 05:09:23 AM, Dinh Nguyen wrote:
> On 8/10/15 6:10 PM, Marek Vasut wrote:
> > Now that we're actually converting the QTS-generated header files,
> > we can even adjust their data types. A good candidate for this is
> > the pinmux table, where each entry can have valu
On Sun, Aug 16, 2015 at 4:37 AM, Simon Glass wrote:
> This is incorrect since we require the -m parameter to the microcode tool.
> Update the two examples to show this.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> doc/README.x86 | 4 ++--
> 1 file changed, 2 insertions(+), 2
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr board
Sorry for top posting, replying from my phone
OK, I will updated this patch.
Regards,
Yuantian
From: Sun York-R58495
Sent: Wednesday, August 19, 2015 10:42 AM
To: Tang Yuantian-B29983; Sun York-R58495
Cc: u-boot@lists.denx.de; Kushwaha Prabhakar-B32579; Wang Huan-B18965
Subject: RE: [PATCH v2] arm/ls1021a: Add sata support on qds and twr bo
On 08/18/2015 08:03 AM, Guillaume GARDET wrote:
> Add CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG support to set 'board_rev' and
> 'board_name' envs.
That states what the patch does rather than why its useful to do it. Can
you expand on why it's useful to set these variables?
> diff --git a/board/raspb
On 8/10/15 6:10 PM, Marek Vasut wrote:
> This series cleans up the QTS-generated header files and cleans up
> the SoCDK support such that they fit into the framework just like
> any other SoCFPGA boards.
>
> Marek Vasut (8):
> arm: socfpga: Move wrappers into platform directory
> arm: socfpg
On 8/10/15 6:10 PM, Marek Vasut wrote:
> Now that we're actually converting the QTS-generated header files,
> we can even adjust their data types. A good candidate for this is
> the pinmux table, where each entry can have value in the range of
> 0..3, but each element is declared as unsigned long
Hi Suriyan,
On 18 August 2015 at 19:31, Suriyan Ramasami wrote:
> Hi folks and Simon,
> After moving to the driver model for USB, I see that the call to
> board_usb_init() is not done anymore. This has the board specific
> initialisation sequence. It used to be called before the driver model
On 08/18/2015 05:55 AM, Guillaume Gardet wrote:
> Hi Stephen,
>
> I want to add USB keyboard support to raspberry pi but I get the
> following error when I do 'usb start' with a keyboard plugged-in:
> unable to get device descriptor (error=-22)
>
> Ethernet chip and mass storage devices are f
Sorry for top posting, replying from my phone.
Please use macros instead of numbers. It's still better than putting magic
numbers in the code. And please move it out of board files.
York
Original message
From: Tang Yuantian-B29983
Date:08/18/2015 19:31 (GMT-08:00)
To: Sun Yor
> > +#ifdef CONFIG_SYS_FSL_ERRATUM_A008407
> > +#define SATA_ECC_REG_ADDR 0x20220520
> > + unsigned int __iomem *ecc_reg = (void *)SATA_ECC_REG_ADDR;
> #endif
> > +
> > + out_le32(&ccsr_ahci->ppcfg, 0xa003fffe);
> > + out_le32(&ccsr_ahci->pp2c, 0x28183411);
> > + out_le32(&ccsr_ahci->pp3c,
Hi, Andreas
Any feedback for this patch serials.
Best Regards,
Josh Wu
On 7/7/2015 7:08 PM, Josh Wu wrote:
As almost all sama5 sd/mmc env configurations are same, so move them to
at91-sama5_common.h.
Also we define a KERNEL_DTB_FILE_NAME as dtb file name for different
board.
Signed-off-by: J
Hi, Andreas
Any feedback for this patch? Thanks.
Best Regards,
Josh Wu
On 6/17/2015 6:56 PM, Josh Wu wrote:
Then we can use this ek_name variable to load corresponding dtb file in
mmc boot.
Also we change the mmc boot command to load zImage as this format is
prefered.
Signed-off-by: Josh Wu
Hi, Andreas
On 8/18/2015 9:04 PM, Andreas Bießmann wrote:
Hi Josh,
On 08/18/2015 01:46 PM, Andreas Bießmann wrote:
Dear "Wu, Josh",
Josh Wu writes:
From: Bo Shen
As the cache coherence issue in OHCI HCD, when enable I/D cache
for sama5d3 SoC, the OHCI can not work properly. So, switch to
Hi folks and Simon,
After moving to the driver model for USB, I see that the call to
board_usb_init() is not done anymore. This has the board specific
initialisation sequence. It used to be called before the driver model
existed by usb_lowlevel_init(). Without it, usb fails to work.
I see t
Hi Lukasz,
On Tue, Aug 18, 2015 at 4:28 PM, Lukasz Majewski wrote:
> On Tue, 18 Aug 2015 10:12:46 -0500
> Joe Hershberger wrote:
>
>> Hi Lukasz,
>>
>> On Thu, Aug 13, 2015 at 6:02 PM, Lukasz Majewski
>> wrote:
>> > This commit enables support for DFU_TFTP on the am335x bone black
>> > device.
>
On Tue, 18 Aug 2015 10:12:40 -0500
Joe Hershberger wrote:
> Hi Lukasz,
>
> On Thu, Aug 13, 2015 at 6:02 PM, Lukasz Majewski
> wrote:
> > The dfu tftp feature can be now enabled via Kconfig. This
> > commit provides necessary code for it.
> >
> > Signed-off-by: Lukasz Majewski
> > ---
> > Chang
On Tue, 18 Aug 2015 10:12:46 -0500
Joe Hershberger wrote:
> Hi Lukasz,
>
> On Thu, Aug 13, 2015 at 6:02 PM, Lukasz Majewski
> wrote:
> > This commit enables support for DFU_TFTP on the am335x bone black
> > device.
> >
> > Signed-off-by: Lukasz Majewski
> >
> > ---
> > Changes for v3:
> > - Ne
On Wed, Aug 12, 2015 at 07:31:55AM +0900, Masahiro Yamada wrote:
> We have flipped CONFIG_SPL_DISABLE_OF_CONTROL. We have cleansing
> devices, $(SPL_) and CONFIG_IS_ENABLED(), so we are ready to clear
> away the ugly logic in include/fdtdec.h:
>
> #ifdef CONFIG_OF_CONTROL
> # if defined(CONFIG
On Wednesday, August 19, 2015 at 12:36:40 AM, Jagan Teki wrote:
> On 19 August 2015 at 03:33, Marek Vasut wrote:
> > On Monday, August 17, 2015 at 12:32:54 PM, Jagan Teki wrote:
> >> This patch adds flag status register reading support to
> >> spi_flash_cmd_wait_ready.
> >>
> >> Signed-off-by: Ja
On 19 August 2015 at 03:32, Marek Vasut wrote:
> On Monday, August 17, 2015 at 12:32:53 PM, Jagan Teki wrote:
>> Current flash wait_ready logic is not modular to add new
>> register status check, hence few of the logic is used from
>> Linux spi-nor framework.
>>
>> Below are the sf speed runs with
On 19 August 2015 at 03:33, Marek Vasut wrote:
> On Monday, August 17, 2015 at 12:32:54 PM, Jagan Teki wrote:
>> This patch adds flag status register reading support to
>> spi_flash_cmd_wait_ready.
>>
>> Signed-off-by: Jagan Teki
>> Cc: Simon Glass
>> Cc: Marek Vasut
>> Cc: Michal Simek
>> Cc:
On Tuesday, August 18, 2015 at 10:30:15 PM, Dinh Nguyen wrote:
> On 8/10/15 6:02 PM, Marek Vasut wrote:
> > The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
> > This makes aliases not very usable, so make everything into mmc0.
> > Moreover, zap the useless mmc alias while at this.
On Tuesday, August 18, 2015 at 10:44:24 PM, Dinh Nguyen wrote:
> On 8/12/15 3:08 PM, Marek Vasut wrote:
> > On Tuesday, August 11, 2015 at 01:10:38 AM, Marek Vasut wrote:
> >> This series cleans up the QTS-generated header files and cleans up
> >> the SoCDK support such that they fit into the frame
On Tuesday, August 18, 2015 at 10:27:29 PM, Dinh Nguyen wrote:
> On 8/10/15 6:00 PM, Marek Vasut wrote:
> > Based on observation, this udelay(20) was apparently too high and caused
> > subsequent failure to calibrate DDR when U-Boot was compiled with certain
> > toolchains. Lowering this delay fixe
On Tuesday, August 18, 2015 at 10:13:42 PM, Dinh Nguyen wrote:
> On 8/10/15 5:59 PM, Marek Vasut wrote:
> > This gem is really really rare, there was an actual float used in
> > the Altera DDR init code, which pulled in floating point ops from
> > the libgcc, just wow.
> >
> > Since we don't suppo
On Tuesday, August 18, 2015 at 10:14:17 PM, Dinh Nguyen wrote:
> On 8/10/15 5:59 PM, Marek Vasut wrote:
> > Fix the following problem:
> > drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
> > drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may
> > be used
On Tuesday, August 18, 2015 at 10:28:55 PM, Dinh Nguyen wrote:
> On 8/10/15 6:00 PM, Marek Vasut wrote:
> > This code claims it needs to wait 7us, yet it uses get_timer() function
> > which operates with millisecond granularity. Use timer_get_us() instead,
> > which operates with microsecond granul
On Tuesday, August 18, 2015 at 10:41:26 PM, Dinh Nguyen wrote:
> On 8/10/15 6:03 PM, Marek Vasut wrote:
> > The GMAC which is enabled is purely board property, so do not enable
> > arbitrary GMAC in DT include files. Same goes for PHY mode, which is
> > again a board property. The CycloneV SoCDK do
On Monday, August 17, 2015 at 02:38:07 PM, Sergey Temerkhanov wrote:
> This patch fixes a potential NULL pointer dereference arising on
> non-present/non-initialized xHCI controllers and adds some error
> handling to xHCI code
>
> Signed-off-by: Sergey Temerkhanov
> Signed-off-by: Radha Mohan Chi
On Monday, August 17, 2015 at 12:32:54 PM, Jagan Teki wrote:
> This patch adds flag status register reading support to
> spi_flash_cmd_wait_ready.
>
> Signed-off-by: Jagan Teki
> Cc: Simon Glass
> Cc: Marek Vasut
> Cc: Michal Simek
> Cc: Siva Durga Prasad Paladugu
> Cc: Stefan Roese
> Cc: To
On Tuesday, August 18, 2015 at 09:27:18 AM, Stefan Roese wrote:
> USB EHCI on SPEAr600 has not been tested for a while. The base controller
> addresses are missing. This patch adds the defines to the header. And adds
> the missing code.
>
> Signed-off-by: Stefan Roese
> Cc: Viresh Kumar
> Cc: Vi
On Monday, August 17, 2015 at 12:32:53 PM, Jagan Teki wrote:
> Current flash wait_ready logic is not modular to add new
> register status check, hence few of the logic is used from
> Linux spi-nor framework.
>
> Below are the sf speed runs with 'sf update' on whole flash, 16MiB.
>
> => sf update
From: Mingkai Hu
High 32-bit address is needed when u-boot runs in 64-bit space.
Tested on armv8-based LS2085ARDB.
Signed-off-by: Mingkai Hu
Signed-off-by: York Sun
---
drivers/net/e1000.c |8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/net/e1000.c b/d
Il 18/08/2015 15:33, Michael Trimarchi ha scritto:
Hi
On Tue, Aug 18, 2015 at 3:22 PM, wrote:
From: Andrea Scian
MAX6373 is a simple WDT which is programmed its configuration pins
and reset via another pin, which is usually connected to a GPIO
Signed-off-by: Andrea Scian
---
Changes for
On 8/12/15 3:08 PM, Marek Vasut wrote:
> On Tuesday, August 11, 2015 at 01:10:38 AM, Marek Vasut wrote:
>> This series cleans up the QTS-generated header files and cleans up
>> the SoCDK support such that they fit into the framework just like
>> any other SoCFPGA boards.
>>
>> Marek Vasut (8):
>>
On 8/10/15 6:03 PM, Marek Vasut wrote:
> The GMAC which is enabled is purely board property, so do not enable
> arbitrary GMAC in DT include files. Same goes for PHY mode, which is
> again a board property. The CycloneV SoCDK does this correctly, but
> SoCrates doesn't. This bug never manifested
On 8/10/15 6:00 PM, Marek Vasut wrote:
> This code claims it needs to wait 7us, yet it uses get_timer() function
> which operates with millisecond granularity. Use timer_get_us() instead,
> which operates with microsecond granularity.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/mach-socfpg
On 8/10/15 6:02 PM, Marek Vasut wrote:
> The socfpga_cyclone5.dtsi has an mmc0 node, socrates has mmc node.
> This makes aliases not very usable, so make everything into mmc0.
> Moreover, zap the useless mmc alias while at this.
>
> Signed-off-by: Marek Vasut
> ---
> arch/arm/dts/socfpga.dtsi
On 8/10/15 6:00 PM, Marek Vasut wrote:
> Based on observation, this udelay(20) was apparently too high and caused
> subsequent failure to calibrate DDR when U-Boot was compiled with certain
> toolchains. Lowering this delay fixed the problem.
>
> Instead of permanently lowering the delay, calcul
On 8/10/15 5:59 PM, Marek Vasut wrote:
> This gem is really really rare, there was an actual float used in
> the Altera DDR init code, which pulled in floating point ops from
> the libgcc, just wow.
>
> Since we don't support floating point operations the same way Linux
> does not support them,
On 8/10/15 5:59 PM, Marek Vasut wrote:
> Fix the following problem:
> drivers/ddr/altera/sequencer.c: In function 'sdram_calibration_full':
> drivers/ddr/altera/sequencer.c:1943:25: warning: 'found_failing_read' may be
> used uninitialized in this function [-Wmaybe-uninitialized]
> if (found_p
Convert MPC8540ADS, MPC8541CDS, MPC8544CDS, MPC8548CDS, MPC8555CDS,
MPC8560ADS, MPC8568MDS, MPC8569MDS, MPC8610HPCD to use generic board
structure.
Signed-off-by: York Sun
---
include/configs/MPC8540ADS.h |3 +++
include/configs/MPC8541CDS.h |3 +++
include/configs/MPC8544DS.h |
On Tue, Aug 18, 2015 at 2:27 PM, Tom Rini wrote:
> On Tue, Aug 18, 2015 at 01:47:20PM -0500, Joe Hershberger wrote:
>> Hi Lars,
>>
>> On Tue, Aug 11, 2015 at 2:29 PM, Joe Hershberger
>> wrote:
>> > Hi Lars,
>> >
>> > On Tue, Jul 28, 2015 at 11:01 AM, Joe Hershberger
>> > wrote:
>> >> Hi Lars,
>>
On Tue, Aug 18, 2015 at 01:47:20PM -0500, Joe Hershberger wrote:
> Hi Lars,
>
> On Tue, Aug 11, 2015 at 2:29 PM, Joe Hershberger
> wrote:
> > Hi Lars,
> >
> > On Tue, Jul 28, 2015 at 11:01 AM, Joe Hershberger
> > wrote:
> >> Hi Lars,
> >>
> >> On Tue, Jul 28, 2015 at 3:25 AM, Lars Poeschel
> >
On 08/13/2015 11:54 PM, Yuan Yao wrote:
> For LS1021A Rev2.0 have already fixed the snoop silicon issue, So enable
> snoop requests and DVM message requests for all the slave insterfaces.
>
> Signed-off-by: Yuan Yao
> ---
> board/freescale/ls1021aqds/ls1021aqds.c | 8 +++-
> board/freescal
On 08/13/2015 11:54 PM, Yuan Yao wrote:
> EDDRTQCFG Registers are Integration Strap values which controls
> performance parameters for DDR Controller.
>
> The bit 25 is used to disable priorities within DDR since DDR
> are connected backwards on silicon Rev2.0.
>
> Signed-off-by: Yuan Yao
> --
On 08/17/2015 02:42 AM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Freescale ARM-based Layerscape LS102xA contain a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls1021aqds and ls1021atw
On 08/17/2015 02:42 AM, yuantian.t...@freescale.com wrote:
> From: Tang Yuantian
>
> Freescale ARM-based Layerscape LS2085A contain a SATA controller
> which comply with the serial ATA 3.0 specification and the
> AHCI 1.3 specification.
> This patch adds SATA feature on ls2085aqds and ls2085ard
> -Original Message-
> From: s...@google.com [mailto:s...@google.com] On Behalf Of Simon Glass
> Sent: Tuesday, August 18, 2015 5:44 AM
> To: Marcel Ziswiler
> Cc: U-Boot Mailing List; Tom Warren; Pantelis Antoniou; Tom Rini; Albert
> Aribaud; Stephen Warren
> Subject: Re: [PATCH 03/11] arm
Hi Lars,
On Tue, Aug 11, 2015 at 2:29 PM, Joe Hershberger
wrote:
> Hi Lars,
>
> On Tue, Jul 28, 2015 at 11:01 AM, Joe Hershberger
> wrote:
>> Hi Lars,
>>
>> On Tue, Jul 28, 2015 at 3:25 AM, Lars Poeschel wrote:
>>> Hi Joe,
>>>
>>> On Wed, Jun 10, 2015 at 11:03:59AM -0500, Joe Hershberger wrote:
On Wed, Aug 12, 2015 at 07:31:53AM +0900, Masahiro Yamada wrote:
> There is no case where defined(SPL_DISABLE_OF_CONTROL) is true.
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Aug 05, 2015 at 01:45:45AM +0200, Stefan Roese wrote:
> On 04.08.2015 20:26, Scott Wood wrote:
> >On Tue, 2015-08-04 at 14:39 +0200, Stefan Roese wrote:
> >>>I've used these patches while porting the pxa3xx_nand driver for the
> >>>Marvell Armada XP / 38x SoC's to current U-Boot. And have f
On Wed, Aug 12, 2015 at 08:22:13PM +0300, Vladimir Zapolskiy wrote:
> LPC32xx has 3 I2C bus controllers, 2 of them are used as generic ones
> and their parent clock is HCLK and CLK_HI/CLK_LO registers are 10 bit
> wide. This means that if HCLK is 104MHz, then minimal configurable I2C
> clock speed
On Wed, Aug 12, 2015 at 07:31:54AM +0900, Masahiro Yamada wrote:
> As we discussed a couple of times, negative CONFIG options make our
> life difficult; CONFIG_SYS_NO_FLASH, CONFIG_SYS_DCACHE_OFF, ...
> and here is another one.
>
> Now, there are three boards enabling OF_CONTROL on SPL:
> - socf
On Wed, Aug 12, 2015 at 08:32:08PM +0300, Vladimir Zapolskiy wrote:
> The change adds a number of macro definitions used by USB OHCI driver,
> if CONFIG_USB_OHCI_LPC32XX is selected from a board config file.
>
> Signed-off-by: Vladimir Zapolskiy
> Tested-by: Sylvain Lemieux
Applied to u-boot/m
On Wed, Aug 12, 2015 at 07:31:52AM +0900, Masahiro Yamada wrote:
> We do not want to compile the DM remove code for SPL. Currently,
> we undef it in include/config_uncmd_spl.h (for C files) and in
> scripts/Makefile.uncmd_spl (for Makefiles). This is really ugly.
>
> This commit demonstrates ho
On Wed, Aug 12, 2015 at 07:31:50AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Tue, Aug 11, 2015 at 07:57:09PM +0300, Vladimir Zapolskiy wrote:
> A number of LPC32xx SLC NAND defines is dictated by controller
> hardware limits and OOB layout is defined by operating system, the
> definitions are common for all users. Since those macro are used
> in out of NAND SLC driver c
On Wed, Aug 12, 2015 at 07:31:51AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Stefano Babic
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Aug 12, 2015 at 07:31:49AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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U-Boot
On Wed, Aug 12, 2015 at 07:31:47AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Stefano Babic
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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_
On Wed, Aug 12, 2015 at 07:31:46AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Stefano Babic
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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_
On Wed, Aug 12, 2015 at 07:31:48AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Wed, Aug 12, 2015 at 07:31:43AM +0900, Masahiro Yamada wrote:
> The previous commit introduced a useful macro used in makefiles,
> in order to reference to different variables (CONFIG_... or
> CONFIG_SPL_...) depending on the build context.
>
> Per-image config option control is a PITA in C so
On Thu, Aug 13, 2015 at 03:40:22PM -0400, slemieux.t...@gmail.com wrote:
> From: Sylvain Lemieux
>
> Incorporate USB driver from legacy LPCLinux NXP BSP.
> The files taken from the legacy patch are:
> - lpc32xx USB driver
> - lpc3250 header file USB registers definition.
>
> The legacy driver w
On Wed, Aug 12, 2015 at 07:31:45AM +0900, Masahiro Yamada wrote:
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
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On Mon, Aug 10, 2015 at 10:45:14PM -0600, Stephen Warren wrote:
> - Re-direct stderr into the log files, so any errors U-Boot emits are
> visible in the logs. This is relevant if the "reset" shell command
> attempts to report that it's not supported on the sandbox board.
> - Fix test_fs_nonfs(
On Wed, Aug 12, 2015 at 07:31:42AM +0900, Masahiro Yamada wrote:
> Commit e02ee2548afe ("kconfig: switch to single .config
> configuration") made the configuration itself pretty simple,
> instead, we lost the way to systematically enable/disable config
> options for each image independently.
>
>
On Thu, Aug 13, 2015 at 03:40:20PM -0400, slemieux.t...@gmail.com wrote:
> From: Sylvain Lemieux
>
> Incorporate NAND SLC hardware ECC support from legacy LPCLinux NXP BSP.
> The code taken from the legacy patch is:
> - lpc32xx SLC NAND driver (hardware ECC support)
> - lpc3250 header file missi
On Wed, Aug 12, 2015 at 07:31:41AM +0900, Masahiro Yamada wrote:
> If the target string matches "CONFIG_", move the pointer p
> forward. This saves several 7-chars adjustments.
>
> Signed-off-by: Masahiro Yamada
> Reviewed-by: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, tha
On Mon, Aug 10, 2015 at 08:16:31AM -0400, slemieux.t...@gmail.com wrote:
> From: Sylvain Lemieux
>
> Incorporate DMA driver from legacy LPCLinux NXP BSP.
> The files taken from the legacy patch are:
> - lpc32xx DMA driver
> - lpc3250 header file DMA registers definition.
>
> The legacy driver w
On Thu, Aug 13, 2015 at 03:40:21PM -0400, slemieux.t...@gmail.com wrote:
> From: Sylvain Lemieux
>
> Incorporate ECC layout for small page NAND from legacy LPCLinux NXP BSP.
> The code taken from the legacy patch is:
> - lpc32xx SLC NAND driver (ECC layout for small page)
>
> This layout is mat
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