Hi Joe,
On Wed, Jun 24, 2015 at 5:26 AM, Joe Hershberger
wrote:
> Hi Tom,
>
> On Tue, Jun 23, 2015 at 9:23 AM, Tom Rini wrote:
>> On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote:
>>
>>> This config defined a CONS_INDEX as a config but did not define it in
>>> any Kconfig, so save
On 24 June 2015 at 04:59, Simon Glass wrote:
> Add a SPI driver for the Rockchip RK3288, using driver model. It should work
> for other Rockchip SoCs also.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/spi/Kconfig | 10 ++
> drivers/spi/Makefile
Remove LS102XA immap header inclusion from xhci fsl driver.
It removes redefinition warnings when built for platforms
other than LS102XA
Signed-off-by: Nikhil Badola
---
drivers/usb/host/xhci-fsl.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/drivers/usb/host/xhci-fsl.c b/drivers/usb/host/
Hi Simon,
On Wed, Jun 24, 2015 at 11:23 AM, Simon Glass wrote:
> Hi,
>
> On 8 June 2015 at 06:32, Andrew Bradford wrote:
>> Hi Bin / Simon,
>>
>> On 06/08 10:57, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>>> > Commit afbbd413a fixed this for non-d
Hi,
On Wed, Jun 24, 2015 at 8:29 AM, Simon Glass wrote:
> Add a few notes on how to try out the Rockchip support so far.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3:
> - Update README to mention available drivers
> - Add various new patches to get RK3288 booting to a prompt
>
> Change
Hi,
On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote:
> Rockchip SoCs require certain formats for code that they execute, The
> simplest format is a 4-byte header at the start of a binary file. Add
> support for this so that we can create images that the boot ROM understands.
>
> Signed-off-by:
Hi,
On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote:
> The Rockchip boot ROM requires a particular file format for booting from SPI.
> It consists of a 512-byte header encoded with RC4, some padding and then up
> to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
>
> Add
Hi,
On Wed, Jun 24, 2015 at 8:28 AM, Simon Glass wrote:
> Since much of the code is generic, this also supports the Radxa Rock Pro.
> Since there is no device tree available for that yet, it uses the same
> config and device tree as the Firefly. This works because not all
> peripherals are suppor
Hi Simon,
On Wed, Jun 24, 2015 at 11:54 AM, Simon Glass wrote:
> Hi Bin,
>
> On 23 June 2015 at 21:46, Bin Meng wrote:
>> Hi Simon,
>>
>> On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>> On 7 June 2015 at 20:15, Bin Meng wrote:
Hi Simon,
On Sun, Jun 7, 20
Hi Bin,
On 23 June 2015 at 21:46, Bin Meng wrote:
> Hi Simon,
>
> On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
>> Hi Bin,
>>
>> On 7 June 2015 at 20:15, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
This driver should use the x86 PCI con
Hi Simon,
On Wed, Jun 24, 2015 at 11:18 AM, Simon Glass wrote:
> Hi Bin,
>
> On 7 June 2015 at 20:15, Bin Meng wrote:
>> Hi Simon,
>>
>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>>> This driver should use the x86 PCI configuration functions. Also adjust its
>>> compatible string to s
Hi Tom,
On Tue, Jun 23, 2015 at 9:33 AM, Tom Rini wrote:
> On Mon, Jun 22, 2015 at 04:15:30PM -0500, Joe Hershberger wrote:
>
>> This sets the default commands Kconfig to match
>> include/config_cmd_default.h commands in the common/Kconfig and removes
>> them from include/configs.
> [snip]
>> dif
On 7 June 2015 at 08:50, Simon Glass wrote:
> The sub-bus passed to pciauto_prescan_setup_bridge() is incorrect. Fix it
> so that sub-buses are numbered correctly.
>
> Signed-off-by: Simon Glass
> ---
>
> drivers/pci/pci-uclass.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Applied t
Hi Tom,
On Tue, Jun 23, 2015 at 9:23 AM, Tom Rini wrote:
> On Mon, Jun 22, 2015 at 04:15:27PM -0500, Joe Hershberger wrote:
>
>> This config defined a CONS_INDEX as a config but did not define it in
>> any Kconfig, so savedefconfig will delete that entry. Use
>> CONFIG_SYS_EXTRA_OPTIONS for now u
On 7 June 2015 at 08:50, Simon Glass wrote:
> Only the PCI controller has access to the PCI region information. Make sure
> to use the controller (rather than any attached bridges) when configuring
> devices.
>
> This corrects a failure to scan and configure devices when driver model is
> enabled
Hi,
On 8 June 2015 at 06:32, Andrew Bradford wrote:
> Hi Bin / Simon,
>
> On 06/08 10:57, Bin Meng wrote:
>> Hi Simon,
>>
>> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>> > Commit afbbd413a fixed this for non-driver-model. Make sure that the driver
>> > model code handles this also.
>>
Hi Bin,
On 7 June 2015 at 20:15, Bin Meng wrote:
> Hi Simon,
>
> On Sun, Jun 7, 2015 at 10:50 PM, Simon Glass wrote:
>> This driver should use the x86 PCI configuration functions. Also adjust its
>> compatible string to something generic (i.e. without a vendor name).
>>
>> Signed-off-by: Simon G
Hi,
On 4 June 2015 at 10:32, Joakim Tjernlund wrote:
> I have seen btrfs patches for u-boot flying around a year ago or so then
> it went silent. Is there any efforts ongoing to add btrfs support to u-boot?
>
> Jocke
I'm not sure. It would be good to get that in - if someone reposts I
am willin
It needs to flush D-cache before 'mmc read' so that
we can see the right data in DDR. And fix parameter
for invalidate_dcache_range() after 'mmc read'.
Signed-off-by: Yangbo Lu
Cc: York Sun
---
drivers/mmc/fsl_esdhc.c | 21 +++--
1 file changed, 15 insertions(+), 6 deletions(-)
On 22 June 2015 at 22:18, Bin Meng wrote:
> Enable writing MP table for Intel Crown Bay board.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
>
> ---
>
> Changes in v2: None
>
> configs/crownbay_defconfig | 1 +
> 1 file changed, 1 insertion(+)
Applied to u-boot-x86, thanks!
_
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> So far interrupt routing works pretty well for any on-chip devices
>> on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
>> Linux kernel is smart enough to do interrupt swizzling and figure
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Remove inline for lapic access routines and expose lapic_read()
>> & lapic_write() as APIs to read/write lapic registers. Also move
>> stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
>>
>>
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Document U-Boot multi-processor support as well as configuration
>> tables like SFI and MP tables for SMP OS kernel.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v2:
>> - New patch to update R
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> The MP table provides a way for the operating system to support
>> for symmetric multiprocessing as well as symmetric I/O interrupt
>> handling with the local APIC and I/O APIC. We provide a bunch of
>> AP
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> I/O APIC registers are addressed indirectly. Add io_apic_read() and
>> io_apic_write() routines to help register access. Two macros for I/O
>> APIC ID and version register offset are also added.
>>
>> Sign
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Implement write_mp_table() to create a minimal working MP table.
>> This includes an MP floating table, a configuration table header
>> and all of the 5 base configuration table entries. The I/O interrupt
On 22 June 2015 at 22:18, Bin Meng wrote:
> There are 4 usb ports on the Intel Crown Bay board, 2 of which are
> connected to Topcliff usb host 0 and the other 2 connected to usb
> host 1. USB devices inserted in the ports connected to usb host 1
> cannot get detected due to wrong IRQ assigned to
On 22 June 2015 at 22:18, Bin Meng wrote:
> Remove all the dead/unused macros from asm/ioapic.h.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
> ---
>
> Changes in v2: None
>
> arch/x86/include/asm/ioapic.h | 26 +++---
> 1 file changed, 3 insertions(+), 23 deletions(-
On 22 June 2015 at 22:18, Bin Meng wrote:
> In fill_irq_info() pci device's function number is written into
> the table, however this is not really necessary. The function
> number can be anything as OS doesn't care about this field,
> neither does the PIRQ routing specification. Change to always
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Add a RTC node in the device tree to enable DM RTC support.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v2:
>> - New patch to enable DM RTC support for Crown Bay
>>
>> arch/x86/dts/crownbay.
On 22 June 2015 at 22:18, Bin Meng wrote:
> There is no need to populate multiple irq info entries with the same
> bus number and device number, but with different interrupt pin. We
> can use the same entry to store all the 4 interrupt pin (INT A/B/C/D)
> routing information to reduce the whole PI
On 22 June 2015 at 22:18, Bin Meng wrote:
> We should write correct bus number to the PIRQ routing table for the
> irq router from device tree, instead of hard-coded zero.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/irq.c | 2 +-
> 1 file c
On 16 June 2015 at 21:15, Bin Meng wrote:
> Intel Crown Bay board has a TunnelCreek processor which supports
> hyper-threading. Add /cpus node in the crownbay.dts and enable
> the MP initialization.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
>
> ---
>
> Changes in v4: None
> Changes in
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
>> but it should be actually CONFIG_DM_RTC.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v2:
>> - New patch to change to use CON
On 16 June 2015 at 21:15, Bin Meng wrote:
> This commit cleans up the lapic codes:
> - Delete arch/x86/include/asm/lapic_def.h, and move register and bit
> defines into arch/x86/include/asm/lapic.h
> - Use MSR defines from msr-index.h in enable_lapic() and disable_lapic()
> - Remove unnecessary
On 23 June 2015 at 19:45, Simon Glass wrote:
> On 22 June 2015 at 22:18, Bin Meng wrote:
>> Add driver model support to the mc146818 rtc driver. Also clean up
>> the driver a little bit for coding convention issues.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v2:
>> - New patch to s
Hi Bin,
On 16 June 2015 at 21:15, Bin Meng wrote:
>
> Ivybridge is not ready for U-Boot MP initialization yet.
>
> Signed-off-by: Bin Meng
> Acked-by: Simon Glass
>
> ---
>
> Changes in v4: None
> Changes in v3:
> - New patch to remove SMP from CPU_SPECIFIC_OPTIONS for ivybridge
>
> Changes in
On 16 June 2015 at 21:15, Bin Meng wrote:
> Currently lapic_setup() is called before calling mp_init(), which
> then calls init_bsp() where it calls enable_lapic(), which was
> already enabled in lapic_setup(). Hence move lapic_setup() call
> into init_bsp() to avoid the duplication.
>
> Signed-of
On 16 June 2015 at 21:15, Bin Meng wrote:
> Most of the MP initialization codes in arch/x86/cpu/baytrail/cpu.c is
> common to all x86 processors, except detect_num_cpus() which varies
> from cpu to cpu. Move these to arch/x86/cpu/cpu.c and implement the
> new 'get_count' method for baytrail and cp
On 17 June 2015 at 09:11, Simon Glass wrote:
> On 16 June 2015 at 21:15, Bin Meng wrote:
>> Introduce a new method 'get_count' in the UCLASS_CPU ops to get
>> the number of CPUs in the system.
>>
>> Signed-off-by: Bin Meng
>>
>> ---
>>
>> Changes in v4:
>> - Remove parameter 'count' from cpu_get
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass wrote:
> These bloat the code and cause problems for SPL. Use debug() where possible
> and try to return a useful error code instead.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v3: None
> Changes in v2: None
>
> drivers/mmc/dw_mmc.c | 21
Hi,
On Wed, Jun 24, 2015 at 5:38 AM, Simon Glass wrote:
> Some SoCs want to adjust the input clock to the DWMMC block as a way of
> controlling the MMC bus clock. Update the get_mmc_clk() method to support
> this.
The subject line should probably reflect this is a DWMMC only patch?
There are sys
On 22 June 2015 at 22:18, Bin Meng wrote:
> Implement write_mp_table() to create a minimal working MP table.
> This includes an MP floating table, a configuration table header
> and all of the 5 base configuration table entries. The I/O interrupt
> assignment table entry is created based on the sa
On 22 June 2015 at 22:18, Bin Meng wrote:
> Document U-Boot multi-processor support as well as configuration
> tables like SFI and MP tables for SMP OS kernel.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to update README.x86 for SMP support
>
> doc/README.x86 | 13 ++
On 22 June 2015 at 22:18, Bin Meng wrote:
> Remove inline for lapic access routines and expose lapic_read()
> & lapic_write() as APIs to read/write lapic registers. Also move
> stop_this_cpu() to mp_init.c as it has nothing to do with lapic.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
On 22 June 2015 at 22:18, Bin Meng wrote:
> I/O APIC registers are addressed indirectly. Add io_apic_read() and
> io_apic_write() routines to help register access. Two macros for I/O
> APIC ID and version register offset are also added.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - D
On 22 June 2015 at 22:18, Bin Meng wrote:
> So far interrupt routing works pretty well for any on-chip devices
> on Intel Crown Bay. When inserting any PCIe card to any PCIe slot,
> Linux kernel is smart enough to do interrupt swizzling and figure
> out device's irq using its parent bridge's inter
On 22 June 2015 at 22:18, Bin Meng wrote:
> The MP table provides a way for the operating system to support
> for symmetric multiprocessing as well as symmetric I/O interrupt
> handling with the local APIC and I/O APIC. We provide a bunch of
> APIs for U-Boot to write the floating table, configura
On 22 June 2015 at 22:18, Bin Meng wrote:
> Add a RTC node in the device tree to enable DM RTC support.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to enable DM RTC support for Crown Bay
>
> arch/x86/dts/crownbay.dts | 1 +
> arch/x86/dts/rtc.dtsi | 6 ++
> con
On 22 June 2015 at 22:18, Bin Meng wrote:
> Currently CONFIG_DM_I2C is used in cmd_date.c for driver model,
> but it should be actually CONFIG_DM_RTC.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to change to use CONFIG_DM_RTC instead of CONFIG_DM_I2C
>
> common/cmd_date.
On 22 June 2015 at 22:18, Bin Meng wrote:
> Add driver model support to the mc146818 rtc driver. Also clean up
> the driver a little bit for coding convention issues.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2:
> - New patch to support mc146818 driver in driver model
>
> drivers/rtc/m
The Firefly RK3288 is a suitable target board for initial mainline Rockchip
support. It includes a good set of peripherals, a recent SoC and it is
readily available.
This adds only some basic files required to allow the baord to display a
serial message in SPL and hang.
Signed-off-by: Simon Glass
This builds and displays an SPL message, but does not function beyond that.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2:
- Tidy up license headers and remove SPL #ifdefs
arch/arm/dts/Makefile | 3 +-
arch/arm/dts/cros-ec-sbs.dtsi | 16 +
Add code for starting up U-Boot SPL and U-Boot proper. This is generic and
makes use of devices provided by the board- or SoC-specific code.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/Kconfig | 10 ++
arch/arm/Makefile
Add an I2C driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/i2c.h | 70 ++
drivers/i2c/Kconfig | 9 +
drivers/i2
Add a driver that provides access to system controllers.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile| 1 +
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 +
2 files changed, 26 insertions(+)
Add a driver which supports pin multiplexing setup for the most commonly
used peripherals.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/pinctrl/Kconfig | 9 +
drivers/pinctrl/Makefile | 1 +
drivers/pinctrl/rockchip/Makef
Add a few notes on how to try out the Rockchip support so far.
Signed-off-by: Simon Glass
---
Changes in v3:
- Update README to mention available drivers
- Add various new patches to get RK3288 booting to a prompt
Changes in v2: None
doc/README.rockchip | 246 +
Add code to set up the SDRAM in SPL, ready for loading U-Boot. This uses
device tree for configuration so should be able to support other RAM
configurations. It may be possible to generalise the code to support other
SoCs at some point.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes
Add a SPI driver for the Rockchip RK3288, using driver model. It should work
for other Rockchip SoCs also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/Kconfig | 10 ++
drivers/spi/Makefile | 1 +
drivers/spi/rk_spi.c | 375
Add header files for the peripherals and clocks supported on Rockchip
platforms. The particular implementation (and register set) for each is
SoC-specific, but it seems that the naming can be generic.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/a
Add an MMC driver which supports RK3288, but may also support other SoCs.
It uses the Designware MMC device.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig| 9 +
drivers/mmc/Makefile | 1 +
drivers/mmc/rockchip_mmc.c | 98
Add a driver for the ACT8846 PMIC. This supports several LDOs and BUCKs and
is connected to the I2C bus. This driver supports using a regulator driver
to access the regulators.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/Kconfig | 9 +
drive
We can reset the SoC using some CRU (clock/reset unit) registers. Add support
for this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile | 7 +
arch/arm/mach-rockchip/rk3288/reset_rk3288.c | 47
Rockchip SoCs require certain formats for code that they execute, The
simplest format is a 4-byte header at the start of a binary file. Add
support for this so that we can create images that the boot ROM understands.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common
PMU is the power management unit and GRF is the general register file. Both
are heavily used in U-Boot. Add header files with register definitions.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/grf_rk3288.h | 768 +
The Rockchip boot ROM requires a particular file format. It consists of
64KB of zeroes, a 512-byte header encoded with RC4, and then some executable
code.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
converted to this format.
Signed-off-by: Simon Glass
---
Changes in
This supports RK3288 at present. It does not implement functions or support
for pull up/down.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/gpio.h | 28 +++
drivers/gpio/Kconfig | 9 +++
drivers/gpio/Makefi
Add a driver for setting up and modifying the various PLLs and peripheral
clocks on the RK3288.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/include/asm/arch-rockchip/cru_rk3288.h | 185 +++
drivers/clk/Makefile| 1 +
drivers
Add a full regulator driver for the ACT8846. This provides easy access to
voltage and current settings for each regulator.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/Kconfig | 9 +++
drivers/power/regulator/Makefile | 1 +
drivers/powe
Bring in required device tree files from Linux. Since mainline Linux is
somewhat behind, use the files from the Chromium tree. We can re-sync once
further code is acccepted upstream.
Signed-off-by: Simon Glass
---
Changes in v3:
- Add device tree bindings for CRU and DMC
Changes in v2:
- Tidy u
Add support for the Rockchip serial device using the ns16550 driver.
This uses driver model and device tree for both SPL and U-Boot proper.
Signed-off-by: Simon Glass
---
Changes in v3:
- Update clock rate to always be 24MHz
Changes in v2: None
drivers/serial/Kconfig | 9 +
The Rockchip boot ROM requires a particular file format for booting from SPI.
It consists of a 512-byte header encoded with RC4, some padding and then up
to 32KB of executable code in 2KB blocks, separated by 2KB empty blocks.
Add support to mkimage so that an SPL image (u-boot-spl-dtb.bin) can be
In SPL we need access to the CRU and other peripherals so we can set up
SDRAM. Mark these so that they will remain in the device tree.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/dts/rk3288.dtsi | 15 +++
1 file changed, 15 insertions(+)
diff --
At present there is an arbitrary limit of 4KB for padding. Rockchip needs
more than that, so remove this restriction.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/mkimage.c | 23 ---
1 file changed, 12 insertions(+), 11 deletions(-)
diff --g
Allow the image handler to store the original input file size so that it
can reference it later.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
tools/imagetool.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tools/imagetool.h b/tools/imagetool.h
index 99bbf2f..23c
The Rockchip RK3288 is based on a quad-core Cortex-A17 CPU and has a good
set of peripherals. Various full-featured U-Boot ports are available and
this is an attempt to bring those features into mainline. With this series
the Firefly RK3288 can boot to a prompt from an SD card.
Since much of the
Add basic support for MMC, providing a uclass which can set up an MMC
device. This allows MMC drivers to move to using driver model.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/Kconfig | 10 ++
drivers/mmc/Makefile | 2 ++
drivers/mmc/mm
Several functions in this file should be marked as static. Update them.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/spi/spi-uclass.c | 8
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/spi/spi-uclass.c b/drivers/spi/spi-uclass.
Add an implementation of RC4. This will be used by Rockchip booting but may
be useful in other situations.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/rc4.h | 21 +
lib/Makefile | 1 +
lib/rc4.c | 49 +
Add a simple uclass for LEDs, so that these can be controlled by the device
tree and activated when needed. LEDs are referred to by their label.
This implementation requires a driver for each type of LED (e.g GPIO, I2C).
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
d
Add a simple driver which allows use of LEDs attached to GPIOs. The linux
device tree binding is used.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
doc/device-tree-bindings/leds/leds-gpio.txt | 52 ++
drivers/led/Kconfig | 9 +++
Now that we support driver model in SPL, allow GPIO drivers to be used there
also.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/gpio/Makefile | 4
1 file changed, 4 deletions(-)
diff --git a/drivers/gpio/Makefile b/drivers/gpio/Makefile
index 5864850..67
Decide when the regulator is set up whether we want to auto-set the voltage
or current. This avoids the complex logic spilling into the processing code.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 12
include/
We can calculate this. Add code to do this if it is not provided.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c | 10 --
1 file changed, 8 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/dw_mmc.c b/drivers/mmc/dw_mmc.c
index a034c3f
Clocks are an important feature of platforms and have become increasing
complex with time. Most modern SoCs have multiple PLLs and dozens of clock
dividers which distribute clocks to on-chip peripherals.
Some SoC implementations have a clock API which is private to that SoC family,
e.g. Tegra and
Some SoCs want to adjust the input clock to the DWMMC block as a way of
controlling the MMC bus clock. Update the get_mmc_clk() method to support
this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/dw_mmc.c| 2 +-
drivers/mmc/exynos_dw_mmc.c | 2 +
It is common for system reset to be available at multiple levels in modern
hardware. For example, an SoC may provide a reset option, and a board may
provide its own reset for reasons of security or thoroughness. It is useful
to be able to model this hardware without hard-coding the behaviour in the
Add an spl_init() function that does basic init such that board_init_f() can
use simple malloc(), device tree and driver model. Each one is set up only
if enabled for SPL.
Note: We really should refactor SPL such that there is a single
board_init_f() and rename the existing weak board_init_f() fun
To reduce unnecessary code size in an uncommon code path, use debug()
where possible(). The driver returns an error which indicates failure.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/regulator/regulator-uclass.c | 2 +-
1 file changed, 1 insertion(+),
Allow read errors to be diagnosed more easily.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/mmc/mmc.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/drivers/mmc/mmc.c b/drivers/mmc/mmc.c
index 4eab274..da47037 100644
--- a/drivers/
It is a common requirement to update some PMIC registers. Provide some
simple convenience functions to do this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/pmic-uclass.c | 32
include/power/pmic.h | 34 +
Add a simple implementaton of register maps, supporting only direct I/O
for now. This can be enhanced later to support buses which have registers,
such as I2C, SPI and PCI.
It allows drivers which can operate with multiple buses to avoid dealing
with the particulars of register access on that bus.
It took a little while to figure this out, so this patch adds documentation
to help the next person who needs to do this.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
include/dwmmc.h | 18 +-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git
This functionality may be useful for setting up regulators early during
boot.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
scripts/Makefile.spl | 1 +
1 file changed, 1 insertion(+)
diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl
index 24ca58b..1e58be9 10064
As a debug option, add positive confirmation that SPL has completed
execution. This can help with diagnosing the location of unexpected hangs.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
common/spl/spl.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/common/spl/
It can be quite confusing with a new platform to figure out why the device
tree cannot be located. Add some debug information for this case.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
lib/fdtdec.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/lib/fdtdec
This is not user input (i.e. from the command line). It should be possible
to get the case correct and avoid the case-insensitive match. This will
help avoid sloppy device tree setups.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/power/pmic/pmic-uclass.c | 2 +
Since we want clk_ops to be used in U-Boot as a whole, rename the Zynq
version until it can be converted to driver model.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-zynq/clk.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/ar
Since Rockchip requires 32-bit serial access, add this to the driver.
Refactor a little to make this easier.
Signed-off-by: Simon Glass
---
Changes in v3: None
Changes in v2: None
drivers/serial/ns16550.c | 36 +---
1 file changed, 21 insertions(+), 15 deletions
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