Add a driver that provides access to system controllers.
Signed-off-by: Simon Glass <s...@chromium.org>
---
Changes in v3: None
Changes in v2: None
arch/arm/mach-rockchip/rk3288/Makefile | 1 +
arch/arm/mach-rockchip/rk3288/syscon_rk3288.c | 25 +++++++++++++++++++++++++
2 files changed, 26 insertions(+)
create mode 100644 arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
diff --git a/arch/arm/mach-rockchip/rk3288/Makefile
b/arch/arm/mach-rockchip/rk3288/Makefile
index c6663f0..3f9900d 100644
--- a/arch/arm/mach-rockchip/rk3288/Makefile
+++ b/arch/arm/mach-rockchip/rk3288/Makefile
@@ -5,3 +5,4 @@
#
obj-y += reset_rk3288.o
+obj-y += syscon_rk3288.o
diff --git a/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
new file mode 100644
index 0000000..c9f7c4e
--- /dev/null
+++ b/arch/arm/mach-rockchip/rk3288/syscon_rk3288.c
@@ -0,0 +1,25 @@
+/*
+ * Copyright (C) 2015 Google, Inc
+ * Written by Simon Glass <s...@chromium.org>
+ *
+ * SPDX-License-Identifier: GPL-2.0+
+ */
+
+#include <common.h>
+#include <dm.h>
+#include <syscon.h>
+#include <asm/arch/clock.h>
+
+static const struct udevice_id rk3288_syscon_ids[] = {
+ { .compatible = "rockchip,rk3288-noc", .data = ROCKCHIP_SYSCON_NOC },
+ { .compatible = "rockchip,rk3288-grf", .data = ROCKCHIP_SYSCON_GRF },
+ { .compatible = "rockchip,rk3288-sgrf", .data = ROCKCHIP_SYSCON_SGRF },
+ { .compatible = "rockchip,rk3288-pmu", .data = ROCKCHIP_SYSCON_PMU },
+ { }
+};
+
+U_BOOT_DRIVER(syscon_rk3288) = {
+ .name = "rk3288_syscon",
+ .id = UCLASS_SYSCON,
+ .of_match = rk3288_syscon_ids,
+};
--
2.4.3.573.g4eafbef
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