Unlike OMAP5, EMIF PHY used in DRA7 will be left in unknown state after
warm reset, emif needs to be configured to bring it back to a known
state. So configure EMIF during warm reset.
Reported-by: Roger Quadros
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 4 ++-
Should be marked for V2 version.
*V2*:
Nothing has changed.
Regards,
-Dongsheng
> -Original Message-
> From: Dongsheng Wang [mailto:dongsheng.w...@freescale.com]
> Sent: Thursday, June 04, 2015 12:01 PM
> To: Sun York-R58495
> Cc: i...@hellion.org.uk; hdego...@redhat.com; albert.u.b...@a
Hi all,
Sorry I was too busy recently, and I forgot to tag version information.
The patches should be marked for V2 version.
*V2*:
1. Retain the original author's Copyright.
2. Based on Chen-Yu Tsai's patch rebase this patch, factor out time_wait
Macro from psci_sun7i.S and psci_sun6i.S.
Reg
From: Wang Dongsheng
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted
completely into a reusable armv7 generic timer. LS1021A will use it
as well.
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S
index
From: Wang Dongsheng
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR.
Test CPU hotplug times: 60K
Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile
b/arch/arm/cpu/armv7/ls102xa/Ma
Hi Bin,
On 3 June 2015 at 06:59, Andrew Bradford wrote:
> On 06/03 07:17, Bin Meng wrote:
>> Hi Andrew,
>>
>> On Wed, Jun 3, 2015 at 4:05 AM, Andrew Bradford
>> wrote:
>> > Hi Bin,
>> >
>> > On 06/01 20:31, Bin Meng wrote:
>> >> The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so f
Hi John,
On 3 June 2015 at 18:13, Bin Meng wrote:
> Hi,
>
> On Thu, Jun 4, 2015 at 5:44 AM, John Hawley wrote:
>> Ok some more data points. I tested with the FSP3 Gold that Saket built,
>> and it continues to work on the A0, but it continues to not work on the
>> A2 D0 board I have. I'm guessi
On Thu, Jun 4, 2015 at 12:37 AM, wrote:
> From: Andrew Bradford
>
> Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF
> and additional SDRAM is mapped from 0x1 and up. There is a
> physical memory hole from 0x8000 to 0x for other uses.
> Because of this
Hi,
On Thu, Jun 4, 2015 at 5:44 AM, John Hawley wrote:
> Ok some more data points. I tested with the FSP3 Gold that Saket built,
> and it continues to work on the A0, but it continues to not work on the
> A2 D0 board I have. I'm guessing this is something between the
> steppings in the CPU and
On Wed, Jun 3, 2015 at 5:26 PM, Tom Rini wrote:
> On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote:
>> Hi Tom,
>>
>> On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote:
>> > On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote:
>> >
>> >> Select CONFIG_CMD_NET and CONFIG_CMD_S
On Wed, Jun 03, 2015 at 05:21:44PM -0500, Joe Hershberger wrote:
> Hi Tom,
>
> On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote:
> > On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote:
> >
> >> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
> >> needing to have this
Hi Tom,
On Wed, Jun 3, 2015 at 5:12 PM, Tom Rini wrote:
> On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote:
>
>> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
>> needing to have this in every sunxi defconfig file.
>>
>> This also fixes the Merrii_A80_Optimus def
On Wed, Jun 03, 2015 at 08:12:16PM +0200, Hans de Goede wrote:
> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
> needing to have this in every sunxi defconfig file.
>
> This also fixes the Merrii_A80_Optimus defconfig no longer building.
>
> Cc: Maxin B. John
> Reported-by
Ok some more data points. I tested with the FSP3 Gold that Saket built,
and it continues to work on the A0, but it continues to not work on the
A2 D0 board I have. I'm guessing this is something between the
steppings in the CPU and the FSP, but I'm not sure.
Adding Vincent to this, as I'm guessi
Hi,
> I'm 99% sure that's the issue. try with FSP 3 gold."
>
> I am now trying to build the u-boot.rom from FSP 3 gold and would let
> you know about the results ASAP.
u-boot.rom prepared from FSP3-Gold dowmloaded from
https://downloadcenter.intel.com/download/24496 doesn't work with the
minnowma
On Wed, 2015-06-03 at 20:12 +0200, Hans de Goede wrote:
> Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
> needing to have this in every sunxi defconfig file.
>
> This also fixes the Merrii_A80_Optimus defconfig no longer building.
>
> Cc: Maxin B. John
> Reported-by: Maxin
On Wed, 2015-06-03 at 16:09 +0200, Hans de Goede wrote:
> Ah yes the W: option in MAINTAINERS is indeed the best place to
> stick URL-s, thanks for your input.
Agreed.
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Hi Simon,
>>> I might be able to create an image that prints out post_code() calls.
>
> I added a debug UART image here:
> https://drive.google.com/folderview?id=0B7WYZbZ9zd-3flBfMEk3WHRSclJDWHFxOWlQTlBEUHg3aGM0aUZhLTdMYWVGbm9HNXNYTlU&usp=sharing
>
The results are identical as that of previous im
Select CONFIG_CMD_NET and CONFIG_CMD_SETEXPR by default rather then
needing to have this in every sunxi defconfig file.
This also fixes the Merrii_A80_Optimus defconfig no longer building.
Cc: Maxin B. John
Reported-by: Maxin B. John
Signed-off-by: Hans de Goede
---
board/sunxi/Kconfig
Hello Pavel,
On Wed, 8 Apr 2015 14:15:54 +0200, Pavel Machek wrote:
>
> Fix big/small letters in comment.
>
> Signed-off-by: Pavel Machek
>
> diff --git a/arch/arm/cpu/armv7/start.S b/arch/arm/cpu/armv7/start.S
> index 5ed0f45..1c7e6f0 100644
> --- a/arch/arm/cpu/armv7/start.S
> +++ b/arc
Hello Axel,
On Tue, 14 Apr 2015 14:55:24 +0800, Axel Lin wrote:
> The LPC32XX GPIO driver platdata currently contains GPIO state information,
> which should go into priv_data. Thus rename lpc32xx_gpio_platdata to
> lpc32xx_gpio_priv and convert to use dev_get_priv() instead.
>
> Signed-off-by: A
This patch introduces some changes to the omap common boot code, to allow the
omap3 to benefit from it, but also to clean it up drastically.
It was tested on an OMAP3 device booting from MMC.
Since this also affects OMAP4, OMAP5 and AM33xx devices, I'm looking forward
to having this tested on boar
This introduces OMAP3 support for the common omap boot code, as well as a
major cleanup of the common omap boot code.
First, the omap_boot_parameters structure becomes platform-specific, since its
definition differs a bit across omap platforms. The offsets are removed as well
since it is U-Boot's
This switches some printf calls to puts and avoids a test repetition.
Signed-off-by: Paul Kocialkowski
---
common/spl/spl_mmc.c | 11 +--
1 file changed, 5 insertions(+), 6 deletions(-)
diff --git a/common/spl/spl_mmc.c b/common/spl/spl_mmc.c
index de495c0..f5ac844 100644
--- a/common/s
From: Andrew Bradford
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF
and additional SDRAM is mapped from 0x1 and up. There is a
physical memory hole from 0x8000 to 0x for other uses.
Because of this, PCI region 3 should only try to use up to the amoun
On 06/03 12:18, and...@bradfordembedded.com wrote:
> From: Andrew Bradford
>
> Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF
> and additional SDRAM is mapped from 0x1 and up. There is a
> physical memory hole from 0x8000 to 0x for other uses.
> Becau
From: Andrew Bradford
Baytrail physically maps the first 2 GB of SDRAM from 0x0 to 0x7FFF
and additional SDRAM is mapped from 0x1 and up. There is a
physical memory hole from 0x8000 to 0x for other uses.
Because of this, PCI region 3 should only try to use up to the amoun
On Wed, Jun 03, 2015 at 09:05:23AM -0500, Joe Hershberger wrote:
> Hi Damien,
>
> On Tue, Jun 2, 2015 at 3:22 PM, Damien Riegel
> wrote:
> > The TS-4800 doesn't have its MAC address fused, therefore the
> > fec_mxc driver can not currently fetch it.
> >
> > This commit adds the capability to fetc
On 05/28/2015 02:23 AM, Prabhakar Kushwaha wrote:
> Add support for board eth initialization and support for loading phy
> firmware. PHY firmware needs to be loaded from board_eth_init() because
> all the MACs are not initialized by ldpaa_eth driver.
>
> Signed-off-by: pankaj chauhan
> Signed-o
On Wed, Jun 03, 2015 at 04:36:06PM +0200, Lars Poeschel wrote:
> On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote:
> > On Mon, Jun 01, 2015 at 05:09:11PM +0200, poesc...@lemonage.de wrote:
> >
> > > From: Lars Poeschel
> > >
> > > This add a Kconfig entry that allows to set the board rev
make Merrii_A80_Optimus_defconfig
make
fails with the following error:
board/sunxi/built-in.o: In function `misc_init_r':
/root/u-boot/board/sunxi/board.c:540: undefined reference to
`eth_setenv_enetaddr'
Enable CONFIG_CMD_NET in Merrii_A80_Optimus_defconfig to fix it.
Signed-off-by: Maxin B. J
Hello Albert,
On Thu, 16 Apr 2015 13:24:50 +0200, Albert ARIBAUD
wrote:
> Hello Thierry,
>
> I assume there will be a v2 series?
>
> (asking so that I can mark the series "Changes Requested")
Ping.
Amicalement,
--
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Hello Tom,
On Wed, 22 Apr 2015 09:49:55 -0400, Tom Rini wrote:
> On Thu, Apr 16, 2015 at 09:30:14AM +0200, Albert ARIBAUD wrote:
> > Hello Tom,
> >
> > On Tue, 3 Feb 2015 15:21:53 -0500, Tom Rini wrote:
> > > - Move the obj- lines for memset.S/memcpy.S to outside of an SPL check
> > > so tha
On Tue, 14 Apr 2015 10:34:46 +0200, Albert ARIBAUD
wrote:
> Hello feng...@phytium.com.cn,
>
> On Tue, 3 Feb 2015 16:10:25 +0800, feng...@phytium.com.cn
> wrote:
> > From: David Feng
> >
> > This patch replace CONFIG_ARM64 with gcc builtin __aarch64__.
> > CONFIG_ARM64 is still needed in makef
Enable the debug UART and emit a single 'a' early in the init sequence to
show that it is working.
Unfortunately the debug UART implementation needs a stack to work. I cannot
seem to remove this limitation as the absolute 'jmp %eax' instruction goes
off into the weeds.
So this means that the char
Hi Saket,
On 2 June 2015 at 11:02, Saket Sinha wrote:
> Hi Simon,
>
>>
>> Also do you know which MinnowMAX board you have? I think there are two
>> versions.
>
> The pcb does not speak of any particular versions.
>
> I found there are two hardware revisions -
> http://www.elinux.org/Minnowboar
On Tue, Jun 02, 2015 at 10:34:34AM -0400, Tom Rini wrote:
> On Mon, Jun 01, 2015 at 05:09:11PM +0200, poesc...@lemonage.de wrote:
>
> > From: Lars Poeschel
> >
> > This add a Kconfig entry that allows to set the board revision in
> > menuconfig. So the deprecated CONFIG_SYS_EXTRA_OPTIONS is no l
On Wed, Jun 03, 2015 at 02:43:26PM +0530, Lokesh Vutla wrote:
> DDRIO_2 and LPDDR2CH1_1 registers are not present
> for DRA7. So not configuring these registers for DRA7xx
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
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On Wed, Jun 03, 2015 at 02:43:27PM +0530, Lokesh Vutla wrote:
> Update DDR IO register values.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
Tom
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On Wed, Jun 03, 2015 at 02:43:25PM +0530, Lokesh Vutla wrote:
> A generic is_dra72x cpu check is useful for grouping
> all the revisions under that. This is used in the
> subsequent patches.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
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On Wed, Jun 03, 2015 at 02:43:24PM +0530, Lokesh Vutla wrote:
> Updating EMIF registers to enable HW leveling
> on DRA72-evm.
> Also updating the timing registers.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
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On Wed, Jun 03, 2015 at 02:43:23PM +0530, Lokesh Vutla wrote:
> Updating EMIF registers to enable HW leveling
> on DRA7-evm.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
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On Wed, Jun 03, 2015 at 02:43:22PM +0530, Lokesh Vutla wrote:
> Updating EMIF registers to enable HW leveling
> on BeagleBoard-X15.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
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On Wed, Jun 03, 2015 at 02:43:21PM +0530, Lokesh Vutla wrote:
> DRA7 EMIF supports Full leveling for DDR3.
> Adding support for the Full leveling sequence.
>
> Signed-off-by: Lokesh Vutla
Reviewed-by: Tom Rini
--
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On Wed, Jun 03, 2015 at 02:43:20PM +0530, Lokesh Vutla wrote:
> This series updates the DDR3 init sequence and adds support for
> hw leveling for all DRA7 platforms.
>
> Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards.
For sanity sake, tested on omap5_uevm (but indeed,
On Fri, May 29, 2015 at 02:47:17PM +0530, Ramneek Mehresh wrote:
> Remove all redundant dwc3 driver function calls that
> are defined by dwc3 driver
>
> Signed-off-by: Ramneek Mehresh
On an am43xx-gp-evm:
Tested-by: Tom Rini
Reviewed-by: Tom Rini
--
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On Fri, May 29, 2015 at 02:47:18PM +0530, Ramneek Mehresh wrote:
> Remove all redundant dwc3 driver function calls that
> are defined by dwc3 driver
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
Tom
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On Fri, May 29, 2015 at 02:47:20PM +0530, Ramneek Mehresh wrote:
> From: ramneek mehresh
>
> Add base register address information for USB
> XHCI controller on LS1021A
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
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On Fri, May 29, 2015 at 02:47:21PM +0530, Ramneek Mehresh wrote:
> From: ramneek mehresh
>
> Enable USB IP support for both EHCI and XHCI for
> ls1021atwr platform
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
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On Fri, May 29, 2015 at 02:47:19PM +0530, Ramneek Mehresh wrote:
> From: ramneek mehresh
>
> Add xhci driver support for all FSL socs
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
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On Fri, May 29, 2015 at 02:47:22PM +0530, Ramneek Mehresh wrote:
> From: ramneek mehresh
>
> Enable USB IP support for both EHCI and XHCI for
> ls1021aqds platform
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
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Hi,
On 03-06-15 14:52, Tom Rini wrote:
On Wed, Jun 03, 2015 at 08:49:04AM +0100, Ian Campbell wrote:
On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote:
So if there is no way to store this info in the defconfigs lets
just leave it out and will point people to the wiki.
Would it be totall
On Fri, May 29, 2015 at 02:47:16PM +0530, Ramneek Mehresh wrote:
> Remove all redundant dwc3 driver function calls that
> are defined by dwc3 driver
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
--
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On Thu, May 28, 2015 at 04:41:54PM +0200, Hannes Schmelzer wrote:
> netconsole had become defective over time and cleanups.
> Because the feature is used very rarely nobody did take notice about this
> defect.
>
> With this patch the resulting syntax error on call will be fixed.
>
> Signed-off-b
On Fri, May 29, 2015 at 02:47:15PM +0530, Ramneek Mehresh wrote:
> Add support for DWC3 XHCI controller driver
>
> Signed-off-by: Ramneek Mehresh
Reviewed-by: Tom Rini
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Hi Damien,
On Tue, Jun 2, 2015 at 3:22 PM, Damien Riegel
wrote:
> The TS-4800 doesn't have its MAC address fused, therefore the
> fec_mxc driver can not currently fetch it.
>
> This commit adds the capability to fetch the MAC address from
> environment if not found in fuses.
>
> Signed-off-by: Da
Hi Simon,
On Wed, Jun 3, 2015 at 2:38 AM, Simon Glass wrote:
> Hi Bin,
>
> On 2 June 2015 at 08:41, Bin Meng wrote:
>> Hi Simon,
>>
>> On Tue, Jun 2, 2015 at 6:44 PM, Bin Meng wrote:
>>> Hi Simon,
>>>
>>> On Tue, Jun 2, 2015 at 6:40 PM, Bin Meng wrote:
The following error is observed on Q
On 06/03 07:17, Bin Meng wrote:
> Hi Andrew,
>
> On Wed, Jun 3, 2015 at 4:05 AM, Andrew Bradford
> wrote:
> > Hi Bin,
> >
> > On 06/01 20:31, Bin Meng wrote:
> >> The call to FspInitEntry is done in arch/x86/lib/fsp/fsp_car.S so far.
> >> It worked pretty well but looks not that good. Apart from
On Wed, Jun 03, 2015 at 08:49:04AM +0100, Ian Campbell wrote:
> On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote:
> > So if there is no way to store this info in the defconfigs lets
> > just leave it out and will point people to the wiki.
>
> Would it be totally mad to have a string CONFIG_B
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 4 ++--
board/ti/beagle_x15/board.c | 4 ++--
2 fil
On Wednesday 03 June 2015 04:17 PM, Lokesh Vutla wrote:
> When DLL_CALIB_INTERVAL is set, an extra delay is added
> which is not required and it consumes EMIF bandwidth.
> So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
I missed updating on emif2 for beagle-x15. Ill send a v2 for thi
When DLL_CALIB_INTERVAL is set, an extra delay is added
which is not required and it consumes EMIF bandwidth.
So making the DLL_CALIB_CTRL[8:0]DLL_CALIB_INTERVAL bits to 0.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 4 ++--
board/ti/beagle_x15/board.c | 2 +-
2 files
On this bus there is a EEPROM containing EDID and ddr3
calibration information.
Signed-off-by: Christian Gmeiner
---
board/bachmann/ot1200/ot1200.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index a33d496..
Make it possible to use the i2c bus in SPL.
Signed-off-by: Christian Gmeiner
---
board/bachmann/ot1200/ot1200.c | 40 ++--
1 file changed, 22 insertions(+), 18 deletions(-)
diff --git a/board/bachmann/ot1200/ot1200.c b/board/bachmann/ot1200/ot1200.c
index e43
L2 cache may still be enabled by the BootROM. We need to first disable
it before enabling d-cache support.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/cpu.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/mach-mvebu/cpu.c b/arch/arm/mach-mvebu/cpu.c
index b687422..7
The u-boot-spl.kwb build target needs the SPL text-base
(CONFIG_SPL_TEXT_BASE) as load and execution address.
Signed-off-by: Stefan Roese
---
Makefile | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Makefile b/Makefile
index 14f782e..13ff552 100644
--- a/Makefile
+++ b/Makef
This patch-set adds the DDR3 setup and training code taken from the Marvell
U-Boot repository. This code used to be included as a binary (bin_hdr) into
the A38x boot image. Not linked with the main U-Boot. With this code
addition and the also included SERDES / PHY setup code, the Armada 38x
suppor
This patch adds SPL support for the Marvell DB-88F6820-GP board.
With this change, the bin_hdr from the original Marvell U-boot
is not needed any more on this board. The sources from bin_hdr
(SERDES/PHY and DDR setup) are now integrated in mainline
U-Boot. And this patch enables them for this board
With the upcoming addition of the Armada 38x SPL support, which is not
compatible to the Armada XP SERDES init code, we need to introduce a new
directory infrastructure. So lets move the AXP serdes init code into
a new directory. This way the A38x code can be added in a clean way.
Signed-off-by: S
With the upcoming addition of the Armada 38x DDR support, which is not
compatible to the Armada XP DDR init code, we need to introduce a new
directory infrastructure. To support multiple Marvell DDR controller.
This will be the new structure:
drivers/ddr/marvell/axp
Supporting Armada XP
On A38x switching the regs base address without running from
SDRAM doesn't seem to work. So let the SPL still use the
default base address and switch to the new address in the
mail u-boot later.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/include/mach/soc.h | 10 ++
1 file chang
Only with disabled MMU its possible to switch the base register address on
Armada 38x. Without this the SDRAM located at >= 0x4000. is also not
accessible, as its still locked to cache.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/cpu.c | 18 ++
1 file changed, 18 ins
To support the Armada 38x, new values for the request-delay and the
response-timeout are needed. As the values already implemented in
this tool (for Kirkwood and Armada XP) don't seem to work here.
To make this more flexible, lets add make those 2 parameters
configurable via the cmdline. Here the n
Pin muxing needs to be done before UART output, since on A38x the UART
pins need some re-muxing for output to work.
Signed-off-by: Stefan Roese
---
arch/arm/mach-mvebu/spl.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/mach-mvebu/spl.c b/arch/arm/mach-mvebu/spl.c
index 40
From: Kevin Smith
If defined, the macro CONFIG_SYS_SPI_U_BOOT_OFFS allows a board
to specify the offset of the payload image into the kwb image
file. This value was being used to locate the image, but was not
used in the "header size" field of the main header. Move the
use of this macro into th
Updating EMIF registers to enable HW leveling
on BeagleBoard-X15.
Signed-off-by: Lokesh Vutla
---
board/ti/beagle_x15/board.c | 26 ++
1 file changed, 18 insertions(+), 8 deletions(-)
diff --git a/board/ti/beagle_x15/board.c b/board/ti/beagle_x15/board.c
index 75dd8e8..7
Update DDR IO register values.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/hw_data.c | 16
1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hw_data.c
b/arch/arm/cpu/armv7/omap5/hw_data.c
index b9734fe..6de5974 100644
--- a/arch
Updating EMIF registers to enable HW leveling
on DRA7-evm.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c
index 2e2385
DDRIO_2 and LPDDR2CH1_1 registers are not present
for DRA7. So not configuring these registers for DRA7xx
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/hwinit.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c
b/arch/a
A generic is_dra72x cpu check is useful for grouping
all the revisions under that. This is used in the
subsequent patches.
Signed-off-by: Lokesh Vutla
---
arch/arm/include/asm/omap_common.h | 7 +++
1 file changed, 7 insertions(+)
diff --git a/arch/arm/include/asm/omap_common.h
b/arch/arm/
Updating EMIF registers to enable HW leveling
on DRA72-evm.
Also updating the timing registers.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap5/sdram.c | 17 +++--
1 file changed, 11 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/
DRA7 EMIF supports Full leveling for DDR3.
Adding support for the Full leveling sequence.
Signed-off-by: Lokesh Vutla
---
arch/arm/cpu/armv7/omap-common/emif-common.c | 146 +++
arch/arm/cpu/armv7/omap5/sdram.c | 76 +-
arch/arm/include/asm/emif.h
This series updates the DDR3 init sequence and adds support for
hw leveling for all DRA7 platforms.
Tested memtest and reboot on DRA7-evm , DRA72-evm, BeagleBoard-x15 boards.
Lokesh Vutla (7):
ARM: DRA7: DDR3: Add support for HW leveling
ARM: BeagleBoard-X15: Enable HW leveling
ARM: DRA7-ev
This patch refer to linux kernel commit: d8b763e1e79f
net/macb: add TX multiqueue support for gem
by: Cyrille Pitchen
1. macb driver will check the register to find how many queues support for
this chip.
2. Then as we only use queue0 for tx, so we will set up all other queues
use a dummy desc
Hi,
On 03-06-15 09:49, Ian Campbell wrote:
On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote:
So if there is no way to store this info in the defconfigs lets
just leave it out and will point people to the wiki.
Would it be totally mad to have a string CONFIG_BOARD_URL containing a
URL (e
On Tue, 2015-06-02 at 09:07 +0200, Hans de Goede wrote:
> So if there is no way to store this info in the defconfigs lets
> just leave it out and will point people to the wiki.
Would it be totally mad to have a string CONFIG_BOARD_URL containing a
URL (e.g. to the relevant wiki page) which was pri
On Tue, 2015-06-02 at 22:10 +0200, Hans de Goede wrote:
> Add "allwinner,sun8i-a33-pinctrl", this is used by the latest upstream
> linux sunxi dts files.
>
> Signed-off-by: Hans de Goede
All four: Acked-by: Ian Campbell
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Hi,
On 02-06-15 22:10, Hans de Goede wrote:
Add and use a proper dts for the ga10h a33 based tablet, as
submitted upstream.
Note this just got accepted upstream.
Regards,
Hans
Signed-off-by: Hans de Goede
---
arch/arm/dts/Makefile | 1 +
arch/arm/dts/sun8i-a33-ga10h
On Tue 2015-06-02 13:13:05, Tom Rini wrote:
> On Tue, Jun 02, 2015 at 11:08:21AM -0600, Simon Glass wrote:
>
> > The root cause of this problem should now be fixed.
> >
> > This reverts commit a6a4c542d316b3401f0840ac5378743191bca851.
> > Signed-off-by: Simon Glass
>
> Thanks for digging into a
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