From: Scott Wood
Use "qixis_reset nand" to reset the board to boot from NAND.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
board/freescale/common/qixis.c | 31 +--
1 file c
From: Yangbo Lu
This patch adds esdhc support for ls2085a.
Signed-off-by: Yangbo Lu
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 10 +++
arch/arm/cpu/armv8/fsl-lsch3/fdt.c
This erratum requires setting GLITCH_EN bit in debug register.
Signed-off-by: York Sun
CC: Heiko Schocher
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2:
Add comment to I2C workaround
arch/arm/cpu/armv8/fsl-lsch3/soc.c | 34 +
From: Scott Wood
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command. Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5:
Fix signed-off-by si
The LS2085ARDB is a evaluation platform that supports LS2085A
family SoCs. This patch add sbasic support for the platform.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma
Signed-off-by: Scott Wood
---
Changes in v5:
Fix Kconfig help for inconsistent
From: Scott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework.
Details of forming NAND image can be found in README.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5:
Update LS2085AQDS README to include instructions to form NAND image
Changes in v4:
From: Prabhakar Kushwaha
Add support of ethernet:
- eth.c: mapping lane to slot for (0x2A, 0x07)
- ls2085a.c: To enable/disable dpmac and get link type
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: No
From: Jaiprakash Singh
IFC has two register pages.Till IFC version 1.4 each
register page is 4KB each.But IFC ver 2.0 register page
size is 64KB each.IFC regiters structure is break into
two viz FCM and RUNTIME.FCM(Flash control machine) registers
are defined in PAGE0 and controls IFC generic fun
From: "J. German Rivera"
Load AIOP image from NOR flash into DDR so that the MC firmware
the MC fw can start it at boot time.
Signed-off-by: J. German Rivera
[York Sun: This is a debug commit. Will drop once AIOP is loaded by Linux]
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v
From: Prabhakar Kushwaha
Fix flush_dcache_range() input parameter to use start and end addresses.
Change ethernet interface name to DPNI. Update entry criteria for
ldpaa_eth_stop. Ethernet stack first stop the device before performing
next operation. At the time of Ethernet driver registration,
n
From: Shaohui Xie
The memac for PHY management on little endian SoCs is similar on big
endian SoCs, so we modify the driver by using I/O accessor function to
handle the endianness, so the driver can be reused on little endian
SoCs, we introduce CONFIG_SYS_MEMAC_LITTLE_ENDIAN for little endian
SoC
From: Prabhakar Kushwaha
Wire rate IO Processor (WRIOP) provide support of receive and transmit
ethernet frames from the ethernet MAC. Here Each WRIOP block supports
upto 64 DPMACs.
Create a house keeping data structure to support upto 16 DPMACs and
store external phy related information.
Sign
The LS2085AQDS is an evaluatoin platform that supports the LS2085A
family SoCs. This patch add basic support of the platform.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma
---
Changes in v5:
Fix board README for inconsistent SoC name
Fix comment i
From: pankaj chauhan
Fix comilation warning which is emitted when
firmware address is more than 32 bit.
Signed-off-by: pankaj chauhan
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
drivers/net/phy/cortina.c |4 ++--
1 file cha
From: Scott Wood
This lets us see the problems (close to) when they happen,
rather than Linux hanging when it enables them prior to having a
working console.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
From: Bhupesh Sharma
This patch adds support to print out the Reset Configuration Word
information.
Signed-off-by: Bhupesh Sharma
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 14 +++
From: "J. German Rivera"
Changed MC firmware loading to comply with the new MC boot architecture.
Flush D-cache hierarchy after loading MC images. Add environment
variables "mcboottimeout" for MC boot timeout in milliseconds,
"mcmemsize" for MC DRAM block size. Check MC boot status before calling
From: Scott Wood
Without this "USB may not work" according to the erratum text, though I
did not notice a problem without it.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/so
From: Minghuan Lian
Add support of SerDes framework for Layerscape Architecture.
- Add support of 2 SerDes block
- Add SerDes protocol parsing and detection
- Create table of SerDes protocol supported by LS2085A
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Minghuan Lian
---
C
From: Scott Wood
The serial nodes in the fsl-lsch3 device trees have compatible =
"fsl,ns16550", "ns16550a" -- so don't look for "ns16550".
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv
From: Scott Wood
This is required for TLB invalidation broadcasts to work.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/lowlevel.S |9 +
arch/arm/include/as
From: Scott Wood
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/Makefile |1 +
arch/arm/cpu/armv8/fsl-lsch3/soc.c| 14 ++
arch/arm/include/asm/arc
Platform clock is half of platform PLL. There is an additional divisor
in place. Clean up code copied from powerpc.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/speed.c |7 +++
1 file changed, 3
From: Prabhakar Kushwaha
ls2085a_common.h contains hard-coded information for NOR/NAND flash,
I2C, DDR, etc. These are platform specific. Move them out of common
header file and placed into respective board header files.
Move TEXTBASE to 1MB offset to fit NOR flash with up to 1MB sector
size.
E
From: pankaj chauhan
Add support for reset_cpu() by asserting RESET_REQ_B.
Signed-off-by: pankaj chauhan
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/fsl-lsch3/cpu.c | 11 +++
board/freescale/ls2085a
During booting, IFC is mapped to low region. After booting up, IFC is
remapped to high region for larger space. The environmental variables are
also stored at high region. In order to read the variables during booting,
a virtual mapping is required.
Cache was enabled for entire IFC space before. A
This set adds necessary support in common ls2085a support and board
support for QDS and RDB.
Changes in v5:
Re-generate patches using patman default flags
s/LayerScape/Layerscape/g
Fix board README for inconsistent SoC name
Fix comment in board header file
s/LS2080/LS2085/g
Fix Kconfig
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v5: None
Generic Timer may contain an erroneous value. The workaround is to
read it twice until getting the same value.
Signed-off-by: York Sun
---
Changes in v5: None
Changes in v4: None
Changes in v3: None
Changes in v2: None
arch/arm/cpu/armv8/generic_timer.c | 11 +++
arch/arm/i
On 03/20/2015 05:33 PM, Scott Wood wrote:
> On Fri, 2015-03-20 at 17:29 -0700, York Sun wrote:
>> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
>> index f4a7851..7478eb4 100644
>> --- a/arch/arm/Kconfig
>> +++ b/arch/arm/Kconfig
>> @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
>>develo
On Fri, 2015-03-20 at 17:29 -0700, York Sun wrote:
> diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> index f4a7851..7478eb4 100644
> --- a/arch/arm/Kconfig
> +++ b/arch/arm/Kconfig
> @@ -658,6 +658,16 @@ config TARGET_LS2085AQDS
> development platform that supports the QorIQ LS2085A
>
The LS2080ARDB is a evaluation platform that supports LS2080A
family SoCs. This patch add sbasic support for the platform.
Signed-off-by: York Sun
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Bhupesh Sharma
Signed-off-by: Scott Wood
---
Changes in v4:
Fix board README for inconsistent
On Fri, 2015-03-20 at 20:18 -0400, Tom Rini wrote:
> On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote:
> > On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
> > > On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
> > >
> > > [snip]
> > > > It would also be nice to sort out loa
On Fri, Mar 20, 2015 at 04:44:19PM -0500, Scott Wood wrote:
> On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
> > On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
> >
> > [snip]
> > > It would also be nice to sort out loading the environment during SPL.
> >
> > *ears perk up*. Plea
On 03/20/2015 05:12 PM, Scott Wood wrote:
> On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote:
>>
>> On 03/20/2015 04:01 PM, Scott Wood wrote:
>>> On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote:
#ifndef __ASSEMBLY__
unsigned long get_board_sys_clk(void);
-unsigned long get_boa
On Fri, 2015-03-20 at 17:08 -0700, York Sun wrote:
>
> On 03/20/2015 04:01 PM, Scott Wood wrote:
> > On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote:
> >> #ifndef __ASSEMBLY__
> >> unsigned long get_board_sys_clk(void);
> >> -unsigned long get_board_ddr_clk(void);
> >> #endif
> >>
> >> #de
On 03/20/2015 04:01 PM, Scott Wood wrote:
> On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote:
>> The LS2080ARDB is a evaluation platform that supports LS2080A
>> family SoCs. This patch add sbasic support for the platform.
>
> s/2080/2085/
>
>> diff --git a/board/freescale/ls2085aqds/Makefile
On 20 March 2015 at 09:24, Tom Rini wrote:
> On Fri, Mar 20, 2015 at 01:24:45PM +0900, Masahiro Yamada wrote:
>
>> Serial-uclass should be generically implemented without depending
>> a particular hardware. Fortunately, nothing in include/ns16550.h is
>> referenced from drivers/serial/serial-ucla
On 13 March 2015 at 02:48, Inha Song wrote:
> We can enable / disable trace feature from the FTRACE config options.
> To enable, compile U-Boot with FTRACE=1.
>
> This patch add #ifdef FTRACE in exynos5-common.h for enable/disable
> to use FTRACE configs instead of having to change board config fi
On 5 March 2015 at 12:25, Simon Glass wrote:
> Move chromebook_link over to driver model for PCI.
>
> This involves:
> - adding a uclass for platform controller hub
> - removing most of the existing PCI driver
> - adjusting how CPU init works to use driver model instead
> - rename the lpc compatib
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add some basic tests to check that things work as expected with sandbox.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> test/dm/Makefile | 1 +
> test/dm/pci.c| 59
>
>
On 5 March 2015 at 12:25, Simon Glass wrote:
> Since sandbox does not have real devices (unless it borrows those from the
> host) it must use emulations. Provide a uclass which permits PCI operations
> to be passed through to an emulation device.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes i
On 5 March 2015 at 12:25, Simon Glass wrote:
> Move coreboot-x86 over to driver model for PCI.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/coreboot/pci.c | 63
> ++---
> arch/x86/dts/chromebook_link.dts| 7 +
> b
On 5 March 2015 at 12:25, Simon Glass wrote:
> Enable PCI options so that sandbox can be used for testing this bus with
> driver model.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> configs/sandbox_defconfig | 3 +++
> include/configs/sandbox.h | 4
> 2 files changed, 7 i
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add a simple x86 PCI driver which uses standard functions provided by the
> architecture.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> arch/x86/cpu/pci.c | 40
> arch/x86/include/a
On 5 March 2015 at 12:25, Simon Glass wrote:
> This device sits on the sandbox PCI bus and provides a case-swapping
> service for sandbox. It illustrates the use of both PCI I/O and PCI
> memory accesses.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> drivers/misc/Makefile|
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add a driver which can access emulations of devices and make them available
> in sandbox.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> drivers/pci/Kconfig | 10 ++
> drivers/pci/Makefile | 1 +
> drivers/pci/pci_s
On 5 March 2015 at 12:25, Simon Glass wrote:
> Both of these values are useful for understanding what is going on, so show
> them both.
>
> The requested number comes from a device tree alias. The allocated one is
> set up when the device is activated, and is unique throughout the uclass.
>
> Sign
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add the required header information, device tree nodes and I/O accessor
> functions to support PCI on sandbox. All devices are emulated by drivers
> which can be added as required for testing or development.
>
> Signed-off-by: Simon Glass
> ---
>
> C
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
> the 'pci' command and the existing PCI support to work with this new uclass.
> Keep most of the compatibility code in a separate file so that it can be
> removed one day.
>
>
On 5 March 2015 at 12:25, Simon Glass wrote:
> Some uclasses want to set up a device before it is probed. Add a method
> for this.
>
> An example is with PCI, where a PCI uclass wants to set up its private
> data for later use. This allows the device's uclass() method to make calls
> whcih use tha
On 5 March 2015 at 12:25, Simon Glass wrote:
> At present the device is not active when the probe() method is called. But
> some probe() methods want to set up the device and this can involve
> accessing it through normal methods. For example a PCI bus may wish to
> set up its PCI parameters using
On 5 March 2015 at 12:25, Simon Glass wrote:
> Driver model will share many functions with the existing PCI implementation.
> Move these into their own file to avoid duplication and confusion.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
>
> drivers/pci/Makefile | 2 +-
> d
On 5 March 2015 at 12:25, Simon Glass wrote:
> Add a convenience function to access the private data that a uclass stores
> for each of its devices. Convert over most existing uses for consistency
> and to provide an example for others.
>
> Signed-off-by: Simon Glass
> ---
>
> Changes in v2: None
On 9 March 2015 at 03:06, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> This function does not unmap what it maps. Correct it.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2: None
>>
>> common/cmd_mem.c | 7 ---
>> 1 file changed, 4 insertions(+), 3 de
On 9 March 2015 at 03:09, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> This function returns -ENOENT when the property is missing (which the caller
>> might forgive) and also when the property is present but incorrectly
>> formatted (which many callers would like to rep
On 9 March 2015 at 03:02, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> Since driver model is set up after arch_cpu_init(), that function cannot
>> use drivers. Add a new arch_cpu_init_dm() function which is called
>> immediately after driver model is ready, and can refe
On 9 March 2015 at 03:06, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> At present we do more in this function than we should. Split out the
>> post-driver-model part into a separate function.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Use the new
On 6 March 2015 at 08:43, Tom Rini wrote:
> On Thu, Mar 05, 2015 at 12:25:14PM -0700, Simon Glass wrote:
>
>> This function is missing a prototype but is more widey useful. Add it.
>>
>> Signed-off-by: Simon Glass
>
> Reviewed-by: Tom Rini
Applied to u-boot-dm/next.
On 5 March 2015 at 12:25, Simon Glass wrote:
> These functions currently use a generic name, but they are for x86 only.
> This may introduce confusion and prevents U-Boot from using these names
> more widely.
>
> In fact it should be possible to remove these at some point and use
> generic functio
On 11 March 2015 at 23:08, Bin Meng wrote:
> It is very common in the debug stage to test U-Boot loading a linux
> kernel. The commands to boot linux kernel with ramdisk and nfs as the
> root are common to all x86 targets, so it makes sense to add them as
> the U-Boot default environment in x86-co
Hi,
On 5 March 2015 at 12:25, Simon Glass wrote:
>
> This series is a collection of changes in core DM, sandbox, x86 and PCI code
> to implement a PCI uclass and associated operations. Some basic tests are
> provided as well.
>
> As is becoming common with DM conversions, the existing structure (
On 2 March 2015 at 12:40, Simon Glass wrote:
> Support running U-Boot as a coreboot payload. Tested peripherals include:
>
> - Video (HDMI and DisplayPort)
> - SATA disk
> - Gigabit Ethernet
> - SPI flash
>
> USB3 does not work. This may be a problem with the USB3 PCI driver or
> something in the
On 9 March 2015 at 02:57, Bin Meng wrote:
> On Fri, Mar 6, 2015 at 3:25 AM, Simon Glass wrote:
>> We should have a size value for these. Add one in each case. This will
>> be needed for PCI.
>>
>> Signed-off-by: Simon Glass
>> ---
>>
>> Changes in v2:
>> - Update root node #size=cells to 1 in th
On 2 March 2015 at 12:40, Simon Glass wrote:
> Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Jagannadha Sutradharudu Teki
> ---
>
> Changes in v2: None
>
> drivers/spi/ich.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 de
On 2 March 2015 at 12:40, Simon Glass wrote:
> Since Chromebooks mostly have similar configuration, put it in a common
> file.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2: None
>
> include/configs/chromebook_link.h | 61 +--
> i
On 2 March 2015 at 12:40, Simon Glass wrote:
> Add some new device IDs used by this haswell-based chipset.
>
> Signed-off-by: Simon Glass
> Reviewed-by: Bin Meng
> ---
>
> Changes in v2:
> - Put this patch before the one that needs it
>
> include/pci_ids.h | 2 ++
> 1 file changed, 2 insertions
On 3 March 2015 at 00:56, Lukasz Majewski wrote:
> Hi Simon,
>
>> Some systems have more than 4GB of RAM. U-Boot can only place things
>> below 4GB so any memory above that should not be used. Ignore any
>> such memory so that the memory size will not exceed the maximum.
>>
>> This prevents gd->ra
On 2 March 2015 at 12:40, Simon Glass wrote:
> At present a VGA console assumes a keyboard unless a CONFIG option is set.
> This difference can be dealt with by a device tree option, allowing boards
> that are otherwise the same to use the same configuration.
>
> Signed-off-by: Simon Glass
> ---
Hi Joe,
On 11 March 2015 at 17:44, Joe Hershberger wrote:
> This value is not used by the network stack and is available in the
> global data, so stop passing it around. For the one legacy function
> that still expects it (init op on old Ethernet drivers) pass in the
> global pointer version dir
On Thu, 2015-03-19 at 09:45 -0700, York Sun wrote:
> The LS2080ARDB is a evaluation platform that supports LS2080A
> family SoCs. This patch add sbasic support for the platform.
s/2080/2085/
> diff --git a/board/freescale/ls2085aqds/Makefile
> b/board/freescale/ls2085ardb/Makefile
> similarity i
On Fri, 2015-03-20 at 10:35 +0100, Albert ARIBAUD wrote:
> Hi Scott,
>
> Le Thu, 19 Mar 2015 16:39:42 -0500, Scott Wood
> a écrit :
>
> > On Wed, 2015-03-18 at 10:04 +0100, Albert ARIBAUD (3ADEV) wrote:
> > > +int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
> > > +{
> > > +
On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote:
>
> On 03/20/2015 02:15 PM, Scott Wood wrote:
> > On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
> >> From: Scott Wood
> >>
> >> This adds NAND boot support for LS2085AQDS, using SPL framework.
> >>
> >> To form a NAND image, append u-boot-wi
On Fri, 2015-03-20 at 17:37 -0400, Tom Rini wrote:
> On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
>
> [snip]
> > It would also be nice to sort out loading the environment during SPL.
>
> *ears perk up*. Please elaborate :) We have SPL environment support,
> we have SPL NAND Envir
On 03/20/2015 02:33 PM, Scott Wood wrote:
> On Fri, 2015-03-20 at 14:23 -0700, York Sun wrote:
>>
>> On 03/20/2015 02:15 PM, Scott Wood wrote:
>>> On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
From: Scott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework.
>
On Fri, Mar 20, 2015 at 04:15:40PM -0500, Scott Wood wrote:
[snip]
> It would also be nice to sort out loading the environment during SPL.
*ears perk up*. Please elaborate :) We have SPL environment support,
we have SPL NAND Environment support today. It doesn't get passed along
to the running
On 03/20/2015 02:15 PM, Scott Wood wrote:
> On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
>> From: Scott Wood
>>
>> This adds NAND boot support for LS2085AQDS, using SPL framework.
>>
>> To form a NAND image, append u-boot-with-spl.bin after a proper
>> nand boot RCW and flash to the beginn
On Fri, 2015-03-20 at 12:21 -0700, York Sun wrote:
> From: Scott Wood
>
> This adds NAND boot support for LS2085AQDS, using SPL framework.
>
> To form a NAND image, append u-boot-with-spl.bin after a proper
> nand boot RCW and flash to the beginning of NAND.
Do we want to do it this way, or sho
Hi Joe,
On 20 March 2015 at 13:18, Joe Hershberger wrote:
> Hi Simon,
>
> On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>>
>> This series adds a new ethernet driver for the GMAC found on Intel
>> Topcliff
>> Platform Controller Hub and enable its support on Intel Crown Bay board.
>>
>> The se
Hi,
Thanks for the patch, I've 1 comment inline, please send
a version with that fixed then I'll queue it up for merging upstream.
On 18-03-15 20:46, Paul Kocialkowski wrote:
Signed-off-by: Paul Kocialkowski
---
board/sunxi/board.c| 33 ++---
include/
From: Scott Wood
Enable NAND boot support using SPL framework. To boot from
NAND, either use DIP switches on board, or "qixis_reset nand"
command.
Signed-off-by: Scott Wood
Singed-off-by: York Sun
---
Changes in v4:
Update MAINTAINERS file
Changes in v3: None
Changes in v2: None
arch/ar
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v4:
Re
From: Scott Wood
This adds NAND boot support for LS2085AQDS, using SPL framework.
To form a NAND image, append u-boot-with-spl.bin after a proper
nand boot RCW and flash to the beginning of NAND.
Signed-off-by: Scott Wood
Signed-off-by: York Sun
---
Changes in v4:
Update MAINTAINERS file
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>
> Intel Crown Bay board has one ethernet port connected from Intel
> Topcliff PCH. Enable it in the board configuration.
>
> Signed-off-by: Bin Meng
>
> ---
Reviewed-by: Joe Hershberger
___
U-Boot mai
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>
> Add a new driver for the Gigabit Ethernet MAC found on Intel Topcliff
> Platform Controller Hub. Tested under 10/100 half/full duplex and 1000
> full duplex modes using ping and tftpboot commands.
>
> Signed-off-by: Bin Meng
> ---
Acked-by: Jo
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>
> README.drivers.eth still refers to the deprecated miiphy_register().
> Update the doc to mention new APIs mdio_alloc() and mdio_register().
>
> Signed-off-by: Bin Meng
> ---
Acked-by: Joe Hershberger
__
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>
> Some ethernet drivers use their own version of ethernet FCS length
> macro which is really common. We define ETH_FCS_LEN in net.h and
> replace those custom versions in various places.
>
> Signed-off-by: Bin Meng
> ---
Acked-by: Joe Hershberge
Hi Simon,
On Fri, Mar 20, 2015 at 4:12 AM, Bin Meng wrote:
>
> This series adds a new ethernet driver for the GMAC found on Intel
Topcliff
> Platform Controller Hub and enable its support on Intel Crown Bay board.
>
> The series also did some clean up work below:
> - Introduce ETH_FCS_LEN macro a
On 03/20/2015 11:29 AM, Mark Rutland wrote:
>> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
>> b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
>> index ce9c0c1..5338fe6 100644
>> --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
>> +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
>> @@ -30,6 +30,13 @@ int fsl_lsch3_wake_sec
On 3/19/2015 6:51 PM, peng@freescale.com wrote:
> Hi, Andrew
>
> There is already a patch to fix this issue.
> Patchwork: https://patchwork.ozlabs.org/patch/451775/
>
> Regards,
> Peng.
>
> -Original Message-
> From: U-Boot [mailto:u-boot-boun...@lists.denx.de] On Behalf Of Andrew
>
Hi Thierry,
On Fri, Mar 20, 2015 at 6:41 AM, Thierry Reding
wrote:
>
> From: Thierry Reding
>
> Turn ioaddr into an unsigned long rather than a sized 32-bit variable.
> While at it, fix a couple of pointer to integer cast size mismatch
> warnings by casting through unsigned long going from point
> diff --git a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> index ce9c0c1..5338fe6 100644
> --- a/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> +++ b/arch/arm/cpu/armv8/fsl-lsch3/mp.c
> @@ -30,6 +30,13 @@ int fsl_lsch3_wake_seconday_cores(void)
> u32 cores, cpu_up_mask = 1
On 03/20/2015 11:09 AM, Tom Rini wrote:
On Fri, Mar 20, 2015 at 10:26:12AM -0600, Stephen Warren wrote:
On 03/20/2015 06:24 AM, Thierry Reding wrote:
From: Thierry Reding
For 64-bit ARM SoCs we rely on non-U-Boot code to bring up the CPU in
AArch64 mode so that we don't need the SPL. Non-cach
> >> +int timer_init(void)
> >> +{
> >> + u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR;
> >> + u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR;
> >> +#ifdef COUNTER_FREQUENCY_REAL
> >> + unsigned long cntfrq = COUNTER_FREQUENCY_REAL;
> >> +
> >> + /* Update with accurate clock
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> Some SoCs come with a custom timer interface, so allow them to use that
> instead.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-off-by: Thierry Reding
> ---
> arch/arm/cpu/armv8/generic_timer.c | 2 ++
> 1 file changed
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> For EL3 and EL2, the documentation says that bits 31 and 23 are reserved
> but should be written as 1.
>
> For EL1, only bit 23 is not reserved, so only write bit 31 as 1.
>
> Cc: Albert Aribaud
> Cc: Marc Zyngier
> Signed-of
Hi Codrin,
On Wed, Mar 4, 2015 at 2:46 AM, Codrin Constantin Ciubotariu <
codrin.ciubota...@freescale.com> wrote:
>
> Hi,
>
> Anyone has any comments on this? Please share your thoughts.
Looks good to me.
> > -Original Message-
> > From: Codrin Ciubotariu [mailto:codrin.ciubota...@freesc
The timer clock is system clock divided by 4, not fixed 12MHz.
This is common to the SoC, not board specific. Primary core is
fixed when u-boot still runs in board_f. Secondary cores are
fixed by reading a variable set by u-boot.
Signed-off-by: York Sun
CC: Mark Rutland
---
Changes in v3:
Mo
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> Use the inner shareable attribute for memory, which makes more sense
> considering that this code is called when caches are being enabled.
>
> While at it, fix the values for the shareability attribute field to
> match the docum
On 20/03/15 11:47, Thierry Reding wrote:
> From: Thierry Reding
>
> While generating the page tables, a running integer index is shifted by
> SECTION_SHIFT (29) and causes overflow for any integer bigger than 7.
> The page tables therefore alias to the same 8 sections and cause U-Boot
> to hang o
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