Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN
to Kconfig), the ".config" created by the configuration has been
wrong.
For example, the following is a snippet of the ".config" generated
by "make beaver_defconfig":
--->8-
CONFIG_CC_OPTIMIZE_FOR
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada
---
Changes in v2: None
arch/arm/cpu/armv7/uniphier/Kconfig | 2 +-
1 file chang
Masahiro Yamada (4):
ARM: UniPhier: set CONFIG_SYS_MALLOC_F to the global default value
malloc_f: fix broken .config caused by CONFIG_SYS_MALLOC_F
kconfig: switch to single .config configuration
kconfig: remove unneeded dependency on !SPL_BUILD
Kconfig |
When Kconfig for U-boot was examined, one of the biggest issues was
how to support multiple images (Normal, SPL, TPL). There were
actually two options, "single .config" and "multiple .config".
After some discussions and thought experiments, I chose the latter,
i.e. to create ".config", "spl/.confi
Now CONFIG_SPL_BUILD is not defined in Kconfig, so
"!depends on SPL_BUILD" arn "if !SPL_BUILD" are redundant.
Signed-off-by: Masahiro Yamada
---
Kconfig | 12 ++--
arch/arm/Kconfig| 7 +++
arch/arm/cpu/arm1176/bcm2835/Kconfig
Since commit b724bd7d6349 (dm: Kconfig: Move CONFIG_SYS_MALLOC_F_LEN
to Kconfig), the ".config" created by the configuration has been
wrong.
For example, the following is a snippet of the ".config" generated
by "make beaver_defconfig":
--->8-
CONFIG_CC_OPTIMIZE_FOR
It is true that malloc is necessary for Driver Model before
relocation, but there is no good reason to reserve the malloc
space more than enough. The default value 0x400 works well.
Signed-off-by: Masahiro Yamada
---
arch/arm/cpu/armv7/uniphier/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1
Hello Simon,
Am 18.02.2015 22:10, schrieb Simon Glass:
This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass
---
drivers/i2c/i2c-uclass.c | 2 ++
1 file changed, 2 insertions(+)
Good catch, Thanks!
Acked-by: Heiko Schocher
bye,
Heiko
diff --git a/drivers/i2c/i2c-uclas
On 02/17/2015 01:22 PM, Tom Rini wrote:
> On Tue, Feb 17, 2015 at 12:35:41PM -0700, Stephen Warren wrote:
>> On 02/16/2015 06:03 PM, Tom Rini wrote:
>>> On Mon, Feb 16, 2015 at 12:16:15PM -0700, Stephen Warren
>>> wrote:
>>>
USB doesn't seem to work yet; the controller detects the
on-boa
On Wed, Feb 18, 2015 at 12:20:25AM +0100, Andreas Bießmann wrote:
> Hi Tom,
>
> reworked pull request for avr32 generic board support.
>
> The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
>
> Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
>
> a
On Wed, Feb 18, 2015 at 06:09:28AM -0700, Simon Glass wrote:
> Hi Tom,
>
> The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
>
> Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
>
> are available in the git repository at:
>
> http://git.denx.de/
Hi Marek,
On 18 February 2015 at 14:36, Marek Vasut wrote:
> Enable DM in case these two drivers are enabled, since these
> two drivers depend on DM.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Stefan Roese
> Cc: Tom Rini
> ---
> include/configs/socfpga_common.h | 4
> 1 file
On 18 February 2015 at 14:36, Marek Vasut wrote:
>
> Since device_unbind() is also defined in device-remove.c,
> which is compiled in only in case CONFIG_DM_DEVICE_REMOVE
> is defined, protect the device_unbind() prototype with the
> same CONFIG_DM_DEVICE_REMOVE check.
>
> Signed-off-by: Marek Vas
Hi Stefano,
On 19.02.2015 00:08, Stefano Babic wrote:
> Hi Soeren,
>
> On 18/02/2015 16:43, Soeren Moch wrote:
>>> According to the i.MX6Q Reference Manual, clocks must be gated when
>>> switching input clocks of async clock muxes. So use clock gates. Avoid
>>> ldb_di0_ipu clock, because there is
Hi Soeren,
On 18/02/2015 16:43, Soeren Moch wrote:
>> According to the i.MX6Q Reference Manual, clocks must be gated when
>> switching input clocks of async clock muxes. So use clock gates. Avoid
>> ldb_di0_ipu clock, because there is no clock gate for this signal.
>>
>> There have never been any
Hi Tom,
On Wed, Feb 18, 2015 at 10:32 AM, Tom Rini wrote:
> Well, the best answer is to check the TRM and see what it says about the
> ROM memory map. My recollection is that 0x40200800 - 0x4020BBFF is the
> download area and 0x4020E000 - 0x4020FFFC is what it calls the public
> stack and we deci
Fastboot oem command is updated with SPI specific functionality.
Signed-off-by: Dileep Katta
---
Note: This is on top of Rob Herring patches submitted to support oem format
command
Ref: https://patchwork.ozlabs.org/patch/433056/
https://patchwork.ozlabs.org/patch/433057/
dr
This adds the functionality to flash u-boot and MLO images to QSPI using
fastboot
Signed-off-by: Dileep Katta
---
Note: This is on top of Rob Herring patches submitted to support oem format
command
drivers/usb/gadget/f_fastboot.c | 75 +
1 file changed,
On Wednesday, February 18, 2015 at 04:04:07 AM, Tom Rini wrote:
> On Tue, Feb 17, 2015 at 09:11:01PM +0100, Marek Vasut wrote:
> > Hi Tom,
> >
> > SoCFPGA stuff for current release.
> >
> > The following changes since commit 7f641d53bbb3a426a3bfb132d8346153e86a9d08:
> > Merge branch 'master' of
Since device_unbind() is also defined in device-remove.c,
which is compiled in only in case CONFIG_DM_DEVICE_REMOVE
is defined, protect the device_unbind() prototype with the
same CONFIG_DM_DEVICE_REMOVE check.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Stefan Roese
Cc: Tom Rini
---
inclu
Enable DM in case these two drivers are enabled, since these
two drivers depend on DM.
Signed-off-by: Marek Vasut
Cc: Simon Glass
Cc: Stefan Roese
Cc: Tom Rini
---
include/configs/socfpga_common.h | 4
1 file changed, 4 insertions(+)
diff --git a/include/configs/socfpga_common.h b/inclu
This device sits on the sandbox PCI bus and provides a case-swapping
service for sandbox. It illustrates the use of both PCI I/O and PCI
memory accesses.
Signed-off-by: Simon Glass
---
drivers/misc/Makefile| 1 +
drivers/misc/swap_case.c | 285 +
Some uclasses want to set up a device before it is probed. Add a method
for this.
An example is with PCI, where a PCI uclass wants to set up its private
data for later use. This allows the device's uclass() method to make calls
whcih use that data (for example, read PCI memory regions from device
At present we do more in this function than we should. Create a new
x86_post_cpu_init() which can be called from the board file when needed
(e.g. in board_early_init_f(). This allows us to use driver model for
our x86_post_cpu_init() function.
It is likely that some future refactoring will improve
Add a simple x86 PCI driver which uses standard functions provided by the
architecture.
Signed-off-by: Simon Glass
---
arch/x86/cpu/pci.c | 40
arch/x86/include/asm/pci.h | 8
arch/x86/lib/Makefile | 2 ++
drivers/pci/Makefile
Move chromebook_link over to driver model for PCI.
This involves:
- adding a uclass for platform controller hub
- removing most of the existing PCI driver
- adjusting how CPU init works to use driver model instead
- rename the lpc compatible string (it will be removed later)
This does not really
At present the device is not active when the probe() method is called. But
some probe() methods want to set up the device and this can involve
accessing it through normal methods. For example a PCI bus may wish to
set up its PCI parameters using calls to pci_hose_write_config_dword() and
similar.
Add the required header information, device tree nodes and I/O accessor
functions to support PCI on sandbox. All devices are emulated by drivers
which can be added as required for testing or development.
Signed-off-by: Simon Glass
---
arch/sandbox/Kconfig | 7 ++
arch/san
Add a driver which can access emulations of devices and make them available
in sandbox.
Signed-off-by: Simon Glass
---
drivers/pci/Kconfig | 10 ++
drivers/pci/Makefile | 1 +
drivers/pci/pci_sandbox.c | 79 +++
3 files changed, 90 ins
Enable PCI options so that sandbox can be used for testing this bus with
driver model.
Signed-off-by: Simon Glass
---
configs/sandbox_defconfig | 3 +++
include/configs/sandbox.h | 4
2 files changed, 7 insertions(+)
diff --git a/configs/sandbox_defconfig b/configs/sandbox_defconfig
index
These functions currently use a generic name, but they are for x86 only.
This may introduce confusion and prevents U-Boot from using these names
more widely.
In fact it should be possible to remove these at some point and use
generic functions, but for now, rename them.
Signed-off-by: Simon Glass
Add a convenience function to access the private data that a uclass stores
for each of its devices. Convert over most existing uses for consistency
and to provide an example for others.
Signed-off-by: Simon Glass
---
common/cmd_sf.c| 2 +-
common/cros_ec.c | 2 +-
Add some basic tests to check that things work as expected with sandbox.
Signed-off-by: Simon Glass
---
test/dm/Makefile | 1 +
test/dm/pci.c| 59
test/dm/test.dts | 17
3 files changed, 77 insertions(+)
create mode
Since sandbox does not have real devices (unless it borrows those from the
host) it must use emulations. Provide a uclass which permits PCI operations
to be passed through to an emulation device.
Signed-off-by: Simon Glass
---
drivers/pci/Makefile | 1 +
drivers/pci/pci-emul-uclass.c
This function does not unmap what it maps. Correct it.
Signed-off-by: Simon Glass
---
common/cmd_mem.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/common/cmd_mem.c b/common/cmd_mem.c
index bcb3ee3..855aa57 100644
--- a/common/cmd_mem.c
+++ b/common/cmd_mem.c
@@ -1
Both of these values are useful for understanding what is going on, so show
them both.
The requested number comes from a device tree alias. The allocated one is
set up when the device is activated, and is unique throughout the uclass.
Signed-off-by: Simon Glass
---
test/dm/cmd_dm.c | 4 ++--
1
Move coreboot-x86 over to driver model for PCI.
Signed-off-by: Simon Glass
---
arch/x86/cpu/coreboot/pci.c | 63 ++---
arch/x86/dts/chromebook_link.dts| 7 +
board/google/chromebook_link/link.c | 9 ++
configs/coreboot-x86_defconfig |
Add a uclass for PCI controllers and a generic one for PCI devices. Adjust
the 'pci' command and the existing PCI support to work with this new uclass.
Keep most of the compatibility code in a separate file so that it can be
removed one day.
TODO: Add more header file comments to the new parts of
This function returns -ENOENT when the property is missing (which the caller
might forgive) and also when the property is present but incorrectly
formatted (which many callers would like to report).
Update the error return value to allow these different situations to be
distinguished.
Signed-off-
This function is missing a prototype but is more widey useful. Add it.
Signed-off-by: Simon Glass
---
include/fdtdec.h | 11 +++
lib/fdtdec.c | 2 +-
2 files changed, 12 insertions(+), 1 deletion(-)
diff --git a/include/fdtdec.h b/include/fdtdec.h
index 1bc70db..2a96a0a 100644
---
Driver model will share many functions with the existing PCI implementation.
Move these into their own file to avoid duplication and confusion.
Signed-off-by: Simon Glass
---
drivers/pci/Makefile | 2 +-
drivers/pci/pci.c| 281 +
drivers
These are missing a size value. Add one in each case.
Signed-off-by: Simon Glass
---
arch/sandbox/dts/sandbox.dts | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/sandbox/dts/sandbox.dts b/arch/sandbox/dts/sandbox.dts
index 9ce31bf..1ccfdee 100644
--- a/arch/sandbox/
This strdup() is missing a check. Add it.
Signed-off-by: Simon Glass
---
drivers/i2c/i2c-uclass.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/i2c/i2c-uclass.c b/drivers/i2c/i2c-uclass.c
index a6991bf..b890806 100644
--- a/drivers/i2c/i2c-uclass.c
+++ b/drivers/i2c/i2c-uclass.c
This series is a collection of changes in core DM, sandbox, x86 and PCI code
to implement a PCI uclass and associated operations. Some basic tests are
provided as well.
As is becoming common with DM conversions, the existing structure (here
struct pci_controller) becomes per-bus uclass data. This
From: Stephen Warren
This is needed to correctly apply the new Jetson TK1 pinmux config.
Signed-off-by: Stephen Warren
---
v2:
* Use clrbits_le32() rather than open-code read/modify/write statements.
* Update pinmux_set_tristate_input_clamping to match.
---
arch/arm/cpu/tegra-common/pinmux-com
From: Stephen Warren
Syseng has revamped the Jetson TK1 pinmux spreadsheet, basing the content
completely on correct configuration for the board/schematic, rather than
the previous version which was based on the bare minimum changes relative
to another reference board.
The new spreadsheet sets T
The 'nandecc sw' command selects a software-based error correction
algorithm. By default, this is OMAP_ECC_HAM1_CODE_SW but some
platforms use OMAP_ECC_BCH8_CODE_HW_DETECTION_SW as their
software-based correction algorithm. Allow a user to be specific e.g.
# nandecc sw
where 'hamming' is still
This patch adds functionality to getvar command to get the userdata partition
size.
Signed-off-by: Dileep Katta
---
common/fb_mmc.c | 38 ++
drivers/usb/gadget/f_fastboot.c | 2 ++
include/fb_mmc.h| 2 ++
3 files changed, 42 i
Had a conversation with Ash @ Gumstix and he pointed out relying on
CONFIG_NAND_OMAP_ECCSCHEME could be dangerous as it could be anything other
than the two SW ECC schemes available for OMAP3.
Also it looks like making a selection between OMAP_ECC_BCH8_CODE_HW and
OMAP_ECC_BCH8_CODE_HW_DETECTION_S
On Tue, Feb 17, 2015 at 08:22:17PM -0700, Simon Glass wrote:
> +tom, and pruning the cc list a little
>
> Hi,
>
> On 26 January 2015 at 18:27, Simon Glass wrote:
> > This series adds debug UART infrastructure which can in principle be used on
> > any architecture. It works best with those that
On Tue, Feb 17, 2015 at 04:47:14PM -0800, Adam Lee wrote:
> I have a Gumstix Overo (OMAP3) with a 512MiB NAND. I have been validating
> BCH8 ecc scheme and one of the problems I ran into is this:
>
> arm-linux-gnueabi-ld.bfd: u-boot-spl section `.rodata' will not fit in
> region `.sram'
> arm-linu
I am trying to bring up xen suing u-boot that has this patch. Unfortunately as
soon as the code tries to call _nonsec_init through secure_ram_addr in
arm7_init_nonsec function in virt-v7.c I get an undefined instruction
exception. I suspect the CONFIG_ARMV7_SECURE_BASE needs to be defined to a
Hello Rob,
On 01/26/2015 04:43 PM, Rob Herring wrote:
The gpt command always reports success even if writing the partition table
failed. Propagate the return value of gpt_restore so we get proper status
reported.
Signed-off-by: Rob Herring
---
common/cmd_gpt.c | 4 ++--
1 file changed, 2 in
Hello Rob,
Sorry for delay.
On 01/26/2015 04:44 PM, Rob Herring wrote:
Currently, an environment variable must be used to store the randomly
generated UUID for each partition. This is not necessary, so make storing
the UUID optional. Now passing uuid_disk and uuid are optional when random
UUIDs
Hi Andreas, for OMAP3 and AM35xx boards, it would have been ok omitting the
CONFIG_BCH check and simply use CONFIG_NAND_OMAP_ECCSCHEME.
Those boards use the ecc scheme config already. However I just wasn't 100%
sure if I could rely on this config for all TI OMAP/AM based boards. I know
OMAP3
and A
Hi,
Here's what I think happens:
When working with large TFTP packets (probably 4096 bytes, as set in
your board config file), U-Boot TFTP code sends wrong acknowledges for
the TFTP packets. If the TFTP server implementation is too strict (the
OpenBSD server is a good example), the transfer will
On 02/17/2015 10:01 PM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull mode is not defined
On 02/17/2015 11:13 PM, Jan Kiszka wrote:
On 2015-02-17 22:03, Stephen Warren wrote:
On 02/16/2015 05:54 AM, Jan Kiszka wrote:
This is based on Thierry Reding's work and uses Ian Campell's
preparatory patches. It comes with full support for CPU_ON/OFF PSCI
services. The algorithm used in this v
>Are you saying that it is completely consistent that when TFTPing from a specific TFTP
server to u-boot you always get these time-outs, but with a different one you never get them?
Exactly. Even when I try to download uImage from kvm host machine, I still got timeouts.
But should I try to downlo
According to the i.MX6Q Reference Manual, clocks must be gated when
switching input clocks of async clock muxes. So use clock gates. Avoid
ldb_di0_ipu clock, because there is no clock gate for this signal.
There have never been any complaints about problems with the old code,
but the new approach
On Wed, Feb 18, 2015 at 7:12 AM, Vitaly Andrianov wrote:
>
>
> On 02/17/2015 05:47 PM, Nishanth Menon wrote:
>>
>> On Tue, Feb 17, 2015 at 4:27 PM, Murali Karicheri
>> wrote:
>
> is complete the boot-loader sets the PC to the first MSMC address
> 0x0c00. The u-boot.bin is linked t
Hello,
The documentation [1] for the AM335x defines a manual process for UART
booting as including the steps...
When '' appear select XMODEM -> Send "u-boot-spl.bin", and then...
When '' appear select YMODEM -> Send "u-boot.img"
Is there a pre-existing tool or script around that will au
Hi,
On 18-02-15 10:21, Ian Campbell wrote:
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede
All 4 patches: Acked-by: Ian Campbell
Thanks for the revie
p.s.
On 18-02-15 10:21, Ian Campbell wrote:
On Mon, 2015-02-16 at 23:25 +0100, Hans de Goede wrote:
Add support for the 6" 480x800 tl059wv5c0 panel used on e.g. Utoo P66 and
Aigo M60/M608/M606 tablets.
Signed-off-by: Hans de Goede
All 4 patches: Acked-by: Ian Campbell
Pushed to u-boot-su
Hi Adam,
On 02/18/2015 03:58 AM, Adam YH Lee wrote:
> The ECC scheme selection algorithm in OMAP GPMC appears to be left untested
> when
> BCH8 handling code was added. Running 'nandecc sw' defaults to HAM1 even if
> the board is using another scheme (ex. OMAP_ECC_BCH8_CODE_HW_DETECTION_SW on
> O
Hi Simon,
On Thu, 2015-02-05 at 21:41 -0700, Simon Glass wrote:
> +config SYS_MALLOC_F
> + bool "Enable malloc() pool before relocation"
> + default 0x400
I'm wondering if default value here should be of type "bool" but not a
hex value?
Probably this is just a copy paste from the followi
Hi Simon,
On Wed, Feb 18, 2015 at 6:45 PM, Simon Glass wrote:
> +mailing list
>
> On 18 February 2015 at 06:14, Simon Glass wrote:
>> Hi Vivek,
>>
>> On 18 February 2015 at 03:40, Vivek Gautam wrote:
>>> Hi Marek, Simon,
>>>
>>> This patch-series comes as a update for an earlier posted series[
Hi Tom,
On Wed, 2015-02-18 at 15:35 +0300, Alexey Brodkin wrote:
> Hi Tom,
>
> Could you please pull those changes?
Just realized you already pulled my the changes.
Probably I missed your reply and was too lazy to check latest changes in
U-Boot at say http://git.denx.de/?p=u-boot.git;a=shortlog
+mailing list
On 18 February 2015 at 06:14, Simon Glass wrote:
> Hi Vivek,
>
> On 18 February 2015 at 03:40, Vivek Gautam wrote:
>> Hi Marek, Simon,
>>
>> This patch-series comes as a update for an earlier posted series[1]
>> "[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host suppo
On 02/17/2015 05:47 PM, Nishanth Menon wrote:
On Tue, Feb 17, 2015 at 4:27 PM, Murali Karicheri wrote:
is complete the boot-loader sets the PC to the first MSMC address
0x0c00. The u-boot.bin is linked to the address 0x0c001000.
why not just shift u-boot.bin to start of MSMC address?
Hi Tom,
The following changes since commit 5745f8c4fd5807becf7f246625e153388293aedc:
Merge git://git.denx.de/u-boot-marvell (2015-02-16 08:44:03 -0500)
are available in the git repository at:
http://git.denx.de/u-boot-fdt.git
for you to fetch changes up to c71a0164d9b23e624552fb614bcb426a1
Hello Stephen,
On 02/17/2015 11:39 PM, Stephen Warren wrote:
On 02/17/2015 02:43 PM, Stephen Warren wrote:
On 02/16/2015 08:13 AM, Przemyslaw Marczak wrote:
This patchset reduces the boot time for ARM architecture,
Exynos boards, and boards with DFU enabled.
I tested this series on NVIDIA's
Hello Simon,
On 02/18/2015 05:32 AM, Simon Glass wrote:
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
Reduce the boot time of Odroid X2/U3 by disabling the memset
at malloc init.
This was tested on Odroid X2.
A quick test with checking gpio pin state using the oscilloscope.
Boot tim
Hi Simon,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
Signed-off-by: Przemyslaw Marczak
---
Kconfig | 26 +++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/Kconfig b/Kconfig
index
Hi Tom,
On Fri, 2015-02-13 at 09:23 +0300, Alexey Brodkin wrote:
> Dear Tom,
>
> The following changes since commit
> bd2a4888b123713adec271d6c8040ca9f609aa2f:
>
> sunxi: configs/sunxi-common.h: Enable CONFIG_CMD_PART (2015-02-11
> 19:43:45 -0500)
>
> are available in the git repository at:
>
Hello,
On 02/18/2015 05:32 AM, Simon Glass wrote:
Hi Przemyslaw,
On 16 February 2015 at 08:21, Przemyslaw Marczak wrote:
Hello,
On 02/16/2015 04:13 PM, Przemyslaw Marczak wrote:
For ARM architecture, enable the CONFIG_USE_ARCH_MEMSET/MEMCPY,
will highly increase the memset/memcpy performa
Hello,
I have a Samsung Exynos 5420 Arndale Octa Board and I am trying to run Xen
4.5 on it.
I have successfully managed to configure and patch XEN and the kernel for
the board.
The problem is that XEN doesn't match the correct CPU mode for its boot.
-XEN early debug-
Hello,
On 02/18/2015 05:23 AM, Simon Glass wrote:
On 16 February 2015 at 08:13, Przemyslaw Marczak wrote:
This commit enables the following configs:
- CONFIG_USE_ARCH_MEMCPY
- CONFIG_USE_ARCH_MEMSET
This increases the performance of memcpy/memset
and also reduces the boot time.
This was teste
Hello,
>On Wed, 18 Feb 2015 15:16:27 +0530
>Akshay Saraswat wrote:
>
>> This patch adds workaround for ARM errata 798870 which says
>> "If back-to-back speculative cache line fills (fill A and fill B) are
>> issued from the L1 data cache of a CPU to the L2 cache, the second
>> request (fill B) is
Hi Lukasz,
>Hi Akshay,
>
>> This patch adds code to shutdown secondary cores.
>> When U-boot comes up, all secondary cores appear powered on,
>> which is undesirable and causes side effects while
>> initializing these cores in kernel.
>>
>> Secondary core power down happens in following steps:
>>
Hi Akshay,
> This patch adds code to shutdown secondary cores.
> When U-boot comes up, all secondary cores appear powered on,
> which is undesirable and causes side effects while
> initializing these cores in kernel.
>
> Secondary core power down happens in following steps:
>
> Step-1: After Exy
On Wed, 18 Feb 2015 15:16:28 +0530
Akshay Saraswat wrote:
> This patch adds workaround for the ARM errata 799270 which says
> "If the L2 cache logic clock is stopped because of L2 inactivity,
> setting or clearing the ACTLR.SMP bit might not be effective. The bit is
> modified in the ACTLR, meani
On Wed, 18 Feb 2015 15:16:27 +0530
Akshay Saraswat wrote:
> This patch adds workaround for ARM errata 798870 which says
> "If back-to-back speculative cache line fills (fill A and fill B) are
> issued from the L1 data cache of a CPU to the L2 cache, the second
> request (fill B) is then cancelled
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull modes are defined by proper enum and can be:
- UP
- DOWN
- NONE
- UNKNOWN
Signed-off-by: Przemyslaw Marczak
CC: Simon Glass
Reviewed-by: Simon Glass
---
Changes v2:
- add enum wit
Depending on the boot priority, the eMMC/SD cards,
can be initialized with the same numbers for each boot.
To be sure which mmc device is SD and which is eMMC,
this info is printed by 'mmc list' command, when
the init is done.
Signed-off-by: Przemyslaw Marczak
Cc: Pantelis Antoniou
Reviewed-by:
The dw mmc driver init priority was always the same: ch 0, ch 1, ch 2.
On some boards (e.g. Odroid XU3) the dwmmc driver is enabled for all
mmc channels. In this case, when boot device is switchable (SD/eMMC),
the default MMC device will be 0 or 1.
Change the init priority to boot device, always in
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibility to boot from more then one device,
the CONFIG_SYS_MMC_ENV_DEV should always point to right mmc device.
This can be achieved by i
Hello Simon,
On 02/18/2015 06:02 AM, Simon Glass wrote:
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
Before this commit, the mmc devices were always registered
in the same order. So dwmmc channel 0 was registered as mmc 0,
channel 1 as mmc 1, etc.
In case of possibil
This commit adds implementation of driver model gpio pull
setting to s5p gpio driver.
Signed-off-by: Przemyslaw Marczak
Cc: Simon Glass
Cc: Minkyu Kang
Reviewed-by: Simon Glass
---
Changes v2:
- adjust code after added gpio pull enum to gpio api
---
drivers/gpio/s5p_gpio.c | 28 +
Hello,
On 02/18/2015 06:01 AM, Simon Glass wrote:
+Stephen who might have an opinion on this.
Hi Przemyslaw,
On 17 February 2015 at 06:09, Przemyslaw Marczak wrote:
This commits extends:
- dm gpio ops by: 'set_pull' call
- dm gpio uclass by: dm_gpio_set_pull() function
The pull mode is not
Add devices for XHCI-HCD and EHCI-HCD in exynos5 family.
Signed-off-by: Vivek Gautam
---
arch/arm/dts/exynos5.dtsi |8
1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/exynos5.dtsi b/arch/arm/dts/exynos5.dtsi
index 238acb8..5cdf406 100644
--- a/arch/arm/dts/exynos5.dtsi
++
With driver model now we can enable both EHCI and XHCI on
Exynos5250.
Signed-off-by: Vivek Gautam
---
include/configs/exynos5-common.h|3 +++
include/configs/exynos5250-common.h |3 +++
include/configs/smdk5250.h |2 ++
3 files changed, 8 insertions(+)
diff --git a/incl
Adding a UCLASS driver for USB based on driver-model, to facilitate
binding mutiple host-controllers to their respective drivers, and
thereby enable using mutiple controllers simultaneously on a platform.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/Kconfig |9
drivers/usb/host
Adding support for driver model and necessary callbacks
in ohci/ehci/xhci.
Signed-off-by: Vivek Gautam
---
drivers/usb/host/ehci-hcd.c | 36
drivers/usb/host/ohci-hcd.c | 35 ---
drivers/usb/host/xhci.c | 34 +
Hi Marek, Simon,
This patch-series comes as a update for an earlier posted series[1]
"[PATCH RFC 0/2] usb: host: Add a wrapper layer for mutiple host support"
which was posted long back.
We had discussion to introduce the driver model instead of the approach used
in [1]. The driver model seems pr
Until yet usb_**_msg() APIs don't contain the string 'submit'.
Rename it to make things uniform. This is also helping while
adding a host translational layer wherein we are using
usb_submit_**_msg string to name APIs.
Signed-off-by: Vivek Gautam
---
common/usb.c |4 ++--
common/usb_k
Add wrapper functions for usb layer operations for control, bulk,
interrupt transfers to accomodate support for driver model.
Signed-off-by: Vivek Gautam
---
common/usb.c | 99
common/usb_hub.c |2 +-
include/dm/uclass-id.h |
On warm reset, all cores jump to the low_power_start function because iRAM
data is retained and because while executing iROM code all cores find
the jump flag 0x02020028 set. In low_power_start, cores check the reset
status and if true they clear the jump flag and jump back to 0x0.
The A7 cores do
From: Doug Anderson
It was found that the L2 cache timings that we had before could cause
freezes and hangs. We should make things more robust with better
timings. Currently the production ChromeOS kernel applies these
timings, but it's nice to fixup firmware too (and upstream probably
won't ta
This patch does 3 things:
1. Enables ECC by setting 21st bit of L2CTLR.
2. Restore data and tag RAM latencies to 3 cycles because iROM sets
0x3000400 L2CTLR value during switching.
3. Disable clean/evict push to external by setting 3rd bit of L2ACTLR.
We need to restore this here due to switc
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