Signed-off-by: Albert ARIBAUD (3ADEV)
---
Makefile | 3 +
scripts/Makefile.spl | 11
tools/.gitignore | 1 +
tools/Makefile| 2 +
tools/mklpc32xxboot.c | 169 ++
5 files changed, 186 insertions(+)
create mode
Signed-off-by: Albert ARIBAUD (3ADEV)
---
drivers/hwmon/Makefile | 1 +
drivers/hwmon/ds620.c | 64 ++
include/dtt.h | 15 ++--
3 files changed, 73 insertions(+), 7 deletions(-)
create mode 100644 drivers/hwmon/ds620.c
diff --g
Signed-off-by: Albert ARIBAUD (3ADEV)
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/spi/Makefile | 1 +
drivers/spi/lpc32xx_ssp.c
Work_92105 from Work Microwave is an LPC3250-
based board with the following features:
- 64MB SDR DRAM
- 1 GB SLC NAND, managed through MLC controller.
- Ethernet
- Ethernet + PHY SMSC8710
- I2C:
- EEPROM (24M01-compatible)
- RTC (DS1374-compatible)
- Temperature sensor (DS620)
- DACs (2 x
Signed-off-by: Albert ARIBAUD (3ADEV)
---
arch/arm/include/asm/arch-lpc32xx/gpio.h | 43 ++
drivers/gpio/Makefile| 1 +
drivers/gpio/lpc32xx_gpio.c | 223 +++
3 files changed, 267 insertions(+)
create mode 100644 arch/arm/inclu
The controller's Reed-Solomon ECC hardware is
used except of course for raw reads and writes.
It covers in- and out-of-band data together.
The SPL framework is supported.
Signed-off-by: Albert ARIBAUD (3ADEV)
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 6 +
arch/arm/include/asm/arch-
This series extends functionality for the LPC32xx platform and
introduces the WORK Microwave work_92105 board which makes use
of the extended functionality.
NOTES:
The series is not entirely checkpatch-clean. The following warnings
and checks were not fixed:
1. "warning: tools/mklpc32xxboot.c,81
Signed-off-by: Albert ARIBAUD (3ADEV)
---
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 11 ++
arch/arm/include/asm/arch-lpc32xx/clk.h | 4 +
arch/arm/include/asm/arch-lpc32xx/cpu.h | 2 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/i2c/Makefile
Signed-off-by: Albert ARIBAUD (3ADEV)
---
arch/arm/cpu/arm926ejs/lpc32xx/cpu.c | 9 +
arch/arm/cpu/arm926ejs/lpc32xx/devices.c | 7 +
arch/arm/include/asm/arch-lpc32xx/config.h| 3 +
arch/arm/include/asm/arch-lpc32xx/sys_proto.h | 1 +
drivers/net/Makefile
Hi, Bo
On 1/16/2015 1:27 PM, Bo Shen wrote:
Hi Josh,
On 01/16/2015 11:54 AM, Josh Wu wrote:
As the PMECC hardware has different version. In SAMA5D4 chip, the
PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we
a
On 15/01/15 22:41, Akshay Saraswat wrote:
> This patch adds code to shutdown secondary cores.
> When U-boot comes up, all secondary cores appear powered on,
> which is undesirable and causes side effects while
> initializing these cores in kernel.
>
> Secondary core power down happens in following
On 15/01/15 22:33, Akshay Saraswat wrote:
> This patch adds "iRAM, CPU state and low power" configs
> which are the addresses acting as flag registers.
>
> iROM code checks CONFIG_LOWPOWER_FLAG address. If it is equal
> to CONFIG_LOWPOWER_EN then it jumps to the address (0x0202+CPUID*4).
> Thi
Hi,
On 01/16/2015 02:48 PM, Akshay Saraswat wrote:
> We planned to fetch peripheral rate through one generic API per
> peripheral. These generic peripheral functions are in turn
> expected to fetch apt values from a function refactored as
> per SoC versions. This patch adds support for fetching pe
Removing dead code of peripheral and SoC specific function
implementations which was used for fetching peripheral clocks.
This code is not being used anymore because of the introduction
of generic clock_get_periph_rate function.
Signed-off-by: Akshay Saraswat
---
Changes since v2:
- No ch
Replacing SoC and peripheral specific function calls with generic
clock_get_periph_rate calls to get the peripheral clocks.
Signed-off-by: Akshay Saraswat
---
Changes since v2:
- No change.
Changes since v1:
- Separated exynos5_get_periph_rate fixes into another patch.
arch/arm
We planned to fetch peripheral rate through one generic API per
peripheral. These generic peripheral functions are in turn
expected to fetch apt values from a function refactored as
per SoC versions. This patch adds support for fetching peripheral
rates for Exynos5420 and Exynos5800.
Signed-off-by
Moving exynos5420_get_pll_clk function definition up in the
code to keep it together with rest of SoC_get_pll_clk functions.
This makes code more legible and also removes the need of
declaration when called before the position of definition in
code. Also, renaming exynos5420_get_pll_clk to
exynos54
Apparently, members of clk_bit_info array do not map correctly
to the members of enum periph_id. This mapping got broken after
we changed periph_id(s) to reflect interrupt number instead of
their position in a sequence. This patch intends to fix above
mentioned issue.
Signed-off-by: Akshay Saraswa
exynos5_get_periph_rate function reads incorrect div for
SDMMC2 & 3. It also reads prediv and does division only for
SDMMC0 & 2 when actually various other peripherals need that.
Adding changes to fix these mistakes in periph rate calculation.
Signed-off-by: Akshay Saraswat
---
Changes since v2:
This patch series does following changes -
1. Removing compiler warnings for clock_get_periph_rate.
2. Adding and enabling support for Exynos542x in
clock_get_periph_rate.
3. Replacing peripheral specific function calls with
clock_get_periph_rate.
4. Remove code from clocks file which became
From: Sonic Zhang
Signed-off-by: Sonic Zhang
---
include/configs/ip04.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/configs/ip04.h b/include/configs/ip04.h
index ec510bd..2ee215f 100644
--- a/include/configs/ip04.h
+++ b/include/configs/ip04.h
@@ -61,7 +61,7
From: Sonic Zhang
Signed-off-by: Sonic Zhang
---
include/configs/bct-brettl2.h |2 +-
include/configs/ibf-dsp561.h |2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/configs/bct-brettl2.h b/include/configs/bct-brettl2.h
index 39982ef..2e0e922 100644
--- a/in
Hi Josh,
On 01/16/2015 11:54 AM, Josh Wu wrote:
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-
On 15.01.2015 09:13, Masahiro Yamada wrote:
All the 74xx_7xx boards are still non-generic boards:
P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
Signed-off-by: Masahiro Yamada
Cc: Wolfgang Denk
Cc: Nye Liu
Cc: Roy Zang
Acked-by: Stefan Roese
Thanks,
Stefan
_
Hi Guys,
I'm looking at getting a dev board and JTAG debugger for ARM development
work. Does anyone have any suggestions on what are good options?
Regards,
Graeme
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-b
On Thursday, January 15, 2015 at 05:54:42 PM, York Sun wrote:
> On 01/15/2015 12:13 AM, Masahiro Yamada wrote:
> > All the 74xx_7xx boards are still non-generic boards:
> > P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
> >
> > Signed-off-by: Masahiro Yamada
> > Cc: Wolfgang Denk
> > Cc: Nye Liu
> > C
On Friday, January 16, 2015 at 05:50:18 AM, Stefan Roese wrote:
Hi!
> >> Would it make sense to make environment bigger (64K?) at this point,
> >> and enabling the redundant environment option, so that one bad block
> >> does not bring the whole device down?
> >
> > Do you think you'll ever have
Hi,
On 01/16/2015 01:58 PM, Joonyoung Shim wrote:
> Hi,
>
> On 01/15/2015 10:31 PM, Akshay Saraswat wrote:
>> We planned to fetch peripheral rate through one generic API per
>> peripheral. These generic peripheral functions are in turn
>> expected to fetch apt values from a function refactored as
As sama5d3 xplained support the PMECC. So add the PMECC header for spl
binary. That make ROM loader can use PMECC to avoid error flips in spl
code in nandflash.
Signed-off-by: Josh Wu
Acked-by: Bo Shen
---
include/configs/sama5d3_xplained.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/i
Hi,
On 01/15/2015 10:31 PM, Akshay Saraswat wrote:
> We planned to fetch peripheral rate through one generic API per
> peripheral. These generic peripheral functions are in turn
> expected to fetch apt values from a function refactored as
> per SoC versions. This patch adds support for fetching pe
On 15.01.2015 23:08, Marek Vasut wrote:
On Thursday, January 15, 2015 at 11:00:00 PM, Pavel Machek wrote:
diff --git a/include/configs/socfpga_common.h
b/include/configs/socfpga_common.h index 6b1f967..673377b 100644
--- a/include/configs/socfpga_common.h
+++ b/include/configs/socfpga_common.h
@
On 15.01.2015 09:10, Masahiro Yamada wrote:
Since commit 843125daebd7 (ppc4xx: remove HH405 board), CONFIG_HH405
is not defined.
Since commit d52633047913 (ppc4xx: remove PMC405), CONFIG_PMC405
is not defined.
Signed-off-by: Masahiro Yamada
Cc: Matthias Fuchs
Acked-by: Stefan Roese
Thanks
As the PMECC hardware has different version. In SAMA5D4 chip, the PMECC ip
can generate 0xff pmecc ECC value for all 0xff sector.
According to this, add PMECC version check, if it's SAMA5D4 then we always
let PMECC hardware to correct it.
Signed-off-by: Josh Wu
---
drivers/mtd/nand/atmel_nand
The commit 8dfafdd (Introduce common timer functions), add common
timer functions, we can use them directly.
Signed-off-by: Bo Shen
---
arch/arm/cpu/armv7/at91/timer.c | 61
arch/arm/include/asm/arch-at91/sama5d3.h | 3 ++
arch/arm/include/asm/arch-at9
As the at91cap9adk board is removed by commit: b5508344
(ARM: remove broken "at91cap9adk" board), so the at91cap9
code is not used anymore, and also the document for
at91cap9 can not be found on www.atmel.com, so remove the
at91cap9 related code.
Signed-off-by: Bo Shen
---
arch/arm/cpu/arm926ej
Supports boot up from NAND flash with software ECC eanbled.
And supports boot up from SD/MMC card with FAT file system.
As the boot from SD/MMC card with FAT file system, the BSS
segment is too big to fit into SRAM, so, use the lds to put
it into SDRAM. So, we need to initialize the SDRAM as soon
Hi,
On 01/15/2015 10:31 PM, Akshay Saraswat wrote:
> Apparently, members of clk_bit_info array do not map correctly
> to the members of enum periph_id. This mapping got broken after
> we changed periph_id(s) to reflect interrupt number instead of
> their position in a sequence. This patch intends
Hi,
On 01/15/2015 10:31 PM, Akshay Saraswat wrote:
> Moving exynos5420_get_pll_clk function definition up in the
> code to keep it together with rest of SoC_get_pll_clk functions.
> This makes code more legible and also removes the need of
> declaration when called before the position of definitio
Hi York,
Yes, I did it on purpose. T102XQDS is not supported in SDK1.7 anymore.
So I don't want to put more efforts to add SPI/NAND/SD boot deep sleep support.
That means t102xqds only supports nor-boot deep sleep and need not to update
spl.c.
It is the same case for T1040QDS.
Thanks,
Yuantian
Hi Stefano,
On 1/15/2015 5:00 PM, Przemyslaw Marczak wrote:
Hello Peg,
On 01/08/2015 02:00 PM, Peng Fan wrote:
This patch is to implement pmic_mode_init function, and add prototype
in header file.
This function is to set switching mode for pmic buck regulators to
improve system efficiency.
M
Hi, Przemyslaw
On 1/15/2015 10:58 PM, Przemyslaw Marczak wrote:
Hello Peng,
On 01/15/2015 11:18 AM, Peng Fan wrote:
This patch is to implement pfuze_mode_init and pfuze_regulator_mode_set
function, and add prototype in header file.
pfuze_mode_init is to set switching mode for all buck regulat
On Friday, January 16, 2015 at 01:07:55 AM, Dinh Nguyen wrote:
Hi!
> >>> which should be plenty, right? If moving the stack to SDRAM is really
> >>> needed, then you might want to use the common stack relocation code
> >>> (see relocate_code() function). Also, you should thoroughly describe
> >>>
On 01/15/2015 04:00 PM, Marek Vasut wrote:
> On Thursday, January 15, 2015 at 08:19:15 PM, Dinh Nguyen wrote:
>> Hi Marek,
>
> Hi Dinh,
>
>> On 01/14/2015 05:58 PM, Marek Vasut wrote:
>>> On Wednesday, January 14, 2015 at 05:40:55 PM,
>>> dingu...@opensource.altera.com
>>>
>>> wrote:
From: D
On 01/13/2015 12:45 PM, Ian Campbell wrote:
The secure world code is relocated to the MB just below the top of 4G, we
reserve it in the FDT (by setting CONFIG_ARMV7_SECURE_RESERVE_SIZE) but it is
not protected in h/w. See next patch.
diff --git a/include/configs/jetson-tk1.h b/include/configs/
On 01/13/2015 12:45 PM, Ian Campbell wrote:
In this case the secure code lives in RAM, and hence needs to be reserved, but
it has been relocated, so the reservation of __secure_start does not apply.
Add support for setting CONFIG_ARMV7_SECURE_RESERVE_SIZE to reserve such a
region.
This will be
On 01/13/2015 12:45 PM, Ian Campbell wrote:
I will need mc_security_cfg0/1 in a future patch and I added the rest while
debugging, so thought I might as well commit them.
diff --git a/arch/arm/include/asm/arch-tegra124/mc.h
b/arch/arm/include/asm/arch-tegra124/mc.h
@@ -35,9 +35,40 @@ struc
On 01/14/2015 09:12 AM, Vijay Rai wrote:
> T1040RDB_D4 board is a variant of T1040RDB(DDR3) board with DDR4 memory.
>
> Similarily T1042RDB_D4 is a variant of T1042RDB(DDR3) board with DDR4
> memory.
>
It is helpful to add what DDR4 DIMM has been tested here.
> Changes related
On Thursday, January 15, 2015 at 08:19:15 PM, Dinh Nguyen wrote:
> Hi Marek,
Hi Dinh,
> On 01/14/2015 05:58 PM, Marek Vasut wrote:
> > On Wednesday, January 14, 2015 at 05:40:55 PM,
> > dingu...@opensource.altera.com
> >
> > wrote:
> >> From: Dinh Nguyen
> >>
> >> Add a function to relocate th
On Thursday, January 15, 2015 at 11:00:00 PM, Pavel Machek wrote:
> Hi!
Hi!
> > From: Dinh Nguyen
> >
> > Signed-off-by: Dinh Nguyen
> > Cc: Marek Vasut
> > Cc: Tom Rini
> > Cc: Pavel Machek
> > ---
> >
> > include/configs/socfpga_common.h | 5 -
> > 1 file changed, 4 insertions(+), 1
Hi!
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_common.h
> index 673377b..0c87faa 100644
> --- a/include/configs/socfpga_common.h
> +++ b/include/configs/socfpga_common.h
> @@ -304,6 +304,7 @@ unsigned int cm_get_qspi_controller_clk_hz(void);
> #define CONFIG_SPL_
Hi!
> From: Dinh Nguyen
>
> Signed-off-by: Dinh Nguyen
> Cc: Marek Vasut
> Cc: Tom Rini
> Cc: Pavel Machek
> ---
> include/configs/socfpga_common.h | 5 -
> 1 file changed, 4 insertions(+), 1 deletion(-)
>
> diff --git a/include/configs/socfpga_common.h
> b/include/configs/socfpga_com
Hi!
> This patchset adds all the SPL code that is necessary to support the SoCFPGA
> platform. With this patch series, one should be able to configure the SDRAM
> controller and run u-boot.
>
> I have pushed a branch to git://git.rocketboards.org/u-boot-socfpga-next.git
> socfpga_for_next_spl_v1
Hi Simon, Masahiro-san,
On Thu, 2015-01-15 at 12:44 -0700, Simon Glass wrote:
> Hi Masahiro,
> > Honestly, I do not like baseline options in board-Kconfig very much.
> > The advantage is that it works without any change.
> >
> >
> > What I suggested before was to use scripts/kconfig/merge_config.s
On Mon, Jan 12, 2015 at 6:08 AM, Codrin Ciubotariu <
codrin.ciubota...@freescale.com> wrote:
>
> This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
> is integrated in Freescale T1040 and T1020 SoCs.
> The L2 switch has 10 Ethernet ports: 2 internal fixed-links
> (ports 8 and 9) at 2.5
On 01/12/2015 04:08 AM, Codrin Ciubotariu wrote:
> T1040 and T1020 are two Freescale SoCs with an integrated
> VSC9953 Gigabit L2 Switch. This patch initializes this L2
> switch on boards with T1040 and T1020.
>
> Signed-off-by: Codrin Ciubotariu
> ---
>
> Changes for v2:
> - added patch
Hi MAsahiro-san,
On Fri, 2015-01-16 at 03:36 +0900, Masahiro YAMADA wrote:
> Weird. I can access the link.
>
> The subject is
> [RFC] How to move lots of CONFIGs from header files to Kconfig
>
>
> Another URL is
> http://lists.denx.de/pipermail/u-boot/2014-October/193117.html
Thanks a lot! No
On 01/12/2015 04:08 AM, Codrin Ciubotariu wrote:
> This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
> is integrated in Freescale T1040 and T1020 SoCs.
> The L2 switch has 10 Ethernet ports: 2 internal fixed-links
> (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
> T
On 01/12/2015 04:08 AM, Codrin Ciubotariu wrote:
> This patch adds a driver for VSC9953 L2 Switch. This Vitesse IP
> is integrated in Freescale T1040 and T1020 SoCs.
> The L2 switch has 10 Ethernet ports: 2 internal fixed-links
> (ports 8 and 9) at 2.5 Gbps and and 8 external ports at 1 Gbps.
> The
On Thu 2015-01-15 10:26:36, Pali Rohár wrote:
> Generic board with #define CONFIG_SYS_GENERIC_BOARD is working fine.
> There is no visible difference between legacy and generic board code.
>
> Signed-off-by: Pali Rohár
Thanks!
Acked-by: Pavel Machek
(I added Albert Aribaud to the To: list, as
On 01/08/2015 09:13 PM, Alison Wang wrote:
> There 4 JRs, 4 RTICs and 8 DECOs, and set them the same stream id
> for using the same SMMU3 on LS1021A.
>
> Signed-off-by: Xiubo Li
> Signed-off-by: Alison Wang
> ---
> arch/arm/include/asm/arch-ls102xa/config.h | 1 +
> arch/arm/include/
On 01/06/2015 10:44 PM, Shaveta Leekha wrote:
> The code provides framework for heterogeneous multicore chips based on
> StarCore
> and Power Architecture which are chasis-2 compliant, like B4860 and B4420
>
> It will make u-boot recognize all non-ppc cores and peripherals like
> SC3900/DSP CPU
On Wed, 2015-01-14 at 19:16 +0530, Bhupesh Sharma wrote:
> This patch adds basic constructs in the ARMv8 u-boot code
> to handle and apply Cortex-A57 specific erratas.
>
> As and example, the framework showcases how erratas 833069, 826974
> and 828024 can be handled and applied.
>
> Later on this
Dear Tom,
The following changes since commit
28c4dae114c9b94b2ad81d4da716e9fc2cba:
Merge branch 'next' of git://git.denx.de/u-boot-video (2015-01-14
16:26:15 -0500)
are available in the git repository at:
git://git.denx.de/u-boot-arc.git
for you to fetch changes up to fdff23702a361e89
Hi,
On Mon, Jan 12, 2015 at 08:56:45PM +, Arnab Basu wrote:
> Implement core support for PSCI. As this is generic code, it doesn't
> implement anything really useful (all the functions are returning
> Not Implemented).
>
> This is largely ported from the similar code that exists for ARMv7
>
Hi Masahiro,
On 15 January 2015 at 12:10, Masahiro YAMADA wrote:
> Hi
>
> 2015-01-15 23:46 GMT+09:00 Simon Glass :
>> Hi,
>>
>> On 14 January 2015 at 01:18, Alexey Brodkin
>> wrote:
>>> Hi Simon, Masahiro-san,
>>>
>>> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>
>> Probably
On Tue, Dec 30, 2014 at 4:32 AM, wrote:
>
> From: Shaohui Xie
>
> This patch supports AQ1202, AQ2104, AQR105 PHY.
>
> Signed-off-by: Shaohui Xie
Acked-by: Joe Hershberger
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listi
On 12/30/2014 02:32 AM, shh@gmail.com wrote:
> From: Shaohui Xie
>
> This patch supports AQ1202, AQ2104, AQR105 PHY.
>
> Signed-off-by: Shaohui Xie
> ---
> drivers/net/phy/Makefile | 1 +
> drivers/net/phy/aquantia.c | 156
> +
> drivers/n
Hi Marek,
On 01/14/2015 05:58 PM, Marek Vasut wrote:
> On Wednesday, January 14, 2015 at 05:40:55 PM, dingu...@opensource.altera.com
> wrote:
>> From: Dinh Nguyen
>>
>> Add a function to relocate the stack from OCRAM to SDRAM.
>
> Hi,
>
> is this functionality really needed ? There's like 128
Dear David,
In message <54b7d34a.6090...@rapitasystems.com> you wrote:
>
> I had a look at this FAQ entry, and I think it's addressing a different
> point than the issue I'm seeing here. This part of the FAQ tells the
> user that the load point of their standalone function may differ due to
>
On Wed, Jan 14, 2015 at 07:57:25AM +, Thierry Reding wrote:
> On Tue, Jan 13, 2015 at 07:44:50PM +, Ian Campbell wrote:
> > Hi Thierry,
> >
> > I needed to boot my Jetson in NS mode (in order to boot Xen) and was
> > investigating the possibility of PSCI support when I discovered that you
On 01/15/2015 11:05 AM, Mark Rutland wrote:
> On Thu, Jan 15, 2015 at 06:10:57AM +, bhupesh.sha...@freescale.com wrote:
>> Hi York,
>>
>>> -Original Message-
>>> From: Sun York-R58495
>>> Sent: Wednesday, January 14, 2015 9:44 PM
>>> On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
Hi Mark,
> -Original Message-
> From: Mark Rutland [mailto:mark.rutl...@arm.com]
> Sent: Friday, January 16, 2015 12:35 AM
> To: Sharma Bhupesh-B45370
> Cc: Sun York-R58495; u-boot@lists.denx.de; albert.u.b...@aribaud.net;
> Wood Scott-B07421; Yoder Stuart-B08248
> Subject: Re: [U-Boot] [P
Vijay,
On 12/19/2014 04:35 AM, Vijay Rai wrote:
> Add support of 2 stage SD boot loader using SPL framework.
> here, PBL initialise the internal SRAM and copy SPL(160KB). This further
> initialise DDR using SPD environment and copy u-boot(768 KB) from NAND to DDR.
> Finally SPL transer control to
On Thu, Jan 15, 2015 at 06:10:57AM +, bhupesh.sha...@freescale.com wrote:
> Hi York,
>
> > -Original Message-
> > From: Sun York-R58495
> > Sent: Wednesday, January 14, 2015 9:44 PM
> > On 01/14/2015 05:46 AM, Bhupesh Sharma wrote:
> > > This patch adds basic constructs in the ARMv8 u-
Hi
2015-01-15 23:46 GMT+09:00 Simon Glass :
> Hi,
>
> On 14 January 2015 at 01:18, Alexey Brodkin
> wrote:
>> Hi Simon, Masahiro-san,
>>
>> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>>> >
>>> >> Probably I'm missing details of our Kconfig migration plan if one
>>> >> exists. Then I'd
On 01/15/2015 12:13 AM, Masahiro Yamada wrote:
> All the 74xx_7xx boards are still non-generic boards:
> P3G4, ZUMA, ppmc7xx, ELPPC, mpc7448hpc2
>
> Signed-off-by: Masahiro Yamada
> Cc: Wolfgang Denk
> Cc: Nye Liu
> Cc: Roy Zang
> ---
7xx or 74xx are pretty old. I don't even have any board
Hi Alexey,
2015-01-14 17:18 GMT+09:00 Alexey Brodkin :
> Hi Simon, Masahiro-san,
>
> On Tue, 2015-01-13 at 20:18 -0800, Simon Glass wrote:
>> >
>> >> Probably I'm missing details of our Kconfig migration plan if one
>> >> exists. Then I'd like to get a reference to the plan so I'm not
>> >> atte
Yuantian,
On 12/17/2014 05:55 PM, Tang Yuantian wrote:
> A new deep sleep interface is introduced to support generic
> board structure. Converts it to use new interface.
>
> Signed-off-by: Tang Yuantian
> ---
> board/freescale/t102xqds/ddr.c | 19 +++
> board/freescale/t102
On 01/15/2015 03:59 PM, Tom Rini wrote:
> On Wed, Jan 14, 2015 at 04:00:39PM +0100, Michal Simek wrote:
>
>> Use phys_addr_t instead of int for addresses.
>> Addresses can't be < 0.
>>
>> Signed-off-by: Michal Simek
>
> Note that this introduces:
> w+(microblaze-generic) ../drivers/net/xilinx_ll
This patch fix the compilation warning
w+../drivers/net/xilinx_ll_temac.c: In function 'll_temac_init':
w+../drivers/net/xilinx_ll_temac.c:235:3: warning: format '%X' expects
argument of type 'unsigned int', but argument 4 has type 'phys_addr_t'
[-Wformat]
introduced by
"net: Declare physical addre
On 01/15/2015 01:29 AM, Alison Wang wrote:
> CAAM is connected to CCI-400 S0 slave interface. Disable snooping for
> S0 will cause CAAM self test failure. This patch is to enable snooping
> for S0 slave interface. These CCI-400 operations are moved to
> board_early_init_f() to be initialized earli
Since GPIO support has now moved to the driver model uclass, we can drop
this include.
Signed-off-by: Simon Glass
---
lib/fdtdec.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/lib/fdtdec.c b/lib/fdtdec.c
index 3306028..fe30305 100644
--- a/lib/fdtdec.c
+++ b/lib/fdtdec.c
@@ -11,8 +11,6
Add initial sun9i (A80) support, only uart + mmc are supported for now.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile| 2 ++
arch/arm/cpu/armv7/sunxi/board.c | 4
arch/arm/cpu/armv7/sunxi/cpu_info.c | 5 +
arch/arm/cpu/armv7/sunxi/lowlevel_in
Add initial sun9i (A80) clock setup support, enough to get the uart + mmc
going.
Signed-off-by: Hans de Goede
---
arch/arm/cpu/armv7/sunxi/Makefile | 1 +
arch/arm/cpu/armv7/sunxi/clock_sun9i.c | 68 ++
2 files changed, 69 insertions(+)
create mode 100644 a
Signed-off-by: Hans de Goede
---
configs/Merrii_A80_Optimus_defconfig | 6 ++
1 file changed, 6 insertions(+)
create mode 100644 configs/Merrii_A80_Optimus_defconfig
diff --git a/configs/Merrii_A80_Optimus_defconfig
b/configs/Merrii_A80_Optimus_defconfig
new file mode 100644
index 000.
Hello list,
I'm using u-boot-2014.10 and trying to build it with LCD support for the
Beaglebone black to include a Boot logo image.
It seems that spl hangs while loading a 2.8MB sized u-boot.img !
I reduced the the logo header file and rebuild u-boot, that worked for a
1.6MB sized u-boot.img.
Is
The Fusion LCD needs the 32bit color depth to properly work; the
default is different on the 3.10.17 kernels and it is better to ensure
it work out of box using proper default color setting.
Signed-off-by: Otavio Salvador
---
include/configs/wandboard.h | 2 +-
1 file changed, 1 insertion(+), 1
Dear all,
i would like to post a patch with the m68k generic board
support, tested and working here, but of course not tested
for all the other m68k boards except mine.
My coldfire board is the "amcore" board not yet accepted.
http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/193661
http:/
On 15 January 2015 at 07:55, Michal Simek wrote:
> On 01/15/2015 03:25 PM, Simon Glass wrote:
>> Hi Michal,
>>
>> On 15 January 2015 at 01:53, Michal Simek wrote:
>>> Fake option is enabled only when CONFIG_TRACE is
>>> enabled in common/bootm.c:do_boot_states().
>>>
>>> Signed-off-by: Michal Sim
On Tue, Dec 02, 2014 at 01:17:36PM -0700, Simon Glass wrote:
> Refactor to allow this function to be used to announce the image being
> loaded regardless of compression type and even when there is no
> decompression.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
si
On Tue, Jan 13, 2015 at 06:49:01PM +0300, Alexey Brodkin wrote:
> It makes sense to specify CONFIG_SYS_CLK_FREQ in "configs/xx_defconfig"
> instead of "include/configs/xxx.h" because then header will be reusable
> across boards with different CPU clocks.
>
> Also this nice to have an ability for
On Wed, Jan 14, 2015 at 04:00:39PM +0100, Michal Simek wrote:
> Use phys_addr_t instead of int for addresses.
> Addresses can't be < 0.
>
> Signed-off-by: Michal Simek
Note that this introduces:
w+(microblaze-generic) ../drivers/net/xilinx_ll_temac.c: In function
'll_temac_init':
w+(microblaze
On Wed, Jan 14, 2015 at 03:36:35PM +0100, Michal Simek wrote:
> Signed-off-by: Michal Simek
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mail
Hey Wolfgang,
Hmm, I think I might not have made my point clear enough ... my
apologies! Either that or I have a fundamental misunderstanding of the
issue (more likely).
No. See the FAQ entry. The entry point address really depends on te
code. If you add code, it can be basically anywehre
On Mon, Dec 08, 2014 at 05:49:42PM +0100, Evgeni Dobrev wrote:
> Add support for Seagate BlackArmor NAS220
>
> Signed-off-by: Evgeni Dobrev
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot mailing li
On Thu, Jan 08, 2015 at 07:23:35PM +0900, Masahiro Yamada wrote:
> If CONFIG_SPL_NOR_SUPPORT is defined, spl_nor_load_image() requires
> spl_start_uboot(), CONFIG_SYS_OS_BASE, CONFIG_SYS_SPL_ARGS_ADDR,
> CONFIG_SYS_FDT_BASE to be defined even if users just want to run
> U-Boot, not Linux. This is
On Wed, Jan 14, 2015 at 03:36:34PM +0100, Michal Simek wrote:
> Trivial fix.
>
> Signed-off-by: Michal Simek
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
U-Boot mailing list
U-Boot@lists.denx.de
http://
On Tue, Dec 02, 2014 at 01:17:40PM -0700, Simon Glass wrote:
> This allows the caller to easily detect how much of the destination buffer
> has been used.
>
> Signed-off-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital signature
___
On Tue, Dec 16, 2014 at 02:07:22PM +0100, Marek Vasut wrote:
> Allow booting the OpenRTOS payloads via fitImage image type.
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digit
On Tue, Dec 16, 2014 at 02:07:21PM +0100, Marek Vasut wrote:
> Add separate image type for the Wittenstein OpenRTOS .
>
> Signed-off-by: Marek Vasut
> Cc: Simon Glass
> Cc: Tom Rini
> Reviewed-by: Simon Glass
Applied to u-boot/master, thanks!
--
Tom
signature.asc
Description: Digital sig
1 - 100 of 170 matches
Mail list logo
