Set the frame buffer to write-combining. This makes it faster, although for
scrolling write-through is even faster for U-Boot.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/gma.c | 8
1 file changed, 8 insertions(+)
diff --git a/arch/x86/cpu/ivybridge/gma.c b/arch/x86/cpu/ivyb
There is no need to run with the cache disabled, and there is no point in
clearing the display frame buffer since U-Boot does it later.
Signed-off-by: Simon Glass
---
arch/x86/lib/bios.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/
For bare platforms we turn off ROM-caching before calling board_init_f_r()
It is then very slow to copy U-Boot from ROM to RAM. So adjust the order so
that the copying happens before we turn off ROM-caching.
Signed-off-by: Simon Glass
---
common/board_f.c | 8 +---
1 file changed, 5 inserti
We should use MTRRs to speed up execution. Add a list of MTRR requests which
will dealt with when we relocate and run from RAM.
We set RAM as cacheable (with write-back) and registers as non-cacheable.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/sdram.c | 10 ++
1 file change
Some machines are very slow to scroll their displays. To cope with this,
support the CONFIG_CONSOLE_SCROLL_LINES option. Setting this to 5 allows
the display to operate at an acceptable speed by scrolling 5 lines at
a time.
This same option is available for LCDs so when these systems are unified
t
At present the normal update (which happens much later) does not work. This
seems to have something to do with the 'no eviction' mode in the CAR, or at
least moving the microcode update after that causes it not to work.
For now, do an update early on so that it definitely works. Also refuse to
con
It is useful to be able to see the MTRR setup in U-Boot. Add a command
to list the state of the variable MTRR registers and allow them to be
changed.
Update the documentation to list some of the available commands.
This does not support fixed MTRRs as yet.
Signed-off-by: Simon Glass
---
commo
Provide a way to display this address when booting.
Signed-off-by: Simon Glass
---
drivers/video/x86_fb.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/video/x86_fb.c b/drivers/video/x86_fb.c
index 8743a8c..6641033 100644
--- a/drivers/video/x86_fb.c
+++ b/drivers/video/x86_fb.c
@
Memory Type Range Registers are used to tell the CPU whether memory is
cacheable and if so the cache write mode to use.
Clean up the existing header file to follow style, and remove the unneeded
code.
These can speed up booting so should be supported. Add these to global_data
so they can be reque
Once we stop running from ROM we should set up the MTTRs to speed up
execution. This is only needed for platforms that don't have an FSP.
Also in the Coreboot case, the MTRRs are set up for us.
Signed-off-by: Simon Glass
---
arch/x86/lib/init_helpers.c | 8
1 file changed, 8 insertions
The hex value is more commonly understood, so use that instead of decimal.
Add a 0x prefix to avoid confusion.
Signed-off-by: Simon Glass
---
drivers/pci/pci_rom.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c
index 5ba315b
This is set up along with CAR (Cache-as-RAM) anyway. When we relocate we
don't really need ROM caching (we read the VGA BIOS from ROM but that is
about it)
Drop it.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/cpu.c | 25 -
1 file changed, 25 deletions(-)
diff
This takes about about 700ms on link when running natively and 900ms when
running using the emulator. It is a waste of time if video is not enabled,
so don't bother running the video BIOS in that case.
We could add a command to run the video BIOS later when needed, but this is
not considered at pr
Scrolling a line at a time is very slow for reasons that I don't understand.
It seems to take about 100ms to copy 4MB of RAM in the frame buffer. To cope
with this, scroll 5 lines each time.
Signed-off-by: Simon Glass
---
include/configs/x86-common.h | 1 +
1 file changed, 1 insertion(+)
diff
This can be very slow - typically 80ms even on a fast machine since it uses
the SPI flash to read the data. Add an option to display the time taken.
Signed-off-by: Simon Glass
---
drivers/pci/pci_rom.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pc
For platforms with CAR we should disable it before relocation. Check if
this function is available and call it if so.
Signed-off-by: Simon Glass
---
arch/x86/cpu/start.S | 10 ++
1 file changed, 10 insertions(+)
diff --git a/arch/x86/cpu/start.S b/arch/x86/cpu/start.S
index 125782c..8c
There are some bits which should be ignored when displaying the mode number.
Make sure that they are not included in the mode that is displayed.
Signed-off-by: Simon Glass
---
arch/x86/lib/bios.c | 11 +++
1 file changed, 7 insertions(+), 4 deletions(-)
diff --git a/arch/x86/lib/bios.c
This currently assumes that U-Boot resides at the start of ROM. Update
it to remove this assumption.
Signed-off-by: Simon Glass
---
tools/ifdtool.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tools/ifdtool.c b/tools/ifdtool.c
index fe8366b..590ccc9 100644
--- a/tools
Cache-as-RAM should be turned off when we relocate since we want to run from
RAM. Add a function to perform this task.
Signed-off-by: Simon Glass
---
arch/x86/cpu/ivybridge/car.S | 52
1 file changed, 52 insertions(+)
diff --git a/arch/x86/cpu/ivybr
If the video has not been set up, we should not return a success code. This
can be detected by seeing if any of the variables are non-zero.
Signed-off-by: Simon Glass
---
drivers/pci/pci_rom.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/pci/pci_rom.c b/drivers/pc
We don't need this in U-Boot since we calculate it based on available memory.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 4
1 file changed, 4 deletions(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index 7d007bb..e992e64 100644
--- a/arch/x86/Kconfig
+++ b/arch/x86/Kconfig
@@
This should default to the size of the ROM for faster execution before
relocation.
Signed-off-by: Simon Glass
---
arch/x86/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig
index ebf72b3..7d007bb 100644
--- a/arch/x86/Kconfig
+++ b/a
On 27 December 2014 at 05:10, Bin Meng wrote:
> The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
> 1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
> Open Firmware PCI bus bindings.
>
> Also a comment block is added for the 'stdout-path' property in the
> cho
Hi Bin,
On 27 December 2014 at 05:10, Bin Meng wrote:
> There are many pci uart devices which are ns16550 compatible. We can
> describe them in the board dts file and use it as the U-Boot serial
> console as specified in the chosen node 'stdout-path' property.
>
> Those pci uart devices can have
On 27 December 2014 at 05:10, Bin Meng wrote:
> Use ePAPR defined properties for x86-uart: clock-frequency and
> current-speed. Assign the value of clock-frequency in device tree
> to plat->clock of x86-uart instead of using hardcoded number.
>
> Signed-off-by: Bin Meng
>
> ---
>
> Changes in v2
Hi Bin,
On 27 December 2014 at 05:10, Bin Meng wrote:
> This commit adds several APIs to decode PCI device node according to
> the Open Firmware PCI bus bindings, including:
> - fdtdec_get_pci_addr() for encoded pci address
> - fdtdec_get_pci_vendev() for vendor id and device id
> - fdtdec_get_pc
On 27 December 2014 at 05:10, Bin Meng wrote:
> Introduce a gd->hose to save the pci hose in the early phase so that
> apis in drivers/pci/pci.c can be used before relocation. Architecture
> codes need assign a valid gd->hose in the early phase.
>
> Some variables are declared as static so change
On 27 December 2014 at 05:10, Bin Meng wrote:
> arch/x86/cpu/pci.c has access to the U-Boot global data thus
> DECLARE_GLOBAL_DATA_PTR is needed.
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
>
> ---
>
> Changes in v2:
> - Add a commit message
>
> arch/x86/cpu/pci.c | 2 ++
> 1 file chang
On 27 December 2014 at 05:10, Bin Meng wrote:
> On x86, some peripherals on pci buses need to be accessed in the
> early phase (eg: pci uart) with a valid pci memory/io address,
> thus scan the pci bus and do the corresponding resource allocation.
>
> Signed-off-by: Bin Meng
> ---
>
> Changes in
On 27 December 2014 at 18:22, Simon Glass wrote:
> On 23 December 2014 at 22:06, Bin Meng wrote:
>> This commits cleans up the board dts files.
>>
>> - Correct the serial port register size to 8
>> - Remove the misleading status = "disabled" statement in the
>> serial.dtsi
>> - Move the inclusi
On 27 December 2014 at 18:22, Simon Glass wrote:
> On 23 December 2014 at 22:06, Bin Meng wrote:
>> The name of coreboot.dtsi is misleading, as it actually describes
>> the legacy serial port device node.
>>
>> Signed-off-by: Bin Meng
>
> Acked-by: Simon Glass
Applied to u-boot-x86/next, thank
On 27 December 2014 at 18:22, Simon Glass wrote:
> On 23 December 2014 at 22:06, Bin Meng wrote:
>> No board is using alex.dts, so remove it.
>>
>> Signed-off-by: Bin Meng
>
> Acked-by: Simon Glass
Applied to u-boot-x86/next, thanks!
___
U-Boot maili
On 23 December 2014 at 22:06, Bin Meng wrote:
> This commits cleans up the board dts files.
>
> - Correct the serial port register size to 8
> - Remove the misleading status = "disabled" statement in the
> serial.dtsi
> - Move the inclusion of skeleton.dtsi from serial.dtsi to board
> dts file
On 23 December 2014 at 22:06, Bin Meng wrote:
> No board is using alex.dts, so remove it.
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
___
U-Boot mailing list
U-Boot@lists.denx.de
http://lists.denx.de/mailman/listinfo/u-boot
On 23 December 2014 at 22:06, Bin Meng wrote:
> The name of coreboot.dtsi is misleading, as it actually describes
> the legacy serial port device node.
>
> Signed-off-by: Bin Meng
Acked-by: Simon Glass
___
U-Boot mailing list
U-Boot@lists.denx.de
http
Hi Bin,
On 23 December 2014 at 22:06, Bin Meng wrote:
> Right now all dts files under arch/x86/dts are compiled. This is
> not necessary so update the Makefile to only compile dts file for
> a specific board.
I'd rather that we go the other way - making the boards more common.
If I can get the M
Hi Bin,
On 23 December 2014 at 22:06, Bin Meng wrote:
> The include directory in arch/x86/dts is not used, so remove it.
>
> Signed-off-by: Bin Meng
> ---
Actually we do need this - the Chrome OS keyboard .dtsi will use a
binding when I get around to updating it.
>
> arch/x86/dts/include/dt-b
Commit "initcall: Improve debugging support" makes sense and indeed
simplifies process of matching initcalls executed with static
disassembly.
Until you are debugging relocation functionality.
Existign output may make you think that at some point execution somehow
returned back to non-relocated a
This patch adds boot script support to pcm051
Signed-off-by: Matwey V. Kornilov
---
include/configs/pcm051.h | 29 ++---
1 file changed, 18 insertions(+), 11 deletions(-)
diff --git a/include/configs/pcm051.h b/include/configs/pcm051.h
index 7d102a4..c0bb227 100644
--- a
Hi Masahiro,
On 25 December 2014 at 00:15, Masahiro Yamada wrote:
> Simon, Heiko,
>
>
> If you have no objection to this series,
> I will apply it to u-boot-uniphier.
>
> Is this OK?
>
>
> Some replies below to Simon's comment.
>
>
>
> On Tue, 23 Dec 2014 12:54:53 -0700
> Simon Glass wrote:
>
>
Hi,
On 24-12-14 17:58, Siarhei Siamashka wrote:
After reboot, reset or even short power off, DRAM typically retains
the old stale data for some period of time (for this type of memory,
the bits of data are stored in slowly discharging capacitors).
The current sun6i/sun8i DRAM size detection log
PLL1 on sun6i / sun8i also has a p factor which divides the clock by
2^p (to the power p). On sun6i the p factor is ignored, but on sun8i it is
used and we were setting it to 1, resulting in the CPU running at 504 MHz
instead of 1008 MHz, this commit fixes this.
Signed-off-by: Hans de Goede
---
If a board has no LCD, but does have VGA fallback to VGA when no HDMI cable
is connected (unless hpd=0).
Signed-off-by: Hans de Goede
---
Changes in v2:
-Fix missing "break;" in v1 which caused hdmi output to no longer work
---
doc/README.video | 3 +--
drivers/video/sunxi_display.
It turns out that the problems I was seeing were due to a bad powersupply,
so enable proper negative hsync / vsync support.
Also adjust various defconfigs to keep the hsync and vsync for the lcd
panels positive, changing sync:0 into sync:3.
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/
If a board has no LCD, but does have VGA fallback to VGA when no HDMI cable
is connected (unless hpd=0).
Signed-off-by: Hans de Goede
---
doc/README.video | 3 +--
drivers/video/sunxi_display.c | 47 ---
2 files changed, 27 insertions(+), 23
Add support for using PORTD hsync/vsync pins with tcon1, this is a preparation
patch for adding native VGA support.
Signed-off-by: Hans de Goede
---
drivers/video/sunxi_display.c | 22 +++---
1 file changed, 19 insertions(+), 3 deletions(-)
diff --git a/drivers/video/sunxi_displ
Hi Ian,
Here is my last sunxi-video patch series, this time adding support for
the native vga out found on the A10 / A20 SoCs, and used e.g. on the
Cubietruck.
With this patch series by default (can be overridden through video-mode env.)
the display will fallback to 1024x768 over VGA when no HDMI
Add support for VGA directly from the sunxi SoC / display engine.
Signed-off-by: Hans de Goede
---
arch/arm/include/asm/arch-sunxi/clock_sun4i.h | 2 +
arch/arm/include/asm/arch-sunxi/display.h | 76 +++
board/sunxi/Kconfig | 9 +++-
config
Hi,
Thanks, I've queued both patch up in u-boot-sunxi/next. Note I've
changed the sync:0 to sync:3 in the LCD_MODE for the Primo73,
because of:
https://github.com/jwrdegoede/u-boot-sunxi/commit/5a6b9376f78128d00459db21da80f17ad3473d3a
Before the above commit the lcd-code was ignoring the sync f
There are many pci uart devices which are ns16550 compatible. We can
describe them in the board dts file and use it as the U-Boot serial
console as specified in the chosen node 'stdout-path' property.
Those pci uart devices can have their register be memory mapped, or
i/o mapped. The driver will t
The Topcliff PCH has 4 UART devices integrated (Device 10, Funciton
1/2/3/4). Add the corresponding device nodes in the crownbay.dts per
Open Firmware PCI bus bindings.
Also a comment block is added for the 'stdout-path' property in the
chosen node, mentioning that by default the legacy superio se
Use ePAPR defined properties for x86-uart: clock-frequency and
current-speed. Assign the value of clock-frequency in device tree
to plat->clock of x86-uart instead of using hardcoded number.
Signed-off-by: Bin Meng
---
Changes in v2:
- New patch to use ePAPR defined properties for x86-uart
ar
This commit adds several APIs to decode PCI device node according to
the Open Firmware PCI bus bindings, including:
- fdtdec_get_pci_addr() for encoded pci address
- fdtdec_get_pci_vendev() for vendor id and device id
- fdtdec_get_pci_bdf() for pci device bdf triplet
- fdtdec_get_pci_bar32() for pc
On x86, some peripherals on pci buses need to be accessed in the
early phase (eg: pci uart) with a valid pci memory/io address,
thus scan the pci bus and do the corresponding resource allocation.
Signed-off-by: Bin Meng
---
Changes in v2: None
arch/x86/cpu/pci.c | 1 +
1 file changed, 1 insert
Introduce a gd->hose to save the pci hose in the early phase so that
apis in drivers/pci/pci.c can be used before relocation. Architecture
codes need assign a valid gd->hose in the early phase.
Some variables are declared as static so change them to be either
stack variable or global data member s
arch/x86/cpu/pci.c has access to the U-Boot global data thus
DECLARE_GLOBAL_DATA_PTR is needed.
Signed-off-by: Bin Meng
---
Changes in v2:
- Add a commit message
arch/x86/cpu/pci.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/x86/cpu/pci.c b/arch/x86/cpu/pci.c
index f3492c3..404
This series add support to the ns16550 compatible pci devices.
Newer x86 Platform Controller Hub chipset (like Topcliff, BayTrail)
starts to integrate ns16550 compatible pci uart devices. In order to
use them, we have to scan the pci bus and allocate memory/io address
in the early phase. A gd->hos
Ping.
This patch is needed for the release. Otherwise, raw boot mode is broken if
FAT/SPL support is also enabled.
Guillaume
Le 16/12/2014 12:00, Guillaume GARDET a écrit :
As reported by Robert Nelson, commit 4c5bbc2328a24f5e1ee990c9a9527e48e5fb3b5f
may break MMC RAW boot mode.
This patch
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