Current code does not set gpio output value in ich6_gpio_direction_output(),
fix it.
Signed-off-by: Axel Lin
---
drivers/gpio/intel_ich6_gpio.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpio/intel_ich6_gpio.c b/drivers/gpio/intel_ich6_gpio.c
index b095d17..92c23ae 100644
---
On Sat, Dec 06, 2014 at 10:24:33AM -0800, Steve Rae wrote:
> enable this clock with the following:
> clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
>
> Signed-off-by: Steve Rae
Reviewed-by: Felipe Balbi
> ---
>
> Changes in v2:
> removed unrelated changes as per Felipe Balbi
>
> arch/arm/cp
On Sun, 2014-12-07 at 02:32 +0100, Marek Vasut wrote:
> On Sunday, December 07, 2014 at 12:45:30 AM, Scott Wood wrote:
> > On Sat, 2014-12-06 at 14:07 +0100, Marek Vasut wrote:
> > > On Tuesday, December 02, 2014 at 02:26:14 PM, Stefan Roese wrote:
> > > > This patch adds support for multiple NAND
On Sunday, December 07, 2014 at 12:45:30 AM, Scott Wood wrote:
> On Sat, 2014-12-06 at 14:07 +0100, Marek Vasut wrote:
> > On Tuesday, December 02, 2014 at 02:26:14 PM, Stefan Roese wrote:
> > > This patch adds support for multiple NAND chips connected to the
> > > i.MX6. Linux already supports thi
On Sat, 2014-12-06 at 14:07 +0100, Marek Vasut wrote:
> On Tuesday, December 02, 2014 at 02:26:14 PM, Stefan Roese wrote:
> > This patch adds support for multiple NAND chips connected to the
> > i.MX6. Linux already supports this configuration. So lets port
> > the missing features to the U-Boot dr
enable this clock with the following:
clk_usb_otg_enable((void *)HSOTG_BASE_ADDR)
Signed-off-by: Steve Rae
---
Changes in v2:
removed unrelated changes as per Felipe Balbi
arch/arm/cpu/armv7/bcm281xx/Makefile| 1 +
arch/arm/cpu/armv7/bcm281xx/clk-bcm281xx.c | 16 +++
a
This patch adds NAND boot support for LS1021AQDS board. SPL
framework is used. PBL initialize the internal RAM and copy
SPL to it, then SPL initialize DDR using SPD and copy u-boot
from NAND flash to DDR, finally SPL transfer control to u-boot.
Signed-off-by: Prabhakar Kushwaha
Signed-off-by: Ali
On Thursday, December 04, 2014 at 11:36:33 PM, Steve Rae wrote:
> Implement a feature to allow fastboot to write the downloaded image
> to the space reserved for the Protective MBR and the Primary GUID
> Partition Table.
>
> Signed-off-by: Steve Rae
Lukasz, what do you think please ?
In my opti
On Tuesday, December 02, 2014 at 02:26:14 PM, Stefan Roese wrote:
> This patch adds support for multiple NAND chips connected to the
> i.MX6. Linux already supports this configuration. So lets port
> the missing features to the U-Boot driver to support more than
> one NAND chip here as well.
>
> T
On Saturday, November 08, 2014 at 01:18:31 PM, Stefan Roese wrote:
> On 07.11.2014 20:56, Dinh Nguyen wrote:
> > +CC: Graham Moore
> >
> > On 11/07/2014 09:26 AM, Stefan Roese wrote:
> >> Hi Dinh, Hi Vince!
>
>
>
> >> Could we not just use a "plain" GPL (v2) license here as well.
> >> Especiall
On Wednesday, November 26, 2014 at 07:14:33 PM, dingu...@opensource.altera.com
wrote:
> From: Dinh Nguyen
>
> Correctly increment the base address of the freeze controller. And since
> SYSMGR_FRZCTRL_VIOCTRL_SHIFT is not needed, remove it from the include
> file.
>
> Signed-off-by: Dinh Nguyen
On Thursday, October 30, 2014 at 09:19:56 AM, Stefan Roese wrote:
> This patch includes the latest DT sources for socfpga from the current
> Linux kernel. And enables CONFIG_OF_CONTROL for socfpga_cyclone5 to
> make use of this new DT support.
>
> Note that now the image to use is u-boot-dtb.img!
Hi Simon,
On Fri, Dec 5, 2014 at 11:08 PM, Simon Glass wrote:
> Hi Bin,
>
> On 5 December 2014 at 01:35, Bin Meng wrote:
>> Hi Simon,
>>
>> On Fri, Dec 5, 2014 at 6:43 AM, Simon Glass wrote:
>>> Hi Bin,
>>>
>>> On 4 December 2014 at 08:01, Bin Meng wrote:
Intel Tunnel Creek GPIO register
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