This patch fixes the S3C24xx I2C driver as per new I2C
multibus/multiadapter support for Exynos5250.
Change-Id: I95873fef7d312310670e3bb33ad9532c10f60463
Signed-off-by: Rajeshwari S Shinde
---
drivers/i2c/s3c24x0_i2c.c | 14 +++---
include/configs/exynos5250-dt.h | 3 ++-
2 files
This patch enables ethernet support in ARMv8 foundation model. The ARMv8
foundation model supports a SMSC91C111 integrated MAC and PHY module
which is present at base address 0x01A00.
The patch has been tested on ARMv8 foundation model by running ping/tftp
between the foundation model and the
NAND boot mode on AM335x EVM has been verified, and steps
to use it has been documented and update in this README
Signed-off-by: Pekon Gupta
---
board/ti/am335x/README | 59 +++---
1 file changed, 42 insertions(+), 17 deletions(-)
diff --git a/board/t
chip->ecc.correct() is used for detecting and correcting bit-flips during read
operations. In omap-nand driver it implemented as:
(a) omap_correct_data(): for h/w based ECC_HAM1 scheme
(b) omap_correct_data_bch() + CONFIG_NAND_OMAP_ECC_BCH8_CODE_HW_DETECTION_SW
for ECC_BCH8 scheme using GPM
chip->ecc.calculate() is used for calculating and fetching of ECC syndrome by
processing the data passed during Read/Write accesses.
All H/W based ECC schemes use GPMC controller to calculate ECC syndrome.
But each BCHx_ECC scheme has its own implemetation of post-processing and
fetching ECC syndr
BCH8_ECC scheme implemented in omap_gpmc.c driver has following favours
+---+-+-+
|ECC Scheme | ECC Calculation | Error Detection |
+---+-+-+
|OMAP
chip->ecc.hwctl() is used for preparing the H/W controller before read/write
NAND accesses (like assigning data-buf, enabling ECC scheme configs, etc.)
Though all ECC schemes in OMAP NAND driver use GPMC controller for generating
ECC syndrome (for both Read/Write accesses). But but in current code
*changes in v4*
[PATCH 1/5]
- removed omap_read_page_bch(): chip->ecc.read_page uses default API
nand_read_page_hwecc() in nand_base.c
- updated tricorder.h: added new CONFIGS for ECCSCHEME & ONFI_DETECTION
- converted printf("ECC-SCHEME") to debug("ECC-SCHEM
T1040 SoC has
- DDR controller ver 5.0
- 2 PLLs
- 8 IFC Chip select
- FMAN Muram 192K
- No Srio
- Sec controller ver 5.0
- Max CPU update for its personalities
So, update the defines accordingly.
Signed-off-by: Prabhakar Kushwaha
---
Changes for v2:
- Remove
CHASSIS2 architecture never fix clock groups for Cluster and hardware
accelerator like PME, FMA. These are SoC defined. SoC defines :-
- NUM of PLLs present in the system
- Clusters and their Clock group
- hardware accelerator and their clock group
if no clock group, then plat
Dear U-Boot maintainer,
I have two questions about mmc driver base u-boot-2013.07.
Q 1:
In mmc.c, function sd_send_op_cond(), line 506:
line 505:
if (timeout <= 0)
line 506:
return UNUSABLE_ERR;
I think it should be return TIMEOUT .
Because for MMC card or eMMC device, the progra
于 2013年09月02日 19:32, Marek Vasut 写道:
This makes not much sense to me. If what you claim is true, than JFFS2 in U-Boot
and Linux would be incompatible for all MTD drivers. This would also mean that
The jffs2 in uboot and linux is compatible now. But the mtd base code,
such as nand_base.c /nand_bb
Add atmel usba udc driver support, porting from Linux kernel
Signed-off-by: Bo Shen
---
drivers/usb/gadget/Makefile |1 +
drivers/usb/gadget/atmel_usba_udc.c | 1305 +++
drivers/usb/gadget/atmel_usba_udc.h | 326 +
include/linux/usb/atmel_usba
Add RNDIS gadget support to test atmel usba udc driver
Signed-off-by: Bo Shen
---
arch/arm/cpu/armv7/at91/sama5d3_devices.c| 12 ++
arch/arm/include/asm/arch-at91/at91_common.h |1 +
board/atmel/sama5d3xek/sama5d3xek.c | 51 ++
include/configs/sa
Add atmel usb udc driver support porting from Linux kernel.
Using RNDIS gadget driver to test it.
Test it on sama5d31ek and sam9x5ek board.
Bo Shen (3):
USB: gadget: add atmel usba udc driver
ARM: atmel: correct UDPHS name
ARM: atmel: add RNDIS gadget support
arch/arm/cpu/armv7/at91/sama5d
Signed-off-by: Bo Shen
---
arch/arm/include/asm/arch-at91/sama5d3.h |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/arch-at91/sama5d3.h
b/arch/arm/include/asm/arch-at91/sama5d3.h
index 49bd335..b9d574d 100644
--- a/arch/arm/include/asm/arch-at91/sama5d
Hi Mike,
On 09/03/2013 10:38 AM, Thomas Chou wrote:
The gcc-4.7.3 in lastest nios2 toolchain generated lots of warning on
type mismatch. So change typedef of size_t to unsigned int, followed
those of arm and mips arch.
spi_flash.c: In function 'spi_flash_read_write':
spi_flash.c:42:3: warning:
Hi Albert Aribaud,
On 08/22/2013 11:04 PM, Andreas Bießmann wrote:
Dear Albert Aribaud,
The following changes since commit 9ed887caecb9ecb0c68773a1870d143b9f28d3da:
Merge branch 'u-boot-imx/master' into 'u-boot-arm/master' (2013-08-17
18:24:13 +0200)
are available in the git repository at
The gcc-4.7.3 in lastest nios2 toolchain generated lots of warning on
type mismatch. So change typedef of size_t to unsigned int, followed
those of arm and mips arch.
spi_flash.c: In function 'spi_flash_read_write':
spi_flash.c:42:3: warning: format '%zu' expects argument of type
'size_t', but a
The commit 1a4596601fd395f3afb8f82f3f840c5e00bdd57a
Add GPL-2.0+ SPDX-License-Identifier to source files
generated a warning due to a missing comment terminator.
longlong.h:7:1: warning: "/*" within comment
Signed-off-by: Thomas Chou
---
arch/nios2/lib/longlong.h | 1 +
1 file changed, 1 in
On Mon, Sep 2, 2013 at 7:30 AM, Christian Gmeiner <
christian.gmei...@gmail.com> wrote:
> This patch is needed if the MAC is directly connected to a ethernet switch.
> In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to
> is configure my fixed phy/link like:
>
> #define IMX_F
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA1
On 08/31/2013 05:15 PM, Otavio Salvador wrote:
> On Sat, Aug 31, 2013 at 5:52 PM, Stefano Babic wrote:
>> Am 31/08/2013 22:03, schrieb Marek Vasut:
>>
>>> I suppose there will be not much problem with this reorder ... it would be
>>> nice
>>> if you
Dear Tom,
In message <20130902182422.GX17898@bill-the-cat> you wrote:
>
> I've put v2013.10-rc2 out, and I hope Detlev can get the tarball
> uploaded soon.
Done!
Thanks!
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB 165235 Munich,
Dear Tom,
In message <20130902182422.GX17898@bill-the-cat> you wrote:
>
> I've put v2013.10-rc2 out, and I hope Detlev can get the tarball
> uploaded soon.
BTW - the Subject: was wrong...
Best regards,
Wolfgang Denk
--
DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel
HRB
Hey all,
I've put v2013.10-rc2 out, and I hope Detlev can get the tarball
uploaded soon.
We don't have a whole lot of changes in here, but I think that's partly
due to some folks being on holiday. I hope that we can finish
re-syncing everyone in around the 16th when I'll kick out -rc3.
For my p
Hi Thomas,
On 02/09/2013 16:59, thomas.lan...@lantiq.com wrote:
> Hello Stefano,
>
> Stefano Babic wrote on 2013-09-02:
>
>> Some phys have additional registers that are not covered
>> by standard. Access to this registers can be done via
>> specific sequence according to the phy datasheet.
>>
Hello Stefano,
Stefano Babic wrote on 2013-09-02:
> Some phys have additional registers that are not covered
> by standard. Access to this registers can be done via
> specific sequence according to the phy datasheet.
> The driver for Micrel phy contains some additional function,
> that the board
On 08/29/2013 05:16 AM, Jaehoon Chung wrote:
Hi Przemyslaw,
Could you give me the test-case?
I want to test this problem.
On 08/29/2013 01:49 AM, Przemyslaw Marczak wrote:
According to JEDEC eMMC specification, after data transfer
(multiple or single block) host must wait for card ready
status
On 08/30/2013 04:16 AM, Minkyu Kang wrote:
Dear Przemyslaw Marczak,
...
Your v1 patchset is made by 3 patches.
But this patch is only one patch.
Do you want to separate patchset?
Then please send each patches again.
or not, please send whole patchset.
Thanks,
Minkyu Kang.
Hello Minkyu Kang,
Some phys (Micrel) has extended registers that must be
accessed in a special way. Add pointers to the phy driver
structure to allow to use these functions with mdio command.
Signed-off-by: Stefano Babic
---
include/phy.h |3 +++
1 file changed, 3 insertions(+)
diff --git a/include/phy.h b/i
Some phys (Micrel) have additional registers that can
be accessed using a special sequence. This patch allows
to use standard "mdio" command to accesss these registers.
Signed-off-by: Stefano Babic
---
common/cmd_mdio.c | 75 +
1 file changed
Signed-off-by: Stefano Babic
---
include/micrel.h |5 +
1 file changed, 5 insertions(+)
diff --git a/include/micrel.h b/include/micrel.h
index e1c62d8..04c9ecf 100644
--- a/include/micrel.h
+++ b/include/micrel.h
@@ -15,6 +15,11 @@
#define MII_KSZ9031_MOD_DATA_POST_INC_RW 0x8000
Signed-off-by: Stefano Babic
---
drivers/net/phy/micrel.c | 32
1 file changed, 32 insertions(+)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index f3e3054..5d7e3be 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -100
Signed-off-by: Stefano Babic
---
drivers/net/phy/micrel.c |2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/net/phy/micrel.c b/drivers/net/phy/micrel.c
index a7450f8..f3e3054 100644
--- a/drivers/net/phy/micrel.c
+++ b/drivers/net/phy/micrel.c
@@ -174,7 +174,7 @@ int
Some phys have additional registers that are not covered
by standard. Access to this registers can be done via
specific sequence according to the phy datasheet.
The driver for Micrel phy contains some additional function,
that the board maintainer can call to tune the phy. However,
these registers
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
Changes in V2:
- None
include/configs/smdk5420.h | 316 +
1 file changed, 316 inserti
This patch adds support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Akshay Saraswat
Signed-off-by: Rajeshwari S Shinde
---
Changes in V2:
- None
arch/arm/dts/exynos5.dtsi | 213 +
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
Changes in V2:
- None
MAINTAINERS | 1 +
Makefile
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
Changes in V2:
Corrected a compilation issue for SMDK5250.
arch/arm/cpu/armv7/exynos/dmc_common.c| 8 -
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.
From: Akshay Saraswat
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
Changes in V2:
- None
arch/arm/cpu/armv7/exynos/pinmux.c | 171 +++-
arch/arm/include/asm/arch-exy
From: Akshay Saraswat
This patch modifies UNCON and UFCON values to make s5p
serial support exynos5420 by doing following changes:
* Enable Rx time-out interrupts.
* Make Rx time-out interrupt interval = 32 frame time.
* Enable DMA mode.
* Enable FIFO.
* Make Rx FIFO Trigger level 64, 16 and
From: Akshay Saraswat
Currently, part of TZPC init code for Exynos5 starts setting DECPROT
from the base address 0x1010 upto 0x1019 but in case of
Exynos5420 we need it to start from 0x0100E and keep end address
same as 0x1019.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: A
From: Akshay Saraswat
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
Changes in V2:
- None
arch/arm/include/asm/arch-exynos/cpu.h | 48 +-
1 file changed,
This patch adds basic board support for SMDK5420 board.
These patches are tested for booting fine on EVT0 SMDK5420.
Changes in V2:
Corrected a compilation issue for SMDK5250.
Akshay Saraswat (5):
Exynos5420: Add base addresses for 5420
Exynos5420: Add clock initialization for 5420
E
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform cpecific code.
Signed-off-by: Rajeshwari S Shinde
---
Changes in V2:
- None
arch/arm/include/asm/arch-exynos/board.h | 17 ++
board/samsung/common
This patch is needed if the MAC is directly connected to a ethernet switch.
In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to
is configure my fixed phy/link like:
#define IMX_FEC_BASEENET_BASE_ADDR
#define CONFIG_FEC_XCV_TYPE MII100
#define C
This patch is needed if the MAC is directly connected to a ethernet switch.
In my case the FEC MAC is connected to a Micrel KSZ8895. All I need to to
is configure my fixed phy/link like:
Signed-off-by: Christian Gmeiner
---
drivers/net/phy/Makefile |1 +
drivers/net/phy/fixed.c | 34 +
Adding initial config for SMDK5420 to build and boot U-Boot
over Exynos based SMDK5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
include/configs/smdk5420.h | 316 +
1 file changed, 316 insertions(+)
create mode 100644 inc
From: Akshay Saraswat
This patch modifies UNCON and UFCON values to make s5p
serial support exynos5420 by doing following changes:
* Enable Rx time-out interrupts.
* Make Rx time-out interrupt interval = 32 frame time.
* Enable DMA mode.
* Enable FIFO.
* Make Rx FIFO Trigger level 64, 16 and
From: Akshay Saraswat
This patch intends to add DDR3 initialization code for Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
arch/arm/cpu/armv7/exynos/dmc_common.c| 8 -
arch/arm/cpu/armv7/exynos/dmc_init_ddr3.c | 411 +-
arc
From: Akshay Saraswat
Adds code in pinmux and gpio framework to support Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
arch/arm/cpu/armv7/exynos/pinmux.c | 171 +++-
arch/arm/include/asm/arch-exynos/gpio.h | 52 ++
2
This patch adds support for SMDK5420.
exynos5.dtsi created is a common file which has the nodes common
to both 5420 and 5250.
Signed-off-by: Rajeshwari S Shinde
---
arch/arm/dts/exynos5.dtsi | 213 ++
arch/arm/dts/exynos5250.dtsi | 177 +--
Adding the base patch for Exynos based SMDK5420.
This shall enable compilation and basic boot support for
SMDK5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
MAINTAINERS | 1 +
Makefile | 2 +-
board/samsung/
From: Akshay Saraswat
Adds base addresses of various IPs and controllers required for
Exynos5420.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: Akshay Saraswat
---
arch/arm/include/asm/arch-exynos/cpu.h | 48 +-
1 file changed, 47 insertions(+), 1 deletion(
From: Akshay Saraswat
Currently, part of TZPC init code for Exynos5 starts setting DECPROT
from the base address 0x1010 upto 0x1019 but in case of
Exynos5420 we need it to start from 0x0100E and keep end address
same as 0x1019.
Signed-off-by: Rajeshwari S Shinde
Signed-off-by: A
This patch adds basic board support for SMDK5420 board.
These patches are tested for booting fine on EVT0 SMDK5420.
Akshay Saraswat (6):
Exynos5420: Add base addresses for 5420
Exynos5420: Add clock initialization for 5420
Exynos5420: Add DDR3 initialization for 5420
Exynos5420: Modify TZP
Create a common board.c file for all functions which are common across
all EXYNOS5 platforms.
exynos_init function is provided for platform cpecific code.
Signed-off-by: Rajeshwari S Shinde
---
arch/arm/include/asm/arch-exynos/board.h | 17 ++
board/samsung/common/Makefile| 4 +
2013/9/2 Javier Martinez Canillas :
> There seems to be a naming convention for the configuration
> files for boards using the same SoC family. This makes
> easier to do changes that affect different boards based
> on the same SoC.
>
> Since the IGEPv2 board and the IGEP COM Module use a TI
> OMAP3
Dear Huang Shijie,
> 于 2013年09月02日 18:10, Hector Palacios 写道:
> > So does this mean that U-Boot is now unable to properly write a JFFS2
> > partition for it to be understood by the linux-next
>
> For the gpmi nand controller, the uboot is not proper to write a jffs2 now.
>
> > kernel? What is ex
于 2013年09月02日 18:10, Hector Palacios 写道:
So does this mean that U-Boot is now unable to properly write a JFFS2
partition for it to be understood by the linux-next
For the gpmi nand controller, the uboot is not proper to write a jffs2 now.
kernel? What is exactly the difference? Does it only aff
Dear Huang,
On 09/02/2013 10:50 AM, Huang Shijie wrote:
于 2013年09月02日 16:42, Hector Palacios 写道:
I am writing the JFFS2 partition from my custom U-Boot. Do you mean
that they way it writes it could not be compatible with what the new
driver expects? That sounds really bad.
The mtd code(as wel
There seems to be a naming convention for the configuration
files for boards using the same SoC family. This makes
easier to do changes that affect different boards based
on the same SoC.
Since the IGEPv2 board and the IGEP COM Module use a TI
OMAP35xx/DM37xx processor, is better to rename its boa
Hi Tom,
On Wednesday 28 August 2013 08:10 PM, Tom Rini wrote:
> On Wed, Jul 24, 2013 at 05:02:04PM +0300, Oleg Kosheliev wrote:
>
>> From: Oleg_Kosheliev
>>
>> The u-boot-spl image must be stored in SRAM at
>> addresses from 0x4030 till 0x4030bfff.
>> Higher than that area is located the ROM
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