Fix the following build warning in drivers/net/e1000.c
e1000.c: In function 'e1000_reset_hw':
e1000.c:1373:11: warning: variable 'icr' set but not used
[-Wunused-but-set-variable]
e1000.c: In function 'e1000_phy_init_script':
e1000.c:4395:11: warning: variable 'ret_val' set but not used
[-Wunuse
From: Jerry Huang
The new MPC8360EMDS board changes the oscillator to 33.33MHz
in order to support QE 500MHz since 2008.
Signed-off-by: Jerry Huang
CC: Kim Phillips
---
cahnges for v2:
- fix multiline comment wrong
changes for v3:
- change the oscillator to , not 333000
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Hi Mike,
On Sun, Nov 6, 2011 at 5:09 PM, Mike Frysinger wrote:
> On Sunday 06 November 2011 14:29:47 Simon Glass wrote:
>> On this particular patch, I feel it should be more explicit about L1
>> cache, which is what I think it deals with. We may want to support L2
>> also through a similar API. A
W związku z art. 10 ustawy z dnia 18 lipca 2002 r. o świadczeniu usług drogą
elektroniczną (Dz.U. nr 144, poz. 1204), zwracamy się z prośbą o pozwolenie na
przesłanie oferty dotyczącej:
- KURSÓW JĘZYKOWYCH DLA dla FIRM
- TŁUMACZEŃ PISEMNYCH I USTNYCH
Jeżeli Państwa firma będzie zaintereso
On Sunday 06 November 2011 14:29:47 Simon Glass wrote:
> On this particular patch, I feel it should be more explicit about L1
> cache, which is what I think it deals with. We may want to support L2
> also through a similar API. And a CONFIG option is a good idea.
the point of flushing caches is to
On Sunday 06 November 2011 13:07:29 Marek Vasut wrote:
> > On Sunday 06 November 2011 07:39:56 Marek Vasut wrote:
> > > > On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
> > > > > This patch should allow a CPU to register it's own cache ops. This
> > > > > shall allow multiple CPUs with di
Snapper 9G45 is a ARM9-based CPU module with 1GB NAND and 128MB
DDR SDRAM. This patch includes NAND and Ethernet support.
Signed-off-by: Simon Glass
---
Changes in v2:
- Removed unneeded i2c config
- Added machine type define
Changes in v3:
- Use CONFIG_MACH_TYPE instead of custom code
- Reduce
On Sunday, November 6, 2011, Ilya Yanok wrote:
> Hi Tom,
>
> 03.11.2011 4:33, Tom Rini wrote:
>>>
>>> these patches introduce support for HTKW mcx board (AM3517-based).
>>>
>>> Previously posted DaVinci EMAC patches
>>> ( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 )
>>> and NAND
Hi Tom,
03.11.2011 4:33, Tom Rini wrote:
>> these patches introduce support for HTKW mcx board (AM3517-based).
>>
>> Previously posted DaVinci EMAC patches
>> ( http://thread.gmane.org/gmane.comp.boot-loaders.u-boot/112309 )
>> and NAND SPL patches
>> ( http://thread.gmane.org/gmane.comp.boot-load
This should make sending out e-mails to the right people easier.
Signed-off-by: Mike Frysinger
---
doc/git-mailrc | 100
1 files changed, 100 insertions(+), 0 deletions(-)
create mode 100644 doc/git-mailrc
diff --git a/doc/git-mailrc b/
Dear Gerlando Falauto,
In message <1319647072-17504-1-git-send-email-gerlando.fala...@keymile.com> you
wrote:
> This is a resubmission (after removing remove checkpatch errors) of
> http://lists.denx.de/pipermail/u-boot/2011-September/102875.html
>
> Here I am proposing a set of changes in the b
Hi Wolfgang,
On Mon, Nov 7, 2011 at 6:50 AM, Wolfgang Denk wrote:
> Dear Graeme Russ,
>
> In message <4eb6e405.4060...@gmail.com> you wrote:
>>
>> > This being mostly cleanup, and we still being relatively early in the
>> > stabilization phase, I would also accept this stuff now.
>>
>> OK - There
Dear lau,
In message <2f8655c0.11b2c.1336c60d38a.coremail.laub...@163.com> you wrote:
>
> I find many uboot patches on mx28. Which branch do I clone source
> code from? I didn't find in master or other branches.
See branch "m28" in the u-boot-testing repo, i. e.
http://git.denx.de/?p=u-boot/u-boo
Dear Gerlando Falauto,
In message <1319647072-17504-1-git-send-email-gerlando.fala...@keymile.com> you
wrote:
> This is a resubmission (after removing remove checkpatch errors) of
> http://lists.denx.de/pipermail/u-boot/2011-September/102875.html
>
> Here I am proposing a set of changes in the b
Syntax: env regex [-g] [-s subst] regex name [...]
The code is based on SLRE (http://slre.sourceforge.net/)
which provides a tiny subset of Perl regular expressions.
Without options, this will implement regex pattern matching on
environment variables. Variables with matching values will be prin
Downloaded from http://slre.sourceforge.net/
and adapted for U-Boot environment.
Used to implement regex operations on environment variables.
Code size is ~ 3.5 KiB on PPC.
Signed-off-by: Wolfgang Denk
---
Note: This patch was generated on top of my ``env: fix "env ask"
command'' patch. This sho
The "env ask" traditionally uses a somewhat awkward syntax:
env ask name [message ...] [size]
So far, when a mesage was given, you always also had to enter a size.
If you forgot to do that, the command would terminate without any
indication of the problem.
To avoid incompatible changes o
Dear Graeme Russ,
In message <4eb6e405.4060...@gmail.com> you wrote:
>
> > This being mostly cleanup, and we still being relatively early in the
> > stabilization phase, I would also accept this stuff now.
>
> OK - There is only one patch that adds new 'features' - The 'Add multiboot
> header' b
Dear Mike Frysinger,
In message <20061306.37421.vap...@gentoo.org> you wrote:
>
> have you pushed out your master in a while ? i see your tree sitting at
> fec79acc864bed049b6beae719ccbf2bbec5403a which still has this warning. i
> also
> don't see commit ecfd752 in your tree.
master is i
Dear Stefan Schmidt,
In message <2006170219.GB20104@excalibur.local> you wrote:
>
> > Could you please be so kind and explain which exact issues you see for
> > such a separation?
>
> As Andrzej pointed out the DFU spec is written by the USB forum and
> one can see that there target are USB
Hi Wolfgang,
On 07/11/11 06:09, Wolfgang Denk wrote:
> Dear Graeme Russ,
>
> In message <4eb67a6e.2090...@gmail.com> you wrote:
>>
>> I have two x86 tidy-up patch series that I intend to apply in the next 2-3
>> weeks to a 'next' branch on the x86 repo. Being 'next', these patches are
>> intended
Acked-by: Anatolij Gustschin
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Acked-by: Anatolij Gustschin
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Hi,
On Sun, Nov 6, 2011 at 10:07 AM, Marek Vasut wrote:
>> On Sunday 06 November 2011 07:39:56 Marek Vasut wrote:
>> > > On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
>> > > > This patch should allow a CPU to register it's own cache ops. This
>> > > > shall allow multiple CPUs with dif
Dear Stefan Schmidt,
In message <2006163605.GA20104@excalibur.local> you wrote:
>
> > > usbtty interface as usb gadget as well as the runtime descripto for
> > > DFU. With dfu-util it was possible to iniate the DFU download or
> > > upload procedure while being in the mode. Another option wou
Dear Graeme Russ,
In message <4eb67a6e.2090...@gmail.com> you wrote:
>
> I have two x86 tidy-up patch series that I intend to apply in the next 2-3
> weeks to a 'next' branch on the x86 repo. Being 'next', these patches are
> intended for the current merge window which closes on December 12
You
> On Sunday 06 November 2011 07:39:56 Marek Vasut wrote:
> > > On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
> > > > This patch should allow a CPU to register it's own cache ops. This
> > > > shall allow multiple CPUs with different cache handlings to be
> > > > supported.
> > >
> > > s
On Saturday 05 November 2011 05:33:38 Wolfgang Denk wrote:
> Kim Phillips wrote:
> > This reverts commit a9f4fc3fe571cc99260b063ad0ff291d31bafed0.
> >
> > commit aab773a47a8f7f40b9d7c4877853b00d22fb1347 already fixed the
> > issue.
> >
> > --- a/arch/powerpc/lib/board.c
> > +++ b/arch/powerpc/lib
Acked-by: Mike Frysinger
-mike
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On Sunday 06 November 2011 07:39:56 Marek Vasut wrote:
> > On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
> > > This patch should allow a CPU to register it's own cache ops. This
> > > shall allow multiple CPUs with different cache handlings to be
> > > supported.
> >
> > sorry, what's t
Hi Wolfgang
On Sat, 5 Nov 2011, Wolfgang Denk wrote:
> Fix:
> ide.c: In function 'ide_preinit':
> ide.c:69:21: warning: array subscript is above array bounds
> [-Warray-bounds]
> ide.c:69:21: warning: array subscript is above array bounds
> [-Warray-bounds]
> ide.c:70:17: warning: array subscript
Hello.
On Sat, 2011-11-05 at 16:33, Wolfgang Denk wrote:
> In message <000601cc9abe$4f544bd0$edfce370$%p...@samsung.com> you wrote:
> >
> > > > http://www.usb.org/developers/devclass_docs/DFU_1.1.pdf
> >
> > DFU is part of USB; an extension to be precise, but an extension bound
> > so tightly to
Hello.
On Sat, 2011-11-05 at 16:31, Wolfgang Denk wrote:
> In message <2002200717.GP17069@excalibur.local> you wrote:
> >
> > While I think a dfu command is usefull I don't like the need to
> > execute it before any DFU interaction can happen. That may be an
> > option during development but f
Hi,
I am a newbie to bootloaders,
My requirement is to port u-boot + linux to a FPGA board (ARM926EJS +
video Coprocessors + basic peripherals (uart,ethernet))
I am basically trying to start u-boot from RAM since flash is already
locked with fpga code.
I happened to see some of mail chains about q
> On 11/06/2011 01:43 PM, Marek Vasut wrote:
> > Yes sure, but the controller driver sets it as a chip option as there's
> > no "controller" option field and I don't want to introduce new
> > definition consuming one bit in the top half of chip option.
>
> Let's see how evolve the discussion - all
On 11/06/2011 01:43 PM, Marek Vasut wrote:
>
> Yes sure, but the controller driver sets it as a chip option as there's no
> "controller" option field and I don't want to introduce new definition
> consuming
> one bit in the top half of chip option.
Let's see how evolve the discussion - allowin
> On 11/05/2011 03:24 AM, Marek Vasut wrote:
> > There is a problem reported that the NAND_NO_SUBPAGE_WRITE, set by some
> > drivers, is silently ignored by NAND core. This causes UBI to
> > malfunction on these drivers, because UBI tries to use subpage writes.
>
> Hi Marek,
>
> > This was discus
> On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
> > This patch should allow a CPU to register it's own cache ops. This shall
> > allow multiple CPUs with different cache handlings to be supported.
>
> sorry, what's the point ? this would make sense if you wanted to build one
> u- boot
Hi Wolfgang, Gabe,
I have two x86 tidy-up patch series that I intend to apply in the next 2-3
weeks to a 'next' branch on the x86 repo. Being 'next', these patches are
intended for the current merge window which closes on December 12
Please be aware that the latest series (checkpatch cleanup) is
Signed-off-by: Graeme Russ
---
./checkpatch.pl --no-tree -f arch/x86/lib/*.c
WARNING: externs should be avoided in .c files
#47: FILE: x86/lib/bios_setup.c:47:
+extern ulong __bios_start;
WARNING: externs should be avoided in .c files
#48: FILE: x86/lib/bios_setup.c:48:
+extern ulong __bios_size;
---
./checkpatch.pl --no-tree -f board/eNET/*.c
total: 0 errors, 0 warnings, 289 lines checked
board/eNET/eNET.c has no obvious style problems and is ready for submission.
WARNING: labels should not be indented
#89: FILE: eNET/eNET_pci.c:89:
+ fixup_irq: pci_enet_fixup_irq,
total: 0 errors,
Signed-off-by: Graeme Russ
---
./checkpatch.pl --no-tree -f arch/x86/cpu/sc520/*.c
total: 0 errors, 0 warnings, 66 lines checked
arch/x86/cpu/sc520/sc520.c has no obvious style problems and is ready for
submission.
WARNING: line over 80 characters
#84: FILE: x86/cpu/sc520/sc520_pci.c:84:
+
Signed-off-by: Graeme Russ
---
./checkpatch.pl --no-tree -f arch/x86/cpu/*.c
total: 0 errors, 0 warnings, 157 lines checked
arch/x86/cpu/cpu.c has no obvious style problems and is ready for submission.
total: 0 errors, 0 warnings, 675 lines checked
arch/x86/cpu/interrupts.c has no obvious style
Signed-off-by: Graeme Russ
---
arch/x86/cpu/interrupts.c | 20 ++--
1 files changed, 10 insertions(+), 10 deletions(-)
diff --git a/arch/x86/cpu/interrupts.c b/arch/x86/cpu/interrupts.c
index c6e72ea..89f39d2 100644
--- a/arch/x86/cpu/interrupts.c
+++ b/arch/x86/cpu/interrupts.
Mostly cosmetic (first patch is slight tweak that has no real functional
impact) fixes to the x86 arch. I've included checkpatch outputs for each of
the pure cosmetic patches (patches 2 through 5)
Graeme Russ (5):
x86: Call hang() on unrecoverable exception
cosmetic: checkpatch cleanup arch/x8
Fix:
ivm_core.c: In function 'ispVMLCOUNT':
ivm_core.c:2105:16: warning: unused variable 'usByte'
Signed-off-by: Stefano Babic
CC: Wolfgang Denk
---
drivers/fpga/ivm_core.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/drivers/fpga/ivm_core.c b/drivers/fpga/ivm_core.
Fix:
zmx25.c: In function 'board_late_init':
zmx25.c:131:25: warning: variable 'padctl' set but not used
[-Wunused-but-set-variable]
Signed-off-by: Stefano Babic
---
board/syteco/zmx25/zmx25.c |2 --
1 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/board/syteco/zmx25/zmx25.c b
Fix:
mx3fb.c: In function 'video_hw_init':
mx3fb.c:827:30: warning: variable 'vesa_idx' set but not used
Signed-off-by: Stefano Babic
CC: Anatolij Gustschin
---
drivers/video/mx3fb.c |3 +--
1 files changed, 1 insertions(+), 2 deletions(-)
diff --git a/drivers/video/mx3fb.c b/drivers/video
Dear Simon Glass,
In message
you wrote:
>
> Searching for "DTB append ARM zImage" provides lots of recent
> activity. The justification for this series seems to be old boot
> loaders. ...
True. In my understanding, this is only relevant to less capable boot
loaders (which not always are old -
On Saturday 05 November 2011 15:17:37 Simon Glass wrote:
> On Sat, Nov 5, 2011 at 10:13 AM, Mike Frysinger wrote:
> > On Saturday 05 November 2011 10:36:30 Simon Glass wrote:
> >> On Thu, Nov 3, 2011 at 6:36 PM, Mike Frysinger wrote:
> >> > On Thursday 03 November 2011 18:41:34 Simon Glass wrote:
>
On Saturday 05 November 2011 21:16:23 Marek Vasut wrote:
> This patch should allow a CPU to register it's own cache ops. This shall
> allow multiple CPUs with different cache handlings to be supported.
sorry, what's the point ? this would make sense if you wanted to build one u-
boot image to run
On 11/05/2011 03:24 AM, Marek Vasut wrote:
> There is a problem reported that the NAND_NO_SUBPAGE_WRITE, set by some
> drivers,
> is silently ignored by NAND core. This causes UBI to malfunction on these
> drivers, because UBI tries to use subpage writes.
>
Hi Marek,
> This was discussed alread
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