Wolfgang Denk wrote:
> Dear Bartek,
>
> In message <[EMAIL PROTECTED]> you wrote:
>>> Are seconds an appropriate scale factor for the timeout?
> ...
>> The patch didn't introduce changes in this regard -- TFTP timeouts were
>> defined in seconds originally. The patch makes the timeout behavior
>>
Hello,
2008/9/24 Gururaja Hebbar K R <[EMAIL PROTECTED]>:
[skip]
> So both are mutual exclusive and finally only one will be compiled.
Exactly! Really I didn't spot that subtle difference -- #ifdef, #ifndef.
Thanks for pointing out.
--
Roman Mashak
_
Hi,
> From: Roman Mashak [mailto:[EMAIL PROTECTED]
> Subject: Re: [U-Boot] PrimeCell Peripherals
> I must've confused you with the question.
No u havent. Sorry to say that u havent checked the code properly
> suppose we build U-Boot for arm920t based target, in such a
> case, two files defini
Hello,
2008/9/24 Gururaja Hebbar K R <[EMAIL PROTECTED]>:
>> I'm a bit confused: 'do_irq' is defined in several files,
>> including CPU-specific (arm920t, 720t etc.) and ARM
>> architecture library ($(U_BOOT)/lib_arm). So if we build for
>> arm920t-based platform (provided that CONFIG_USE_IRQ is
>
Hi Ben,
Sorry I keep mangling the patch.
I made an updated version based on the latest files from the git-tree.
If you don't mind, can you try applying it?
Thanks for all the help
-Richard
>From 61a47dbf76980860858417ae850f909a0552b123 Mon Sep 17 00:00:00 2001
From: Richard Retanubun <[EMAIL
Le mardi 23 septembre 2008 à 12:31 +0200, Remy Bohmer a écrit :
> Hello Stelian,
>
> Thanks for the logging. This is useful info.
>
> > usb_control_msg: request: 0x1, requesttype: 0x23, value 0x14 index 0x1
> > length 0x0
> > New Device 1
> > usb_control_msg: request: 0x6, requesttype: 0x80, val
On Sun, 2008-09-07 at 01:39 +0200, Wolfgang Denk wrote:
> Dear Jon,
>
> I have a couple of unapplied patches in my list which seem to fall
> into your area of responsibility. Can you please have a look at
> these:
>
> 6185 08/19 Kumar Gala [U-Boot] [PATCH] 86xx: remove redudant code
>
From: Haiying Wang <[EMAIL PROTECTED]>
Change UEC phy interface from GMII to RGMII on MPC8568MDS board
Because on MPC8568MDS, GMII interface is only recommended for 1000Mbps speed,
but RGMII interface can work at 10/100/1000Mbps, and RGMII interface works more
stable.
Now both UEC1 and UEC2 can
Hello all,
I'm searching for a patch that allows me to write yaffs2 images
(generated with mkyaffs2image from Aleph One Ltd.) to NAND flash with
u-boot.
After spending some time with the U-Boot sources I've found out, that
there seems not to exist a command for doing this.
An older patch from Fr
Hi Wolfgang
Andrew Dyer wrote:
>> Also, please enlighten me: what is "EFI", and what is a "GUID"
>> partition table, and which systems do use that?
>
> EFI is the PC BIOS replacement that Intel came up with, most notably
> used on Apple's Intel based computers. A blurb about EFI is here -
>
Wolfgang D.,
Please pull a ddr base address assignment fix, h/w flash protection
turned on by default, and a fix to facilitate autobooting:
The following changes since commit 8fd4166c467a46773f80208bda1ec3b4757747bc:
Stefan Roese (1):
ppc4xx: Canyonlands: Remove unnecessary FDT warning
bootdelay set to -1 'permanently' disables autobooting, even if
bootcmd is specified. Change to a positive value to allow
autobooting when a bootcmd is set.
Reported-by: Coray Tate <[EMAIL PROTECTED]>
Cc: Scott Wood <[EMAIL PROTECTED]>
Signed-off-by: Kim Phillips <[EMAIL PROTECTED]>
---
include/
Dear Jerry Van Baren,
In message <[EMAIL PROTECTED]> you wrote:
>
> Interestingly enough, dcbst is a *data* cache store, run in the *icache*
> flush routine. I assume this is intended to flush out any instructions
> that are stuck in the dcache due to writes (self modifying code and/or
> loaded/c
Dear Wolfgang,
Andrew Dyer wrote:
>> Also, please enlighten me: what is "EFI", and what is a "GUID"
>> partition table, and which systems do use that?
>
> EFI is the PC BIOS replacement that Intel came up with, most notably
> used on Apple's Intel based computers. A blurb about EFI is here -
>
Remi Lefevre wrote:
> Hi,
>
> From your experience, can some incomplete/incorrect U-Boot configuration
> lead to MMU init failures inside Linux ?
>
> Particularly, my Linux kernel fails during the first Data Cache Block Store
> instruction (dcbst) of the MMU init and I ask myself if this cannot b
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
> Provide a weak defined routine to retrieve the CPU number for reference
> boards that have multiple CPU's. Default behavior is the existing single CPU
> print output. Reference boards with multiple CPU's need to provide a board
> s
Dear Adam Graham,
In message <[EMAIL PROTECTED]> you wrote:
>
> +/*
> + * FPGA read/write helper macros
> + */
> +#define FPGA_READ(offset) ({ \
> + in_8((void *)(CFG_FPGA_BASE + offset)); })
> +#define FPGA_WRITE(offset, data) ({ \
> + out_8((void
(please CC me as I am not on the list yet).
--
From: Florian Fainelli <[EMAIL PROTECTED]>
Date: Wed, 24 Sep 2008 10:46:10 +0200
Subject: [PATCH] serial: add support for the OMRPv2 simple wishbone UART
This patch adds support for the wishbone UART we are using on the
OpenPattern Modular Routing Pla
This patch fixes building with CONFIG_API and COFNIG_USB_STORAGE.
USB_MAX_STOR_DEV is defined in include/usb.h, but
needed in api/api_storage.c.
Signed-off-by: Matthias Fuchs <[EMAIL PROTECTED]>
---
api/api_storage.c |4
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/api
Hi,
> From: Roman Mashak [mailto:[EMAIL PROTECTED]
> Subject: Re: [U-Boot] PrimeCell Peripherals
>
> I'm a bit confused: 'do_irq' is defined in several files,
> including CPU-specific (arm920t, 720t etc.) and ARM
> architecture library ($(U_BOOT)/lib_arm). So if we build for
> arm920t-based
Provide a weak defined routine to retrieve the CPU number for reference boards
that have multiple CPU's. Default behavior is the existing single CPU print
output. Reference boards with multiple CPU's need to provide a board specific
routine. See board/amcc/arches/arches.c for an example.
Sig
This patch add the capability to configure a PPC440 based IBM SDRAM Controller
with static, compiled-in, values. PPC440 memory subsystem includes a Memory
Queue core.
Signed-off-by: Adam Graham <[EMAIL PROTECTED]>
Signed-off-by: Victor Gallardo <[EMAIL PROTECTED]>
---
cpu/ppc4xx/44x_spd_ddr2
These are the initial support files for the AMCC dual PPC460GT Arches reference
board.
Signed-off-by: Adam Graham <[EMAIL PROTECTED]>
Signed-off-by: Victor Gallardo <[EMAIL PROTECTED]>
---
Makefile |3 +
board/amcc/arches/Makefile| 51
board/amcc/arches/arch
Hi,
>From your experience, can some incomplete/incorrect U-Boot configuration
lead to MMU init failures inside Linux ?
Particularly, my Linux kernel fails during the first Data Cache Block Store
instruction (dcbst) of the MMU init and I ask myself if this cannot be linked
to my cache initializati
Hello,
2008/9/23 Gururaja Hebbar K R <[EMAIL PROTECTED]>:
[skip]
> Then the user has to also define a do_irq command to support the same
>
> Kindly look at below file for do_irq function definitions & its usage.
>
> uboot\cpu\arm720t\interrupts.c
> uboot\cpu\arm920t\interrupts.c
>
> i havent seen
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