Re: [Sdcc-user] How do your interrupt handlers look like

2015-08-27 Thread Philipp Klaus Krause
On 26.08.2015 23:27, Wolle K. wrote: > Derived from ST Micro's workaround 2 (CD00237242.pdf, 1.1.3): > > Expecting a DIV / DIVW instruction in ISR, you can simply insert > > push #0x28 > pop cc > > at the beginning of interrupt handler. > > This is for concurrent interrupt handling only, fo

Re: [Sdcc-user] How do your interrupt handlers look like

2015-08-26 Thread Wolle K.
Derived from ST Micro's workaround 2 (CD00237242.pdf, 1.1.3):   Expecting a DIV / DIVW instruction in ISR, you can simply insert   push #0x28 pop cc   at the beginning of interrupt handler.   This is for concurrent interrupt handling only, for nested interrupts, the interruptability level

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-30 Thread Alan Cox
> > An interrupt in a divison which causes a context > > switch with any kind of taskswitcher/threader will also break when there > > is a divide in another thread that is scheduled. > > I am not familiar with context switches. I guess they would have to be > implemented in asm or relying on behvi

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-30 Thread Philipp Klaus Krause
On 29.07.2015 23:29, Alan Cox wrote: >> The information might be useful in improving a workaround for a hardware >> division issue (see bug #2401, RFE #448 / 449). > > As a ps to this, I think the question is a bit wider > (although I note you > fixed the bug anyway). Currently the bugfix / hardw

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread Alan Cox
> The information might be useful in improving a workaround for a hardware > division issue (see bug #2401, RFE #448 / 449). As a ps to this, I think the question is a bit wider (although I note you fixed the bug anyway). An interrupt in a divison which causes a context switch with any kind of tas

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread Alan Cox
On Wed, 29 Jul 2015 09:28:08 +0200 Philipp Klaus Krause wrote: > I wonder how interrupt andlers written by sdcc users look like, in > particular: > > * Do they contain divisions? > * Do they contain multiplications? > * Do they contain pointer arithmetic? > * Do they contain array accesses? > *

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread admin Utilisateur
Hi i am using only the assembler of stm8 for now, in some cases, when i ll need the compiler, i will use all that in my interupts, yes , it could be "overloading" but many times, we dont care , because all we do is "that" (handle that interrupt) i used gpasm many times, and i like to run the

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread roelof 't Hooft
Hi Philipp, I only use sdcc for the 8051 series of microcontrollers. On Wed, 2015-07-29 at 09:28 +0200, Philipp Klaus Krause wrote: > * Do they contain divisions ? Usually not > * Do they contain multiplications ? Usually not > * Do they contain pointer arithmetic ? Do you mean stuff like

Re: [Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread Maarten Brock
Hello Philipp, Pointer arithmetic and array access are very likely in an ISR. And that probably means underlying multiplications (or add or shift). Think buffers for UART/SPI/I2C/ADC/DAC. Averaging a set of ADC samples can also bring division (or shift). And non-power-of-2 sized ring buffers can

[Sdcc-user] How do your interrupt handlers look like

2015-07-29 Thread Philipp Klaus Krause
I wonder how interrupt andlers written by sdcc users look like, in particular: * Do they contain divisions? * Do they contain multiplications? * Do they contain pointer arithmetic? * Do they contain array accesses? * Do they contain shifts? * Do they call other functions? * Are those other called