Derived from ST Micro's workaround 2 (CD00237242.pdf, 1.1.3):
Expecting a DIV / DIVW instruction in ISR, you can simply insert
push #0x28
pop cc
at the beginning of interrupt handler.
This is for concurrent interrupt handling only, for nested interrupts, the interruptability level must be encoded:
push #0b00<i1>0<i0>000
pop cc
.
Advantage: 3 bytes of code, 2 execution cycles
Disadvantage: overrides Software priority register settings.
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