Hi, thanks
The MCS51 has the JBC instruction, which tests a bit, jumps if its set
and also clears the bit - all atomically. These would be perfect for
atomic flags. In addition the MCS51 supports an array of XCH
instructions which exchange the full accumulator with a
register/sfr/memory locat
Hi,
Currently I'm looking at making a sparse hardware re-implementation of
an mcs51-like core. It does not have to be 100% binary compatible as
long as it can run compiled C code.
Two opcodes are a nuisance to implement in hardware:
0xd6/0xd7: XCHD A,(Rx)
these opcodes take the place of wh
