QEMU v6.2 riscv64 device crash

2024-11-19 Thread Yanfeng
Dear experts, I am running a rv64 binary program which uses hypervisor extension v0.6.1 on QEMU with "virt" board. The same RiscV program can run on both QEMU v6.0 and v6.1, but it led to crash of QEMU v6.2: ``` ERROR:../..target/riscv/translate.c:232:get_gpr: code should not be reached Bail out!

Check riscv hypervisor page tables in GDB

2024-11-23 Thread Yanfeng
Dear experts, I am checking a working rv64 program with hypervisor extension on QEMU v6.1 via GDB. While V=0 and Priv=1, I can see page table pointed by $satp from GDB.  However, while V=1, I can read $hgatp from GDB, but can't read the page table any more: ``` (gdb) p/x $hgatp $4 = 0x80002

Re: Check riscv hypervisor page tables in GDB

2024-11-23 Thread Yanfeng
Sorry that I pasted wrong session in last email, it should be ``` (gdb) p/x $hgatp $5 = 0x80002008579a (gdb) p/x *(uint64_t*)0x8579a000 Cannot access memory at address 0x8579a000 ``` Regards, yf On Sat, 2024-11-23 at 21:24 +0800, Yanfeng wrote: > Dear experts, > > I am c

Re: semihosting option

2025-02-27 Thread Yanfeng Liu
On Thu, 2025-02-27 at 09:55 +, Peter Maydell wrote: > On Thu, 27 Feb 2025 at 05:44, Yanfeng Liu wrote: > > I am wondering QEMU semihosting for ARM or RISCV targets allows user to > > control > > the set of functions available in semihosting? for example, I want give &g

QEMU arm boot all CPUs

2025-02-27 Thread Yanfeng Liu
Dear experts, With `qemu-system-arm -M virt -smp 2`, it seems that secondary core is halted upon boot and needs be brought up via PSCI later. I am wondering if there is a way to tell QEMU to boot all cores upon boot without having to use PSCI? I couldn't find an option in the manual yet. Regards

Timer quality

2025-03-04 Thread Yanfeng Liu
Dear experts, I am wondering how the precision of timers are with QEMU on x64 Ubuntu Linux and TCG accelerator? Regards, yf

Re: Timer quality

2025-03-06 Thread Yanfeng Liu
ilities, thus all guest > instructions get executed natively by bare metal, and thus the need > to actually emulate instructions via the TCG gets minimized... > > Frank > > https://www.vmware.com/docs/vmware_timekeeping > https://wiki.osdev.org/APIC_Timer > https://airbus-seclab.git

semihosting option

2025-02-26 Thread Yanfeng Liu
Dear experts, I am wondering QEMU semihosting for ARM or RISCV targets allows user to control the set of functions available in semihosting? for example, I want give read- only host folder share and poweroff functions to a guest. Is this possible? Regards, yf