Re: [PATCH v2 2/8] target/riscv: add support for Zca and Zcf extensions

On 2022/11/14 05:40, Richard Henderson wrote: On 11/13/22 12:32, Weiwei Li wrote: +    } else if ((get_xl_max(ctx) == MXL_RV32) && +    !ctx->cfg_ptr->ext_zcf && +    (((opcode & 0xe003) == 0x6000) || + ((opcode & 0xe003) == 0x6

Re: [PATCH v2 5/8] target/riscv: add support for Zcmp extension

On 2022/11/15 21:44, Richard Henderson wrote: On 11/13/22 12:32, Weiwei Li wrote:   {     sq  101  ... ... .. ... 10 @c_sqsp     c_fsd   101   ..  . 10 @c_sdsp + +  # *** RV64 and RV32 Zcmp Extension *** +  cm_push 101  11000  .. 10 @zcmp +  cm_pop

Re: [PATCH v3 6/9] target/riscv: add support for Zcmp extension

Thanks for your detail comments! On 2022/11/17 17:44, Richard Henderson wrote: On 11/16/22 23:03, Weiwei Li wrote: Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   target/riscv/insn16.decode    |  18 ++   target/riscv

Re: [PATCH v3 7/9] target/riscv: add support for Zcmt extension

On 2022/11/17 17:56, Richard Henderson wrote: On 11/16/22 23:03, Weiwei Li wrote: +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index, + target_ulong next_pc) +{ +    target_ulong target = next_pc; +    target_ulong val = 0; +    int xlen

Re: [PATCH v3 7/9] target/riscv: add support for Zcmt extension

On 2022/11/18 04:57, Richard Henderson wrote: On 11/17/22 03:44, weiwei wrote: Missing a smstateen_check.  Not mentioned in the instruction description itself, but it is within the State Enable section of JVT. smstateen_check have been added in REQUIRE_ZCMT. Oh. I see.  That's wro

Re: [PATCH v3 7/9] target/riscv: add support for Zcmt extension

t now, it's incorrect usage of the tool and might just come back to cause bugs in the future.  Yeah, my previous assumption seems not very reasonable.  I'll try to take the check into the cm_jalt helper. Regards, Weiwei Li

Re: [PATCH v4 7/9] target/riscv: add support for Zcmt extension

On 2022/11/18 18:24, Richard Henderson wrote: On 11/17/22 23:17, Weiwei Li wrote: +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index, + target_ulong next_pc) +{ + +#if !defined(CONFIG_USER_ONLY) +    RISCVException ret = smstateen_acc_ok(env, 0

Re: [PATCH v6 2/9] target/riscv: add support for Zca extension

On 2022/11/29 07:06, Wilfred Mallawa wrote: On Mon, 2022-11-28 at 20:29 +0800, Weiwei Li wrote: Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis ---  target/riscv

Re: [PATCH v7 9/9] disas/riscv.c: add disasm support for Zc*

On 2022/11/30 11:04, Shaobo Song wrote: At 2022-11-29 10:43:43, "Weiwei Li" wrote: >Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* >instructions currently > >Signed-off-by: Weiwei Li >Signed-off-by: Junqiang Wang >Acked-by: Alistair Francis

Re: [PATCH v9 0/9] support subsets of code size reduction extension

On 2023/1/11 13:00, Alistair Francis wrote: On Wed, Dec 28, 2022 at 4:23 PM Weiwei Li wrote: This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available

Re: [PATCH 04/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

On 2023/2/14 02:02, Bin Meng wrote: There is no need to generate the CSR XML if the Zicsr extension is not enabled. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/gdbstub.c | 9 ++--- 1 file changed, 6 insertions(+), 3 deletions(-) diff --git

Re: [PATCH 05/18] target/riscv: Coding style fixes in csr.c

On 2023/2/14 02:02, Bin Meng wrote: Fix various places that violate QEMU coding style: - correct multi-line comment format - indent to opening parenthesis Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 62

Re: [Patch 05/14] target/riscv: Fix relationship between V, Zve*, F and D

On 2023/2/14 21:21, Daniel Henrique Barboza wrote: On 2/14/23 05:38, Weiwei Li wrote: Add dependence chain: *  V => Zve64d => Zve64f => Zve32f => F *  V => Zve64d => D Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang ---   target/riscv/cpu.c | 21

Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

On 2023/2/14 21:37, Daniel Henrique Barboza wrote: On 2/14/23 05:38, Weiwei Li wrote: Only V extension support EEW = 64 in these case: Zve64* extensions don't support EEW = 64 as commented "as commented" where? In the previous patch? Signed-off-by: Weiwei Li Signed-o

Re: [PATCH 08/18] target/riscv: Simplify getting RISCVCPU pointer from env

On 2023/2/14 02:02, Bin Meng wrote: Use env_archcpu() to get RISCVCPU pointer from env directly. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 36 1 file changed, 12 insertions(+), 24 deletions(-) diff

Re: [PATCH 11/18] target/riscv: gdbstub: Drop the vector CSRs in riscv-vector.xml

ort vector registers for rv64 & rv32") inserted these vector CSRs in an ad-hoc, non-standard way in the riscv-vector.xml. Now we can treat these CSRs no different from other CSRs. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/r

Re: [PATCH 06/18] target/riscv: Use 'bool' type for read_only

On 2023/2/14 02:02, Bin Meng wrote: The read_only variable is currently declared as an 'int', but it should really be a 'bool'. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 delet

Re: [PATCH 10/18] target/riscv: gdbstub: Turn on debugger mode before calling CSR predicate()

up in the riscv-csr.xml so the ones in riscv-*-fpu.xml are redundant. But unforuantely that is not ture. typo here -> true otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li As the FPU CSR predicate() has a run-time check on MSTATUS.FS, at the time when CSR XML is generated MSTATUS.FS is

Re: [PATCH 15/18] target/riscv: Allow debugger to access sstc CSRs

debugger check. Signed-off-by: Bin Meng Similar typo, otherwise Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 19 ++- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index d6bcb7f275..c6a7745cb2 100644

Re: [PATCH 09/18] target/riscv: Avoid reporting odd-numbered pmpcfgX in the CSR XML for RV64

ctual read/write routine to the PMP CSR predicate() routine, so that non-existent pmpcfgX won't be reported in the CSR XML for RV64. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 23 --- 1 file changed, 8 insertions(+

Re: [PATCH 07/18] target/riscv: Simplify {read,write}_pmpcfg() a little bit

On 2023/2/14 02:02, Bin Meng wrote: Use the register index that has already been calculated in the pmpcfg_csr_{read,write} call. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff

Re: [PATCH 14/18] target/riscv: Allow debugger to access {h, s}stateen CSRs

-by: Bin Meng Similar typo, Otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 22 -- 1 file changed, 20 insertions(+), 2 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index f1075b5728..d6bcb7f275 100644 --- a/target

Re: [PATCH 16/18] target/riscv: Drop priv level check in mseccfg predicate()

: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index c6a7745cb2..40aae9e7b3 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -450,7 +450,7 @@ static RISCVException pmp

Re: [PATCH 01/18] target/riscv: gdbstub: Check priv spec version before reporting CSR

m gdb. Add the priv spec version check in the CSR XML generation logic to fix this issue. Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12") Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/gdbstub.c | 3 +++ 1 file cha

Re: [PATCH 02/18] target/riscv: Correct the priority policy of riscv_csrrw_check()

in these cases.  *  Read-only  check will trigger ILLEGAL_INST exception which is  also the exception triggered when      CSR is not existed, so put this check before existence check will not affect the final exception. Regards, Weiwei Li Fixes: eacaf4401956 ("target/riscv: Fix pri

Re: [PATCH 12/18] target/riscv: Allow debugger to access user timer and counter CSRs

On 2023/2/14 09:09, Bin Meng wrote: At present user timer and counter CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by addding a debugger check in their predicate() routine. typo: adding Otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li Signed-off-by: Bin

Re: [PATCH 17/18] target/riscv: Group all predicate() routines together

On 2023/2/14 12:31, Bin Meng wrote: Move sstc()/sstc32() to where all predicate() routines live. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 108 ++--- 1 file changed, 54 insertions(+), 54

Re: [PATCH 03/18] target/riscv: gdbstub: Minor change for better readability

On 2023/2/14 02:01, Bin Meng wrote: Use a variable 'base_reg' to represent cs->gdb_num_regs so that the call to ricsv_gen_dynamic_vector_xml() can be placed in one single line for better readability. Signed-off-by: Bin Meng Reviewed-by: Weiwei Li Regards, Weiwei Li ---

Re: [PATCH 13/18] target/riscv: Allow debugger to access seed CSR

On 2023/2/14 09:09, Bin Meng wrote: At present seed CSR is not reported in the CSR XML hence gdb cannot access it. Fix it by addding a debugger check in its predicate() routine. typo: adding Otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li Signed-off-by: Bin Meng --- target

Re: [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate()

check seems not right here.  Why  ILLEGAL_INST is directly triggered if smstateen is enabled? It seems that smstateen related check will be done  for senvcfg/henvcfg{h} when smstateen is enabled. Regards, Weiwei Li + +switch (csrno) { +case CSR_SENVCFG: +predicate = smode

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

On 2023/2/11 19:50, Daniel Henrique Barboza wrote: On 2/10/23 23:43, weiwei wrote: On 2023/2/10 21:36, Daniel Henrique Barboza wrote: At this moment, and apparently since ever, we have no way of enabling RISCV_FEATURE_MISA. This means that all the code from write_misa(), all the nuts and

Re: [PATCH 03/11] target/riscv: remove RISCV_FEATURE_MISA

On 2023/2/10 21:36, Daniel Henrique Barboza wrote: This enum is no longer used after write_misa() started reading the value from cpu->cfg.misa_w. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li r Regards, Weiwei Li --- target/riscv/cpu.h | 1 - 1 file changed

Re: [PATCH 04/11] target/riscv: introduce riscv_cpu_cfg()

enrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 6509ffa951..00a464c9c4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -654,6 +654,11 @@ static

Re: [PATCH 05/11] target/riscv: remove RISCV_FEATURE_DEBUG

On 2023/2/10 21:36, Daniel Henrique Barboza wrote: RISCV_FEATURE_DEBUG will always follow the value defined by cpu->cfg.debug flag. Read the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.c

Re: [PATCH 06/11] target/riscv/cpu.c: error out if EPMP is enabled without PMP

: EPMP requires PMP support This will force users to pick saner options in the QEMU command line. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/target/riscv

Re: [PATCH 07/11] target/riscv: remove RISCV_FEATURE_EPMP

On 2023/2/10 21:36, Daniel Henrique Barboza wrote: RISCV_FEATURE_EPMP is always set to the same value as the cpu->cfg.epmp flag. Use the flag directly. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.c | 10 +++--- tar

Re: [PATCH 08/11] target/riscv: remove RISCV_FEATURE_PMP

On 2023/2/10 21:36, Daniel Henrique Barboza wrote: RISCV_FEATURE_PMP is being set via riscv_set_feature() by mirroring the cpu->cfg.pmp flag. Use the flag instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.c

Re: [PATCH 09/11] hw/riscv/virt.c: do not use RISCV_FEATURE_MMU in create_fdt_socket_cpus()

cpu >= 0; cpu--) { +RISCVCPU *cpu_ptr = &s->soc[socket].harts[cpu]; +RISCVCPUConfig cpu_cfg = cpu_ptr->cfg; Adding cpu_cfg seems not very necessary. Otherwise, Reviewed-by: Weiwei Li Regards, Weiwei Li cpu_phandle = (*phandle)++; cpu_name = g_s

Re: [PATCH 10/11] target/riscv: remove RISCV_FEATURE_MMU

ed in it, predates the existence of the cpu->cfg object. Today, using cpu->cfg is an easier way to retrieve all the features and extensions enabled in the hart. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.c| 4 targ

Re: [PATCH 11/11] target/riscv/cpu: remove CPUArchState^features and friends

id and minimal_version_id since 'features' is no longer being migrated. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.h | 12 target/riscv/machine.c | 5 ++--- 2 files changed, 2 insertions(+), 15 deletions(-) dif

Re: [PATCH 18/18] target/riscv: Move configuration check to envcfg CSRs predicate()

On 2023/2/15 10:22, Bin Meng wrote: On Tue, Feb 14, 2023 at 10:59 PM weiwei wrote: On 2023/2/14 22:27, Bin Meng wrote: At present the envcfg CSRs predicate() routines are generic one like smode(), hmode. The configuration check is done in the read / write routine. Create a new predicate

Re: [PATCH v3 02/10] target/riscv: always allow write_misa() to write MISA

think it's better to add a limitation(such as  writable_mask) to the changable fields of misa here. Regards, Weiwei Li /* 'I' or 'E' must be present */ if (!(val & (RVI | RVE))) { /* It is not, drop write to misa */

Re: [PATCH v6 1/9] target/riscv: turn write_misa() into an official no-op

Signed-off-by: Daniel Henrique Barboza Reviewed-by: Bin Meng Reviewed-by: Andrew Jones Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.h | 1 - target/riscv/csr.c | 55 -- 2 files changed, 56 deletions(-) diff --git a/target

Re: [PATCH v6 2/9] target/riscv: introduce riscv_cpu_cfg()

enrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu.h | 5 + 1 file changed, 5 insertions(+) diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 01803a020d..5e9626837b 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -653,6 +653,11 @@ static

Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble

On 2023/2/18 00:10, Ivan Klokov wrote: Due to typo in opcode list, ctzw is disassembled as clzw instruction. Fixes: 02c1b569a15b ("disas/riscv: Add Zb[abcs] instructions") Signed-off-by: Ivan Klokov --- v2: - added fixes line Reviewed-by: Weiwei Li Weiwei Li --- disas/r

Re: [PATCH v6 2/4] target/riscv: implement Zicboz extension

&& !get_field(env->menvcfg, envbits) should be put before upper check. Illegal instruction exception should be triggered if (env->priv < PRV_M) && !get_field(env->menvcfg, envbits). However, virtual instruction exception may be triggered if we do upper check fir

Re: [PATCH v1 5/7] contrib/gitdm: add ISCAS to the academics group

On 2022/9/26 21:46, Alex Bennée wrote: The English website (http://english.is.cas.cn/) in on a slightly different domain but has the same logo as http://www.iscas.ac.cn/. Signed-off-by: Alex Bennée Cc: Weiwei Li --- contrib/gitdm/group-map-academics | 3 +++ 1 file changed, 3 insertions

Re: [PATCH v9 1/4] target/riscv: Add smstateen support

target_ulong new_val) +{ +return write_mstateen(env, csrno, SMSTATEEN_STATEEN, new_val); +} I still prefer mstateen1~3 to share the same read/write function currently. If you  insist on distinguishing them, I think it's better to pass index directly  than pa

Re: [PATCH v9 3/4] target/riscv: smstateen check for fcsr

wever, smstateen_check  is for accessing fcsr CSR, It may trigger illegal or  virtual instruction exception based on the privilege mode and Xstateen CSRs. Regards, Weiwei Li diff --git a/target/riscv/insn_trans/trans_rvzfh.c.inc b/target/riscv/insn_trans/trans_rvzfh.c.inc index 5d07150cd0..44d962c92

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

+} + +if (!(stateen & SMSTATEEN0_FCSR)) { +if (ctx->virt_enabled) { +ctx->virt_inst_excp = true; +} Are there any considerations for adding  virt_inst_excp instead of directly "generate_exception(ctx, RISCV_EXCP_VIRT_INSTRUCTION_FAULT)" here? Rega

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

On 2022/10/4 14:51, mchit...@ventanamicro.com wrote: On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: On 2022/10/3 19:47, Mayuresh Chitale wrote: If smstateen is implemented and sstateen0.fcsr is clear then the floating point operations must return illegal instruction exception or virtual

Re: [RFC 6/8] target/riscv: delete redundant check for zcd instructions in decode_opc

On 2022/10/25 11:39, Alistair Francis wrote: On Fri, Sep 30, 2022 at 11:28 AM Weiwei Li wrote: All the check for Zcd instructions have been done in their trans function Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/translate.c | 7 --- 1 file changed, 7

Re: [PATCH] MAINTAINERS: Add some RISC-V reviewers

96e25f62ac..847bc7f131 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -287,6 +287,9 @@ RISC-V TCG CPUs M: Palmer Dabbelt M: Alistair Francis M: Bin Meng +R: Weiwei Li +R: Daniel Henrique Barboza +R: Liu Zhiwei L: qemu-ri...@nongnu.org S: Supported F: target/riscv/ Acked-by: Weiwei Li

Re: [PATCH 01/11] target/riscv: do not mask unsupported QEMU extensions in write_misa()

ported QEMU extensions pass by, misa_ext_mask itself needs to be fixed instead. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/csr.c | 3 --- 1 file changed, 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index

Re: [PATCH 02/11] target/riscv: allow users to actually write the MISA CSR

; + +if (!cpu->cfg.misa_w) { It's Ok to get it directly from cfg. However, personally, I prefer to keep the non-isa features in a separate list. Regards, Weiwei Li /* drop write to misa */ return RISCV_EXCP_NONE; }

Re: [PATCH] target/riscv: avoid env_archcpu() in cpu_get_tb_cpu_state()

On 2023/2/10 20:38, Daniel Henrique Barboza wrote: We have a RISCVCPU *cpu pointer available at the start of the function. Signed-off-by: Daniel Henrique Barboza Reviewed-by: Weiwei Li Regards, Weiwei Li --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion

Re: [PATCH v1 RFC Zisslpcfi 1/9] target/riscv: adding zimops and zisslpcfi extension to RISCV cpu config

+DEFINE_PROP_BOOL("zimops", RISCVCPU, cfg.ext_zimops, true), These properties can not expose to users before all its functions are ready. And it need add 'x-' prefix as experimental extensions currently. Regards, Weiwei Li DEFINE_PROP_BOOL("short-isa-string

Re: [PATCH v1 RFC Zisslpcfi 2/9] target/riscv: zisslpcfi CSR, bit positions and other definitions

lt; 9, +MSECCFG_MFCFIEN = 1 << 10 It's unnecessary to use multiple space after '='. Regards, Weiwei Li } mseccfg_field_t; typedef struct {

Re: [PATCH] target/riscv: Fix vslide1up.vf and vslide1down.vf

; \ Reviewed-by: Weiwei Li Regards, Weiwei Li

Re: [PATCH v10 3/5] target/riscv: generate virtual instruction exception

e this gen_exception_illegal. By the way, why not just put  "ctx->virt_inst_excp = false;" at the begin of the decode_opc? Regards, Weiwei Li } else { +ctx->virt_inst_excp = false; ctx->opcode = opcode; ctx->pc_succ_insn = ctx->bas

Re: [PATCH v10 4/5] target/riscv: smstateen check for fcsr

On 2022/10/7 01:06, mchit...@ventanamicro.com wrote: On Tue, 2022-10-04 at 21:23 +0800, weiwei wrote: On 2022/10/4 14:51, mchit...@ventanamicro.com wrote: On Mon, 2022-10-03 at 21:02 +0800, weiwei wrote: On 2022/10/3 19:47, Mayuresh Chitale wrote: If smstateen is implemented and sstateen0

Re: [PATCH v11 3/5] target/riscv: generate virtual instruction exception

if (insn_len(opcode) == 2) { if (!has_ext(ctx, RVC)) { Reviewed-by: Weiwei Li Regards, Weiwei Li

[PATCH v3 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++ target/riscv/translate.c | 2

[PATCH v3 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ 2 files changed, 22 insertions(+), 4 deletions

[PATCH v3 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode| 18 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 242 +- target/riscv/translate.c | 5 + 3 files

[PATCH v3 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 ++-- 2 files changed, 8 insertions(+), 4 deletions(-) diff --git a/target/riscv

[PATCH v3 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h | 6 ++ 2 files changed, 49

[PATCH v3 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 2 + target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c

[PATCH v3 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v3 0/9] support subsets of code size reduction extension

c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf extension target/riscv: add support for Zcd extension target/riscv: add supp

[PATCH v3 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ab04ab246..b9e41df96c 100644

[PATCH v3 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv

[PATCH v4 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v4 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ab04ab246..b9e41df96c 100644

[PATCH v4 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++ target/riscv

[PATCH v4 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 ++-- 2 files changed, 8 insertions(+), 4

[PATCH v4 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv

[PATCH v4 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189 +- target/riscv/translate.c | 5 + 3 files

[PATCH v4 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h | 6

[PATCH v4 0/9] support subsets of code size reduction extension

ca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension target/riscv: add support for Zca extension target/riscv: add support for Zcf

[PATCH v4 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ 2 files changed, 22

[PATCH v4 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c

[PATCH v5 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv

[PATCH v5 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ 2 files changed, 22

[PATCH v5 0/9] support subsets of code size reduction extension

ead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt Weiwei Li (9): target/riscv: add cfg properties for Zc* extension tar

[PATCH v5 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c

[PATCH v5 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 ++-- 2 files changed, 8 insertions(+), 4

[PATCH v5 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++ target/riscv

[PATCH v5 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h | 6

[PATCH v5 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c b

[PATCH v5 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ab04ab246..b9e41df96c 100644

[PATCH v5 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189 +- target/riscv/translate.c

[PATCH v6 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 9f4aa0fe55..64027a07e6 100644

[PATCH v6 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 ++-- 2 files

[PATCH v6 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18

[PATCH v6 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189

[PATCH v6 0/9] support subsets of code size reduction extension

to the way of Zcd * update Zcb to reuse gen_load/store * use trans function instead of helper for push/pop v2: * add check for relationship between Zca/Zcf/Zcd with C/F/D based on related discussion in review of Zc* spec * separate c.fld{sp}/fsd{sp} with fld{sp}/fsd{sp} before support of zcmp/zcmt

[PATCH v6 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h

[PATCH v6 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Acked-by: Alistair Francis --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion

[PATCH v6 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson Reviewed-by: Alistair Francis --- target/riscv/cpu.h| 4 ++ target/riscv

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