Re: [Patch 13/14] target/riscv: Simplify check for EEW = 64 in trans_rvv.c.inc

[weiwei]

On 2023/2/14 21:37, Daniel Henrique Barboza wrote:

On 2/14/23 05:38, Weiwei Li wrote:

Only V extension support EEW = 64 in these case: Zve64* extensions
don't support EEW = 64 as commented

"as commented" where? In the previous patch?

Signed-off-by: Weiwei Li <liwei...@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqi...@iscas.ac.cn>
---

The code LGTM.

Reviewed-by: Daniel Henrique Barboza <dbarb...@ventanamicro.com>

  target/riscv/insn_trans/trans_rvv.c.inc | 12 ++++--------
  1 file changed, 4 insertions(+), 8 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc

index 5dbdce073b..fc0d0d60e8 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc

@@ -1998,8 +1998,7 @@ static bool vmulh_vv_check(DisasContext *s, arg_rmrr *a)

       * are not included for EEW=64 in Zve64*. (Section 18.2)
       */

".... are not included for EEW=64 in Zve64*. (Section 18.2) "

The comment is here, and similar comments can be found in following code.

Regards,

Weiwei Li

      return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }
    static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)

@@ -2012,8 +2011,7 @@ static bool vmulh_vx_check(DisasContext *s, arg_rmrr *a)

       * are not included for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }
    GEN_OPIVV_GVEC_TRANS(vmul_vv,  mul)

@@ -2230,8 +2228,7 @@ static bool vsmul_vv_check(DisasContext *s, arg_rmrr *a)

       * for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivv_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }
    static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)

@@ -2242,8 +2239,7 @@ static bool vsmul_vx_check(DisasContext *s, arg_rmrr *a)

       * for EEW=64 in Zve64*. (Section 18.2)
       */
      return opivx_check(s, a) &&
-           (!has_ext(s, RVV) &&
-            s->cfg_ptr->ext_zve64f ? s->sew != MO_64 : true);
+           (!has_ext(s, RVV) ? s->sew != MO_64 : true);
  }
    GEN_OPIVV_TRANS(vsmul_vv, vsmul_vv_check)