Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register test
hw/intc/armv7m_nvic.c | 69 +--
tests/Makefile.include| 2 +
tests/tcg/arm/test-reserved-reg.c | 60 +++
3 fil
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5ee229eb35..83cca554ad 100644
--- a/target/arm/helper.c
On 05.07.2018 13:33, Peter Maydell wrote:
On 4 July 2018 at 21:36, Julia Suvorova wrote:
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
target/arm/helper.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/target/ar
On 05.07.2018 13:54, Peter Maydell wrote:
On 4 July 2018 at 20:58, Julia Suvorova wrote:
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 69 +++
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register test
hw/intc/armv7m_n
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the
checks, because these registers are reserved in ARMv8-M Baseline too.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 51 +++
ht (c) 2018 Julia Suvorova
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2
+ * or later. See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+static void test_reserved_reg(void)
+{
+QTestSt
On 06.07.2018 00:50, Julia Suvorova wrote:
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Ad
ht (c) 2018 Julia Suvorova
+ *
+ * This work is licensed under the terms of the GNU GPL, version 2
+ * or later. See the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "libqtest.h"
+
+static void test_reserved_reg(void)
+{
+QTestSt
Handle SCS reserved registers listed in ARMv6-M ARM D3.6.1.
All reserved registers are RAZ/WI. ARM_FEATURE_M_MAIN is used for the
checks, because these registers are reserved in ARMv8-M Baseline too.
Signed-off-by: Julia Suvorova
---
hw/intc/armv7m_nvic.c | 51 +++
v3:
* Fix indents
v2:
* Use ARM_FEATURE_M_MAIN instead of ARM_FEATURE_V7 in most cases
* Remove CPUID registers check
* Use bad_offset instead of return
* Misc style fixes
Julia Suvorova (2):
nvic: Handle ARMv6-M SCS reserved registers
tests: Add ARMv6-M reserved register t
MSR handling is the only place where CONTROL.nPRIV is modified.
Signed-off-by: Julia Suvorova
---
v2:
* Add the check in the CONTROL_NS case
target/arm/helper.c | 12
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
hw/intc/arm
v7m.ccr[M_REG_NS] = 0x3f8;
+env->v7m.ccr[M_REG_S] = 0x3f8;
+}
+
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
* that it resets to 1, so QEMU always does that rather than making
* it dependent on CPU model. In v8M it is R
Hi!
I noticed that when I build QEMU from git for the first time, it pulls
in submodules over the insecure git:// protocol - in other words, as
far as I can tell, if I'm e.g. on an open wifi network while building
QEMU for the first time, even if I cloned the main repository over
https, a
On Sun, Jul 15, 2018 at 11:18 PM Peter Maydell wrote:
>
> On 15 July 2018 at 20:50, Jann Horn via Qemu-devel
> wrote:
> > I noticed that when I build QEMU from git for the first time, it pulls
> > in submodules over the insecure git:// protocol - in other words, as
> >
ccr[M_REG_NS] = R_V7M_CCR_STKALIGN_MASK;
env->v7m.ccr[M_REG_S] = R_V7M_CCR_STKALIGN_MASK;
My bad; I'll put the assignments that you mentioned into if/else block.
+}
+
/* In v7M the reset value of this bit is IMPDEF, but ARM recommends
* that it resets to 1, so QEMU alw
On 17.07.2018 16:49, Peter Maydell wrote:
On 17 July 2018 at 14:42, Julia Suvorova wrote:
On 17.07.2018 16:09, Peter Maydell wrote:
This should be outside the "if v8" if(), because you also want it for v6M
(giving you the v6M CCR value of STKALIGN and UNALIGN_TRP set and all
other bits clear).
On 17.07.2018 [13:25:53 -0400], Farhan Ali wrote:
> Hi,
>
> I am seeing some strange QEMU assertion failures for qemu on s390x,
> which prevents a guest from starting.
>
> Git bisecting points to the following commit as the source of the
Forbid stack alignment change. (CCR)
Reserve FAULTMASK, BASEPRI registers.
Report any fault as a HardFault. Disable MemManage, BusFault and
UsageFault, so they always escalated to HardFault. (SHCSR)
Signed-off-by: Julia Suvorova
---
v2:
* Changed CCR reset value
hw/intc/armv7m_nvic.c | 10 +
On 17.07.2018 15:58, Peter Maydell wrote:
On 10 July 2018 at 16:33, Julia Suvorova wrote:
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M s
est (it might have silently been falling back to threaded IO?). I
> > > don't have access to s390x, but would it be possible to run qemu under
> > > gdb and see if aio_setup_linux_aio is being called at all (I think it
> > > might not be, but I'm not sure why), an
Kevin Wolf
Cc: John Snow
Cc: Max Reitz
Cc: Stefan Hajnoczi
Cc: Fam Zheng
Cc: Paolo Bonzini
Cc: qemu-bl...@nongnu.org
Cc: qemu-devel@nongnu.org
---
block/file-posix.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/block/file-posix.c b/block/file-posix.c
index 60af4b3d51..ad299beb38 100
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M supports 4 priority levels against 256 in ARMv7-M.
Signed-off-by: Julia Suvorova
---
v2:
* Ad
t;> I am not too familiar with block device code in QEMU, so not sure if
> >> this is the right fix or if there are some underlying problems.
> >
> > Oh this is quite embarassing! I only added the bdrv_attach_aio_context
> > callback for the file-backed device. Your fi
On 19.07.2018 19:25, Peter Maydell wrote:
On 19 July 2018 at 13:16, Julia Suvorova wrote:
The differences from ARMv7-M NVIC are:
* ARMv6-M only supports up to 32 external interrupts
(configurable feature already). The ICTR is reserved.
* Active Bit Register is reserved.
* ARMv6-M s
On 20.07.2018 [15:11:14 -0400], Farhan Ali wrote:
> I am seeing another issue pop up, in a different test. Even though it's a
> different assertion, it might be related based on the call trace.
Just to be clear, this does not happen if you revert the original patch
(i.e., the one you bisected to b
Ive been looking into the possibility of using a unix signal to send an
acpi shutdown request to a VM, and came across a posting on this l in
March 1. See
https://lists.nongnu.org/archive/html/qemu-devel/2017-03/msg04169.html
To summarise to refresh memories there was a patch proposed using
ght (c) 2018 Julia Suvorova
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include "qemu/log.h"
+#include
nRF51 SoC implementation is intended for the BBC Micro:bit board,
which has 256 KB flash and 16 KB RAM.
Added FICR defines.
Signed-off-by: Julia Suvorova
---
hw/arm/nrf51_soc.c | 12 +++-
include/hw/arm/nrf51_soc.h | 1 +
2 files changed, 8 insertions(+), 5 deletions(-)
diff --
This series adds basic support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
Based-on: <20180503090532.3113-1-j...@jms.id.au>
Julia Suvorova (3):
hw/arm/nrf51_soc: Fix compilation and memory regions
hw/char/nrf51_uart: Implement nRF51 SoC UART
tests/boot-serial
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
---
tests/boot-serial-test.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 4d6815c3e0..e6dbc8a293 100644
--- a/tests/boot-serial-test.c
+++ b/tests/
bug! I'll fix this.
>> +if (r <= 0) {
>> +s->watch_tag = qemu_chr_fe_add_watch(&s->chr, G_IO_OUT | G_IO_HUP,
>> + uart_transmit, s);
>> +if (!s->watch_tag) {
>> +g
On 01.06.2018 13:44, Stefan Hajnoczi wrote:
On Fri, Jun 1, 2018 at 11:41 AM, Stefan Hajnoczi wrote:
On Thu, May 31, 2018 at 2:58 PM, sundeep subbaraya
wrote:
On Wed, May 30, 2018 at 3:33 AM, Julia Suvorova via Qemu-devel
wrote:
+static uint64_t uart_read(void *opaque, hwaddr addr, unsigned
1. Add support for all platforms
2. Add option to map in shared mode, allowing the guest to write
through to the backing file
Taken together, this allows one to write RAM snapshots as the guest is
running. Saving RAM snapshots is then equivalent to exiting the qemu
process or unmapping the file
1. Add support for all platforms
2. Add option to map in shared mode, allowing the guest to write
through to the backing file
Taken together, this allows one to write RAM snapshots as the guest is
running. Saving RAM snapshots is then equivalent to exiting the qemu
process or unmapping the file
I see you point. Just close this issue.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1775366
Title:
[Feature request] qemu-ga - Allow unexpected parameter
Status in QEMU:
New
Bug description
+ * http://infocenter.nordicsemi.com/pdf/nRF51_RM_v3.0.1.pdf
+ *
+ * Copyright 2018 Joel Stanley
+ *
+ * This code is licensed under the GPL version 2 or later. See
+ * the COPYING file in the top-level directory.
+ */
+
+#include "qemu/osdep.h"
+#include "qapi/error.h"
+#in
When scanout_mode enabled, surface is out of sync with actual screen.
In such case, we just call sdl2_gl_scanout_flush to do redraw. This
fixes bug reported in
https://lists.freedesktop.org/archives/virglrenderer-devel/2018-July/001330.html
Signed-off-by: Tao Wu
---
ui/sdl2-gl.c | 5 +
1 fil
move this #include
> line, Rebecca?
Sorry for the delay, I'm just getting back to this. Removing the include
causes it to fail later on, with:
/home/bcran/workspace/qemu/hw/rdma/vmw/pvrdma_cmd.c:60:17: warning:
implicit declaration of function 'mremap' is invalid in
On Sat, Jul 28, 2018, 13:53 Samuel Thibault wrote:
> Hello,
>
> aoa...@google.com, le mer. 25 juil. 2018 21:08:12 -0400, a ecrit:
> > From: Andrew Oates
> >
> > On Linux, SOCK_DGRAM+IPPROTO_ICMP sockets give only the ICMP packet when
> > read from. On macOS, however, the socket acts like a SOCK
On 7/25/18 1:32 AM, Thomas Huth wrote:
>
> When was it still working for you the last time? Was it still working
> with v3.0-rc1 ? Or just with v2.12 ? Any chance that you could bisect
> the problem to determine when it has been introduced?
I'm not sure if it's FreeBSD that might have changed to
Yeah, I suspect (but haven't tested) that this applies to all BSDs. We
could switch CONFIG_DARWIN to CONFIG_BSD (happy to resend the patch, just
LMK).
Agreed that platform-specific ifdefs are gross, but I don't see a better
way here :/ One option would be to look at the packet length and content
The current emulation will clear the XCH bit when a burst finishes.
This is not quite correct. According to the i.MX7d referemce manual,
Rev 0.1, §10.1.7.3:
This bit [XCH] is cleared automatically when all data in the TXFIFO
and the shift register has been shifted out.
So XCH should be c
On Tue, Jul 31, 2018 at 6:22 AM Peter Maydell
wrote:
> On 31 July 2018 at 02:16, Andrew Oates wrote:
> > Yeah, I suspect (but haven't tested) that this applies to all BSDs. We
> > could switch CONFIG_DARWIN to CONFIG_BSD (happy to resend the patch, just
> > LMK).
> >
> > Agreed that platform-sp
On Wed, Aug 1, 2018 at 6:10 AM Peter Maydell
wrote:
> On 1 August 2018 at 00:25, Andrew Oates wrote:
> > Both CONFIG_BSD and not-CONFIG_LINUX work on macOS. I unfortunately
> don't
> > have access to any other BSDs to test them, though.
>
> Is there an easy way t
On 30.07.2018 17:02, Joel Stanley wrote:
On 26 July 2018 at 20:31, Julia Suvorova wrote:
+++ b/hw/arm/nrf51_soc.c
+static void nrf51_soc_init(Object *obj)
+{
+NRF51State *s = NRF51_SOC(obj);
+
+memory_region_init(&s->container, obj, "nrf51-container",
UINT64_MAX);
+
+object_init
On 08.08.2018 12:09, Stefan Hajnoczi wrote:
On Mon, Aug 6, 2018 at 11:01 AM, Steffen Görtz
wrote:
+#define PAGE_SIZE 1024
+#define FLASH_SIZE (256 * PAGE_SIZE)
+#define FLASH_BASE 0x
+#define UICR_BASE 0x10001000
+#define UICR_SIZE 0x100
+
This series adds support for the nRF51 SoC UART, that used in
BBC Micro:bit board, and QTest for it.
v2:
* Suspend/Enable functionality added
* Connection to SoC moved to a separate patch
* Added QTest for checking reception functionality
* Mini-kernel test changed to fit current i
51_RM_v3.0.pdf
+ *
+ * Copyright (c) 2018 Julia Suvorova
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 or
+ * (at your option) any later version.
+ */
+
+#include "qemu/osdep.h"
+#include &q
CE(&s->uart), sysbus_get_default());
}
static Property nrf51_soc_properties[] = {
diff --git a/include/hw/arm/nrf51_soc.h b/include/hw/arm/nrf51_soc.h
index e380ec26b8..46a1c1a66c 100644
--- a/include/hw/arm/nrf51_soc.h
+++ b/include/hw/arm/nrf51_soc.h
@@ -13,6 +13,7 @@
#include "q
rtions(+), 3 deletions(-)
diff --git a/tests/microbit-test.c b/tests/microbit-test.c
index 08e2210916..8b69d83684 100644
--- a/tests/microbit-test.c
+++ b/tests/microbit-test.c
@@ -17,7 +17,10 @@
#include "qemu/osdep.h"
#include "exec/hwaddr.h"
#include "libqtest.h&q
New mini-kernel test for nRF51 SoC UART.
Signed-off-by: Julia Suvorova
---
tests/boot-serial-test.c | 19 +++
1 file changed, 19 insertions(+)
diff --git a/tests/boot-serial-test.c b/tests/boot-serial-test.c
index 952a2e7ead..19714c3f87 100644
--- a/tests/boot-serial-test.c
+++
Some devices (like nvic in armv7m) are not accessable through
address_space_memory, therefore can not be tested with qtest.
Signed-off-by: Julia Suvorova
---
qtest.c | 39 ++-
1 file changed, 26 insertions(+), 13 deletions(-)
diff --git a/qtest.c b/qtest.c
in
Currently call gates are always treated as 32-bit gates. In IA-32e mode
(either compatibility or 64-bit submode), system segment descriptors are
always 64-bit. Treating them as 32-bit has the expected unfortunate
effect: only the lower 32 bits of the offset are loaded, the stack
pointer is trunca
h CONFIG_BSD and not-CONFIG_LINUX work on macOS. I unfortunately
>> don't
>> > have access to any other BSDs to test them, though.
>>
>> Is there an easy way to test it? The QEMU makefiles have some
>> runes for setting up a BSD VM...
>>
>
>
I have a patch for that, it was designed to run NVMe for MacOS guests
and implements at least the bare minimum of the spec. I'll try to polish
it up and upstream it as soon as I have time.
** Patch added: "0001-Enough-GetLogCmd-for-macOS.patch"
https://bugs.launchpad.net/qe
On Sun, Aug 12, 2018 at 6:17 AM Paolo Bonzini wrote:
> On 12/08/2018 05:07, Andrew Oates via Qemu-devel wrote:
> > Currently call gates are always treated as 32-bit gates. In IA-32e mode
> > (either compatibility or 64-bit submode), system segment descriptors are
> > alw
L, true);
+}
unrealize() should set the handlers to NULL. That way the device can
be removed without leaving callbacks registered.
I don't know the reason, but almost all char devices do not implement
this function. Maybe, because when you quit qemu, qemu_chr_cleanup() is called.
Best regards, Julia Suvorova.
Fixup some typos in the comments.
Signed-off-by: Julia Suvorova
---
include/chardev/char-fe.h | 10 +-
1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h
index 71cd069478..c67271f1ba 100644
--- a/include/chardev/char-fe.h
+
l-socket.h"
#include "io/channel-tls.h"
+#include "io/channel-websock.h"
#include "io/net-listener.h"
#include "qemu/error-report.h"
#include "qemu/option.h"
@@ -69,6 +70,8 @@ typedef struct {
GSource *telnet_source;
TCPChardev
Hi!
I have noticed that when a QEMU build from git master is started with
"-seccomp on", the seccomp policy is only applied to the main thread,
the vcpu worker thread and the VNC thread (I'm using VNC in my
config); the seccomp policy is not applied to e.g. the RCU thread
becaus
Ah got it, thanks for the replies / info!
We're using a modified QEMU 2.12, and I don't see the migratable-only loops
and field, so it either got missed in the rebase or was added after 2.12.
Frank
On Mon, Aug 13, 2018 at 9:45 AM Dr. David Alan Gilbert
wrote:
> * Paolo B
qemu_chr_fe_set_handlers(&s->chr, uart_can_receive, uart_receive,
+ uart_event, NULL, s, NULL, true);
+}
unrealize() should set the handlers to NULL. That way the device can
be removed without leaving callbacks registered.
I don't know the reason, but almost all
On 13.08.2018 15:02, Paolo Bonzini wrote:
Thanks Julia, just a few cleanups to simplify the prototypes of some
functions.
Thanks for the review, I'll do the refactoring.
Best regards, Julia Suvorova.
On 13.08.2018 15:21, Daniel P. Berrangé wrote:
On Mon, Aug 13, 2018 at 01:20:37PM +0300, Julia Suvorova via Qemu-devel wrote:
New option "websock" added to allow using websocket protocol for
chardev socket backend.
Example:
-chardev socket,websock,id=...
Signed-off-by: Juli
On Tue, Aug 14, 2018 at 11:52 AM Peter Maydell
wrote:
> On 12 August 2018 at 04:11, Andrew Oates wrote:
> > Ping --- would you like me to resubmit the patch using CONFIG_BSD?
>
> Yes, that seems our best option. Could you please also include
> a comment that summarises the behaviour of the other
On Linux, SOCK_DGRAM+IPPROTO_ICMP sockets give only the ICMP packet when
read from. On macOS, however, the socket acts like a SOCK_RAW socket
and includes the IP header as well.
This change strips the extra IP header from the received packet on macOS
before sending it to the guest. SOCK_DGRAM IC
On Wed, Aug 15, 2018 at 7:03 AM Samuel Thibault
wrote:
> Andrew Oates, le mar. 14 août 2018 22:35:21 -0400, a ecrit:
> > On Linux, SOCK_DGRAM+IPPROTO_ICMP sockets give only the ICMP packet when
> > read from. On macOS, however, the socket acts like a SOCK_RAW socket
> > and includes the IP heade
SPI or UART and then simulate the composite system
as a single machine where each of the cores runs a separate firmware.
Is something like this easy to implement given current processor
objects or does this require substantial changes to how qemu works?
One area I do not fully understand is native
ecure exception 3
Taking exception 17 [v7M NOCP UsageFault]
qemu: fatal: Lockup: can't escalate 3 to HardFault (current priority -1)
Ok so FPU support is not there. What would it take for me to add it? I
would very much like to add it if I get some guidance as to what needs
to be done and where
g works. Why I
> don't know.
>
> It seems the HardFault is preceded by two UsageFaults:
> Taking exception 17 [v7M NOCP UsageFault]
> ...taking pending nonsecure exception 3
> Taking exception 17 [v7M NOCP UsageFault]
> qemu: fatal: Lockup: can't escalate 3 to HardFaul
evice, deliver the notification of a gpio pin being toggled to the
slave device.
How does qemu implement this kind of thing?
On 21.08.2018 14:43, Steffen Görtz wrote:
Hi Peter,
+
+static uint64_t clock_read(void *opaque, hwaddr addr, unsigned int size)
+{
+qemu_log_mask(LOG_UNIMP, "%s: 0x%" HWADDR_PRIx " [%u]\n",
+ __func__, addr, size);
+return 1;
+}
+
+static void clock_write(void *opaque, h
gpio pin. I need to make sure that it gets
called every time master device calls qemu_set_irq.
What's the mechanism behind this behavior and how can I deliver gpio
change to the slave?
On Tue, Aug 21, 2018 at 3:57 PM Peter Maydell wrote:
>
> On 21 August 2018 at 14:29, Martin Schroeder via
This is
> > necessary because plug/unplug currently assume they do not fail.
> >
> > It is trivial to make qemu segfault in my testing. Set
> > /proc/sys/fs/aio-max-nr to 0 and start a guest with
> > aio=native,cache=directsync. With this patch, the guest successfully
>
is the same as if s->use_linux_aio was not
set (but there is no bubbling up). In all three cases, if the setup
function fails, we fallback to the thread pool and an error message is
emitted.
It is trivial to make qemu segfault in my testing. Set
/proc/sys/fs/aio-max-nr to 0 and start a guest w
On 17.06.2018 19:33, Peter Maydell wrote:
On 17 June 2018 at 06:36, Richard Henderson
wrote:
On 06/15/2018 12:55 AM, Peter Maydell wrote:
+uint32_t armv6m_insn[] = {0xf3808000 /* msr */, 0xf3b08040 /* dsb */,
+ 0xf3b08050 /* dmb */, 0xf3b08060 /* isb */,
+
The arrays were made static, "if" was simplified because V7M and V8M
define V6 feature.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 27 +--
1 file changed, 13 insertions(+), 14 deletions(-)
diff --git a/target/arm/translate.c b/target/arm/translate.c
index
On 19.06.2018 [14:35:33 -0500], Eric Blake wrote:
> On 06/15/2018 12:47 PM, Nishanth Aravamudan via Qemu-devel wrote:
> > laio_init() can fail for a couple of reasons, which will lead to a NULL
> > pointer dereference in laio_attach_aio_context().
> >
> > To solve this
Unlike ARMv7-M, ARMv6-M only supports naturally aligned memory accesses
for 16-bit halfword and 32-bit word accesses using the LDR, LDRH,
LDRSH, STR and STRH instructions.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deleti
On 19.06.2018 [13:14:51 -0700], Nishanth Aravamudan wrote:
> On 19.06.2018 [14:35:33 -0500], Eric Blake wrote:
> > On 06/15/2018 12:47 PM, Nishanth Aravamudan via Qemu-devel wrote:
> > > } else if (s->use_linux_aio) {
> > > +
On 19.06.2018 [15:35:57 -0700], Nishanth Aravamudan wrote:
> On 19.06.2018 [13:14:51 -0700], Nishanth Aravamudan wrote:
> > On 19.06.2018 [14:35:33 -0500], Eric Blake wrote:
> > > On 06/15/2018 12:47 PM, Nishanth Aravamudan via Qemu-devel wrote:
>
>
>
>
35:33 -0500], Eric Blake wrote:
> > > > > On 06/15/2018 12:47 PM, Nishanth Aravamudan via Qemu-devel wrote:
> > >
> > >
> > >
> > > > > > } else if (s->use_linux_aio) {
> > > > > > +int rc;
&g
018 [13:14:51 -0700], Nishanth Aravamudan wrote:
> > > > > On 19.06.2018 [14:35:33 -0500], Eric Blake wrote:
> > > > > > On 06/15/2018 12:47 PM, Nishanth Aravamudan via Qemu-devel wrote:
> > > >
> > > >
> > > >
> > > >
ishanth Aravamudan geschrieben:
> > > > > On 19.06.2018 [15:35:57 -0700], Nishanth Aravamudan wrote:
> > > > > > On 19.06.2018 [13:14:51 -0700], Nishanth Aravamudan wrote:
> > > > > > > On 19.06.2018 [14:35:33 -0500], Eric Bla
When the AioContext changes, we need to associate a LinuxAioState with
the new AioContext. Use the bdrv_attach_aio_context callback and call
the new aio_setup_linux_aio(), which will allocate a new AioContext if
needed, and return errors on failures. If it fails for any reason,
fallback to threaded
laio_init() can fail for a couple of reasons, which will lead to a NULL
pointer dereference in laio_attach_aio_context(), called from
aio_get_linux_aio().
Test case 1:
Set /proc/sys/fs/max-aio-nr to 0. Start a guest with an aio=native
disk.
Result: laio_init() returns NULL due to not
laio_init() can fail for a couple of reasons, which will lead to a NULL
pointer dereference in laio_attach_aio_context().
To solve this, add a aio_setup_linux_aio() function which is called
early in raw_open_common. If this fails, propagate the error up. The
signature of aio_get_linux_aio() was no
This feature is intended to distinguish ARMv8-M variants: Baseline and
Mainline. ARMv7-M compatibility requires the Main Extension. ARMv6-M
compatibility is provided by all ARMv8-M implementations.
Signed-off-by: Julia Suvorova
---
target/arm/cpu.c | 3 +++
target/arm/cpu.h | 1 +
2 files change
Unlike ARMv7-M, ARMv6-M and ARMv8-M Baseline only supports naturally
aligned memory accesses for load/store instructions.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 18 --
1 file changed, 16 insertions(+), 2 deletions(-)
diff --git a/target/arm/translate.c b/targ
v2:
* Added feature bit for the Main Extention
* Alignment patch is modified to use ARM_FEATURE_M_MAIN
Julia Suvorova (2):
target/arm: Introduce ARM_FEATURE_M_MAIN
target/arm: Strict alignment for ARMv6-M and ARMv8-M Baseline
target/arm/cpu.c | 3 +++
target/arm/cpu.h |
On 22.06.2018 [10:21:19 +0800], Fam Zheng wrote:
> On Thu, 06/21 15:21, Nishanth Aravamudan wrote:
> > laio_init() can fail for a couple of reasons, which will lead to a NULL
> > pointer dereference in laio_attach_aio_context().
> >
> > To solve this, add a aio_setup_linux_aio() function which is
On 22.06.2018 [11:02:06 +0200], Kevin Wolf wrote:
> Am 22.06.2018 um 04:25 hat Fam Zheng geschrieben:
> > On Thu, 06/21 15:21, Nishanth Aravamudan wrote:
> > > When the AioContext changes, we need to associate a LinuxAioState with
> > > the new AioContext. Use the bdrv_attach_aio_context callback a
gth,
diff --git a/block/linux-aio.c b/block/linux-aio.c
index 88b8d55ec7..19eb922fdd 100644
--- a/block/linux-aio.c
+++ b/block/linux-aio.c
@@ -15,6 +15,7 @@
#include "block/raw-aio.h"
#include "qemu/event_notifier.h"
#include "qemu/coroutine.h"
+#
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required for future Cortex-M0 support.
Signed-off-by: Julia Suvorova
---
target/arm/translate.c | 35
On 13.06.2018 17:05, Stefan Hajnoczi wrote:
On Tue, Jun 12, 2018 at 11:46:32PM +0300, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This pa
this new function before calling
blk_io_plug() (which eventually calls aio_get_linux_aio). This is
necessary because plug/unplug currently assume they do not fail.
It is trivial to make qemu segfault in my testing. Set
/proc/sys/fs/aio-max-nr to 0 and start a guest with
aio=native,cache=directsync
On 15.06.2018 13:55, Peter Maydell wrote:
On 12 June 2018 at 21:46, Julia Suvorova wrote:
ARMv6-M supports 6 Thumb2 instructions. This patch checks for these
instructions and allows their execution.
Like Thumb2 cores, ARMv6-M always interprets BL instruction as 32-bit.
This patch is required f
ply the version 1607 patch (if you
don't do that, you can never apply the patch). After applying this
Windows patch, Windows can detect and use the TPM device assigned to it
successfully.
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