Hi Emilio,
On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota wrote:
> This will enable us to decouple code translation from the value
> of parallel_cpus at any given time. It will also help us minimize
> TB flushes when generating code via EXCP_ATOMIC.
>
> Note that the declaration of parallel_cpus
oot+shutdown test).
Signed-off-by: Pranith Kumar
---
cpus-common.c | 85 ---
1 file changed, 70 insertions(+), 15 deletions(-)
diff --git a/cpus-common.c b/cpus-common.c
index 59f751ecf9..a1c4c7d1a3 100644
--- a/cpus-common.c
+++ b/c
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/tcg-op.c | 17
Update the comment which is not true since MTTCG.
Signed-off-by: Pranith Kumar
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a/target/arm/translate-a64.c
+++ b
On Mon, Aug 28, 2017 at 1:57 PM, Richard Henderson wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h
>> index 55a46ac825..b41a248bee 100644
>> --- a/tcg/aarch64/tcg-target.h
>> +++ b/tcg/aarch6
On Mon, Aug 28, 2017 at 1:47 PM, Richard Henderson
wrote:
> On 08/27/2017 08:53 PM, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
>> continously, we can cache th
On Mon, Aug 28, 2017 at 3:05 PM, Emilio G. Cota wrote:
> On Sun, Aug 27, 2017 at 23:53:25 -0400, Pranith Kumar wrote:
>> Using heaptrack, I found that quite a few of our temporary allocations
>> are coming from allocating work items. Instead of doing this
>> continou
Update the comment which is not true since MTTCG.
Reviewed-by: Richard Henderson
Signed-off-by: Pranith Kumar
---
target/arm/translate-a64.c | 4
1 file changed, 4 deletions(-)
diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c
index 2200e25be0..f42b155d7d 100644
--- a
error margins, however I think
the
patch is still worth. We can also explore atomics instead of taking a lock for
the work item pool.
Signed-off-by: Pranith Kumar
---
cpus-common.c | 75 +++
1 file changed, 60 insertions(+), 15 deletions
optimization pass.
This patch allows us to boot an x86 guest on ARM64 hosts using mttcg.
Signed-off-by: Pranith Kumar
---
tcg/tcg-op.c | 16
1 file changed, 16 insertions(+)
diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
index 87f673ef49..688d91755b 100644
--- a/tcg/tcg-op.c
+++ b/tcg/tcg
Signed-off-by: Pranith Kumar
---
tcg/aarch64/tcg-target.h | 2 ++
tcg/arm/tcg-target.h | 2 ++
tcg/ia64/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 2 ++
tcg/ppc/tcg-target.h | 2 ++
tcg/s390/tcg-target.h| 2 ++
tcg/sparc/tcg-target.h | 2 ++
7 files changed, 14 insertions
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
4K-sized cache.
Signed-off-by: Pranith Kumar
---
include/exec/cpu-defs.h | 5 -
tcg/aarch64/tcg-target.h | 1 +
tcg/i386/tcg-target.h| 2 ++
tcg/mips/tcg-target.h| 1 +
tcg/s390/tcg-target.h| 1 +
tcg/sparc/tcg-target.h | 1 +
6 files changed, 10 insertions(+), 1 deletion
}
> -
> -/* increment number */
> - for(j=7;j>0 && entry->name[j]=='9';j--)
> -entry->name[j]='0';
> -if(j>0) {
> -if(entry->name[j]<'0' || entry->name[j]>'9')
> -entry->name[j]='0';
> -else
> -entry->name[j]++;
> -}
> -}
> +entry = create_short_filename(s, filename, directory_start);
>
> /* calculate checksum; propagate to long name */
> if(entry_long) {
> --
> 2.11.0
>
>
--
Pranith
On Mon, Aug 7, 2017 at 7:07 AM, Eric Blake wrote:
> On 08/05/2017 01:52 PM, Pranith Kumar wrote:
>> FYI,
>>
>> This commit breaks the build with gcc-7:
>>
>> CC block/vvfat.o
>> qemu/block/vvfat.c: In function ‘read_directory’:
>> qemu/block/vv
(s->pc - pc_start > 15) {
+s->pc = pc_start;
+goto illegal_op;
+}
return s->pc;
illegal_op:
gen_illegal_opcode(s);
Thanks,
--
Pranith
eration, so the effect will be
> "execute instruction, then take illegal-opcode
> exception".
>
The pc is restored to original address (s->pc = pc_start), so the
exception will overwrite the generated illegal instruction and will be
executed first.
But yes, it's better to follow the architecture manual.
Thanks,
--
Pranith
On Wed, Mar 22, 2017 at 11:21 AM, Peter Maydell
wrote:
> On 22 March 2017 at 15:14, Pranith Kumar wrote:
>> On Wed, Mar 22, 2017 at 11:04 AM, Peter Maydell
>> wrote:
>>> This doesn't look right because it means we'll check
>>> only after we'v
@ -4418,6 +4418,11 @@ static target_ulong disas_insn(CPUX86State
*env, DisasContext *s,
s->vex_l = 0;
s->vex_v = 0;
next_byte:
+/* The prefixes can atmost be 14 bytes since x86 has an upper
+ limit of 15 bytes for the instruction */
+if (s->pc - pc_start > 14) {
+goto illegal_op;
+}
b = cpu_ldub_code(env, s->pc);
s->pc++;
/* Collect prefixes. */
--
Pranith
to merge this patch to
> community, it's ok or not? Thanks.
>
Your patch seems to be missing. Can you retry with the content of the
patch pasted in the email?
Thanks,
--
Pranith
On Thu, Mar 23, 2017 at 1:37 PM, Paolo Bonzini wrote:
>
>
> On 23/03/2017 17:50, Pranith Kumar wrote:
>> On Thu, Mar 23, 2017 at 6:27 AM, Paolo Bonzini wrote:
>>>
>>>
>>> On 22/03/2017 21:01, Richard Henderson wrote:
>>>>>
>>>>
This fixes the bug: 'user-to-root privesc inside VM via bad translation
caching' reported by Jann Horn here:
https://bugs.chromium.org/p/project-zero/issues/detail?id=1122
CC: Richard Henderson
CC: Peter Maydell
CC: Paolo Bonzini
Reported-by: Jann Horn
Signed-off-by: Pra
ni
Reported-by: Jann Horn
Signed-off-by: Pranith Kumar
---
target/i386/translate.c | 7 +++
1 file changed, 7 insertions(+)
diff --git a/target/i386/translate.c b/target/i386/translate.c
index 72c1b03a2a..1d1372fb43 100644
--- a/target/i386/translate.c
+++ b/target/i386/translate.c
@@ -
easily implementable to increase
TCG performance as part of this project or otherwise.
Thanks,
--
Pranith
Hi Stefan,
On Mon, Mar 27, 2017 at 11:54 AM, Stefan Hajnoczi wrote:
> On Sat, Mar 25, 2017 at 12:52:35PM -0400, Pranith Kumar wrote:
>> Alex Bennée, who mentored me last year, has agreed to mentor me again this
>> time if the proposal is accepted.
>
> Thanks, the project ide
e the TB and the code, then we get exactly the right number
> of TBs allocated with no further effort.
>
> There will be some additional memory wastage, since we'll want to keep the
> code and the data in different cache lines and that means padding, but I
> don't think that'll be significant. Indeed, given the above over-allocation
> will probably still be a net savings.
>
If you think the project makes sense, I will add it to the GSoC wiki
so that others can also apply for it. Please let me know if you are
interested in mentoring it along with Alex.
Thanks,
--
Pranith
Hi Paolo,
On Mon, Mar 27, 2017 at 7:32 AM, Paolo Bonzini wrote:
>
>
> On 25/03/2017 17:52, Pranith Kumar wrote:
>> * Implement an LRU translation block code cache.
>>
>> In the current TCG design, when the translation cache fills up, we flush
>> all
>>
On Mon, Mar 27, 2017 at 11:03 PM, Pranith Kumar wrote:
>
> If you think the project makes sense, I will add it to the GSoC wiki
> so that others can also apply for it. Please let me know if you are
> interested in mentoring it along with Alex.
>
One other thing is if you think t
TCG uses the AMD cpu which warns when we use hyperthreading. Disable
the warning for TCG since it is not necessary.
Signed-off-by: Pranith Kumar
---
target/i386/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7aa762245a
Hi Michael,
qemu-riscv64 seg faults for me on a static binary. You can build the
binary from here: https://github.com/pranith/quickht
$ STATIC=1 RISCV=1 make
$ qemu-riscv64 ./bench -t 1 -u 1
Thanks,
--
Pranith
On second looks, running the benchmark on a RISCV processor is also
giving a seg fault. So may be there is something wrong with the
benchmark... OTOH, x86 version runs fine... hmm
Please ignore this report, I will try to investigate further.
Thanks,
On Mon, Sep 3, 2018 at 12:45 AM Pranith Kumar
ault
~/quickht$ ./bench -t 2 -u 2
Comparisons: 23922
Buckets touched: 4933
Operations: 2000
--
Pranith
x86_64 system
$ gcc --version
gcc (Ubuntu 5.4.1-2ubuntu1~16.04) 5.4.1 20160904
Error:
/home/pranith/devops/code/qemu/linux-user/ioctls.h:224:9: error:
‘SNDCTL_DSP_MAPINBUF’ undeclared here (not in a function)
IOCTL(SNDCTL_DSP_MAPINBUF, IOC_R, MK_PTR(MK_STRUCT(STRUCT_buffmem_desc
On Sun, Dec 11, 2016 at 2:09 PM, Pranith Kumar wrote:
> Hi,
>
> I am getting a strange compilation error lately for aarch64-linux-user. I
> think it is somehow related to TYPE_PTRVOID handling but my investigation has
> not led to anything concrete. I think this is a compiler
On Sun, Dec 11, 2016 at 5:59 PM, Peter Maydell wrote:
>
>> Error:
>> /home/pranith/devops/code/qemu/linux-user/ioctls.h:224:9: error:
>> ‘SNDCTL_DSP_MAPINBUF’ undeclared here (not in a function)
>>IOCTL(SNDCTL_DSP_MAPINBUF, IOC_R, MK_PTR(MK
through some other package which overwrote soundcard.h. It
was working fine earlier.
--
Pranith
On Tue, Aug 29, 2017 at 11:01 AM, Richard Henderson
wrote:
> On 08/28/2017 11:33 PM, Pranith Kumar wrote:
>> + * TODO: rewrite this comment
>> */
>> -#define CPU_TLB_BITS
%) | 919.02(+3.6%) |
|10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) |
|12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) |
The best combination for this workload came out to be 12 bits for the
TLB and a 16 entry vTLB cache.
Signed-off-by: Pranith Kumar
Fix the following warning:
/home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is only
applied to the left hand side of this bitwise operator
[-Wlogical-not-parentheses]
if (!c->gicr_ctlr & GICR_CTLR_ENABLE_LPIS) {
^ ~
/home/
I should have worded the subject better. The warning is pointing to an
actual bug.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only applied to the left hand
On Tue, Aug 29, 2017 at 5:16 PM, Emilio G. Cota wrote:
> On Sun, Aug 27, 2017 at 18:15:50 -0400, Pranith Kumar wrote:
>> Hi Emilio,
>>
>> On Fri, Jul 21, 2017 at 1:59 AM, Emilio G. Cota wrote:
>> > This will enable us to decouple code translation from the value
>
CC'ing stable for 2.10.
On Tue, Aug 29, 2017 at 1:32 PM, Pranith Kumar wrote:
> Fix the following warning:
>
> /home/pranith/qemu/hw/intc/arm_gicv3_kvm.c:296:17: warning: logical not is
> only applied to the left hand side of this bitwise operator
> [-Wlogical-not-parenthes
On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson wrote:
> On 08/29/2017 10:23 AM, Pranith Kumar wrote:
>> This patch increases the number of entries cached in the TLB. I went
>> over a few architectures to see if increasing it is problematic. Only
>> armv6 seems to have a l
Hi Alex,
On Tue, Sep 5, 2017 at 8:02 AM, Alex Bennée wrote:
>
> Pranith Kumar writes:
>
>> Update the comment which is not true since MTTCG.
>
> What happened to the cover letter? We seem to have a mix of patches but
> no summary of the overall outcome.
>
These are a
alternative is to encrypt the "qemu/qemu" repository so that
only the main repository updates are posted on
IRC. (ref. https://github.com/facebook/flow/pull/1822).
Signed-off-by: Pranith Kumar
---
.travis.yml | 4
1 file changed, 4 insertions(+)
diff --git a/.travis.yml b/.travis.yml
ind
ations" ?
>
This does the later. If we prefer the former, we need to encrypt the
IRC channel as suggested in:
https://github.com/facebook/flow/pull/1822
--
Pranith
On Mon, Jun 27, 2016 at 1:28 PM, Peter Maydell wrote:
> On 27 June 2016 at 18:18, Pranith Kumar wrote:
>> On Mon, Jun 27, 2016 at 1:16 PM, Peter Maydell
>> wrote:
>>>>
>>>> +branches:
>>>> + only:
>>>> +- master
>&g
to notify the IRC only for the main repo.
Signed-off-by: Pranith Kumar
CC: serge.f...@gmail.com
CC: peter.mayd...@linaro.org
---
.travis.yml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/.travis.yml b/.travis.yml
index c13881e..b6b1daf 100644
--- a/.travis.yml
+++ b/.
On Mon, Jun 27, 2016 at 1:40 PM, Peter Maydell wrote:
> On 27 June 2016 at 18:34, Pranith Kumar wrote:
>> The idea is to encrypt "irc.oftc.net#qemu" against "qemu/qemu" to
>> generate an ecrypted string like follows:
>>
>> $ travis encrypt -r "
to notify the IRC only for the main repo.
Signed-off-by: Pranith Kumar
CC: serge.f...@gmail.com
CC: peter.mayd...@linaro.org
---
v2: Add comment about what the string is and how the string is generated
.travis.yml | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/.tr
Tracing configurations error out currently as follows:
/home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c: In function
‘aspeed_scu_read’:
/home/travis/build/pranith/qemu/hw/misc/aspeed_scu.c:130:9: error: implicit
declaration of function ‘qemu_log_mask’ [-Werror=implicit-function-declaration
g. You can only have access to the
public key of the repo to create the encrypted string as above.
--
Pranith
The recent patch enabling lock assertions uncovered the missing lock
acquisition in cpu_exec_step(). This patch adds them.
CC: Richard Henderson
CC: Alex Bennée
Signed-off-by: Pranith Kumar
---
cpu-exec.c | 4
1 file changed, 4 insertions(+)
diff --git a/cpu-exec.c b/cpu-exec.c
index
Hello,
I keep seeing these warnings on the latest master with GCC 9.3:
/home/pranith/qemu/hw/block/pflash_cfi01.c: In function
‘pflash_mem_read_with_attrs’:
/home/pranith/qemu/hw/block/pflash_cfi01.c:667:20: note: parameter passing
for argument of type ‘MemTxAttrs’ {aka ‘struct MemTxAttrs
Hi,
On Fri, Jun 14, 2019 at 10:21 AM Alex Bennée wrote:
>
> This is mostly extracted from Emilio's more verbose commit comments
> with some additional verbiage from me.
>
> Signed-off-by: Alex Bennée
> ---
> docs/devel/index.rst | 1 +
> docs/devel/plugins.rst | 99 ++
Minor nits.
On Fri, Jun 14, 2019 at 11:41 AM Alex Bennée wrote:
>
> From: "Emilio G. Cota"
>
> Signed-off-by: Emilio G. Cota
> ---
> bsd-user/syscall.c | 9 +
> linux-user/syscall.c | 3 +++
> 2 files changed, 12 insertions(+)
>
> diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c
n_vcpu_syscall_ret_cb_t)(qemu_plugin_id_t id, unsigned int
> vcpu_idx,
> + int64_t num, int64_t ret);
> +
> +void
> +qemu_plugin_register_vcpu_syscall_ret_cb(qemu_plugin_id_t id,
> + qemu_plugin_vcpu_syscall_ret_cb_t
> cb);
> +
> +
> +/**
> + * qemu_plugin_vcpu_for_each() - iterate over the existing vCPU
> + * @id: plugin ID
> + * @cb: callback function
> + *
> + * The @cb function is called once for each existing vCPU.
> + *
> + * See also: qemu_plugin_register_vcpu_init_cb()
> + */
> +void qemu_plugin_vcpu_for_each(qemu_plugin_id_t id,
> + qemu_plugin_vcpu_simple_cb_t cb);
> +
> +void qemu_plugin_register_flush_cb(qemu_plugin_id_t id,
> + qemu_plugin_simple_cb_t cb);
> +
> +void qemu_plugin_register_atexit_cb(qemu_plugin_id_t id,
> +qemu_plugin_udata_cb_t cb, void
> *userdata);
> +
> +/* returns -1 in user-mode */
> +int qemu_plugin_n_vcpus(void);
> +
> +/* returns -1 in user-mode */
> +int qemu_plugin_n_max_vcpus(void);
> +
> +#endif /* QEMU_PLUGIN_API_H */
> --
> 2.20.1
>
>
--
Pranith
of the callback
once it got the necessary callbacks.
* State saving API
An API to save the state of the VM from the plugin code.
Let me know your thoughts and any other ideas you might have.
Thanks,
--
Pranith
e region-of-interest (ROI) in benchmarks to
> > generate callbacks.
>
> Well we have that now. At each TB generation event the callback is free to
> register
> as many or few callbacks as it likes dynamically.
But how does the plugin know that the TB being generated is the first
TB in the ROI?
Similarly the plugin needs to know the then end of ROI has been reached.
Also, please note that there can be multiple ROIs. It would be good to
know if we can assign ids to each ROI for the plugin.
Thanks,
--
Pranith
+Raghavendra G who implemented this option in write-behind, to this
upstream patch review discussion
Pranith
On 04/06/2016 06:50 PM, Kevin Wolf wrote:
Am 06.04.2016 um 15:10 hat Jeff Cody geschrieben:
On Wed, Apr 06, 2016 at 01:51:59PM +0200, Kevin Wolf wrote:
Am 06.04.2016 um 13:41 hat
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