On Tue, Sep 5, 2017 at 5:50 PM, Richard Henderson <r...@twiddle.net> wrote: > On 08/29/2017 10:23 AM, Pranith Kumar wrote: >> This patch increases the number of entries cached in the TLB. I went >> over a few architectures to see if increasing it is problematic. Only >> armv6 seems to have a limitation that only 8 bits can be used for >> indexing these entries. For other architectures, the number of TLB >> entries is increased to a 4K-sized cache. The patch also doubles the >> number of victim TLB entries. >> >> Some statistics collected from a build benchmark for various cache >> sizes is listed below: >> >> | TLB bits\vTLB entires | 8 | 16 | 32 | >> | 8 | 952.94(+0.0%) | 929.99(+2.4%) | 919.02(+3.6%) | >> | 10 | 898.92(+5.6%) | 886.13(+7.0%) | 887.03(+6.9%) | >> | 12 | 878.56(+7.8%) | 873.53(+8.3%)* | 875.34(+8.1%) | >> >> The best combination for this workload came out to be 12 bits for the >> TLB and a 16 entry vTLB cache. > > This significantly degrades performance of alpha-softmmu. > It spends about 25% of all cpu time in memset.
What workload does it degrade for? I will try to reproduce and see which memset is causing this. -- Pranith
