One of possible problems could be a block size. In this case I am using
ZFS with raidZ 4+1 drives. Each drive has 4Kb block. So optimal block
size is 16384 bytes. By optimizing block size it possible to improve
performance 10 folds but 9p stably provides 10 folds worse performance
than native write
>>>Can you try with security_model=passthrough?
It provides the same results, see below:
$ dd if=/dev/zero of=test count=10
10+0 records in
10+0 records out
5120 bytes (51 MB) copied, 19.8581 s, 2.6 MB/s
$ dd if=/dev/zero of=test count=10 bs=16384
10+0 records in
10+
Hi Mohan,
this parameter provide significant improvement in big file access/write:
VirtFS on /srv/shared type 9p (rw,trans=virtio,version=9p2000.L,msize=262144)
$ dd if=/dev/zero of=test count=10 bs=
Public bug reported:
Hi,
Internet performance for Host to Quest is low.
The speed Guest to same Guest is 11.3 Gbits/sec
The speed Host to same Host is similar (9.8-11 Gbits/sec)
But the speed from Guest to Host is slow and around 1Gbit/sec.
In the reality traffic never leave a Host. I expect
I will try to test the PoC on real e100.
But this work may need some more time.
发自我的 iPhone
> 在 2015年10月20日，上午11:04，Jason Wang 写道：
>
>
>
>> On 10/17/2015 07:35 PM, Peter Maydell wrote:
>>> On 16 October 2015 at 22:37, Stefan Weil wrote:
>>> Maybe real hardware will run an endless loop?
>>>
Public bug reported:
When you tell qemu to shutdown using the "quit" monitor command, the
downscript of the tap interface is not executed.
To reproduce:
Create the test script /tmp/qemu-ifdown-test.sh :
==
#!/bin/bash
touch /tmp/is_this_working
==
Run:
==
# chmod +x /tmp/qemu-ifdown-test.s
>From f972dab518c6581a83f397c35b3d09b2ef6de674 Mon Sep 17 00:00:00 2001
From: max
Date: Sun, 22 Aug 2021 14:02:48 +0300
Subject: [PATCH] virtio-vga, stubs: Fix qemu failing on virio-vga with blobs on
when qemu compiled with modules enabled
Resolves: https://gitlab.com/qemu-project/qemu/-/iss
t -cpu fsf. I can post a patch to
make fsf the default CPU type in big-endian case.
--
Thanks.
-- Max
This makes usable default for -cpu option both for qemu-system-xtensa
and qemu-system-xtensaeb fixing the following error:
$ qemu-system-xtensaeb -M sim
Unable to find CPU definition
Signed-off-by: Max Filippov
---
hw/xtensa_lx60.c|6 +++---
hw/xtensa_sim.c |4
This fixes the following error:
$ qemu-system-xtensa -cpu help
Segmentation fault
Signed-off-by: Max Filippov
---
hw/xtensa_sim.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index ed38bd4..831460b 100644
--- a/hw
On Thu, Aug 9, 2012 at 11:43 AM, Markus Armbruster wrote:
> Max Filippov writes:
>
>> This fixes the following error:
>>
>> $ qemu-system-xtensa -cpu help
>> Segmentation fault
>
> main() attempts to cope with "no machine found", it just
On Thu, Aug 9, 2012 at 5:31 PM, Markus Armbruster wrote:
> Cc: Max Filippov
>
> Suppress default floppy, CD-ROM and SD card drives for machines lx60,
> lx200, sim.
>
> Signed-off-by: Markus Armbruster
Acked-by: Max Filippov
Though I'd agree with Andreas about i
ample, the tb has an instruction of mov 0x4(%ebx) %eax.
> To calculate the address of 0x4(%ebx), I need to know the value of %ebx.
> Is this correct? Thanks.
Why don't you just instrument actual memory access functions in
softmmu_template.h ?
--
Thanks.
-- Max
On Thu, Aug 16, 2012 at 9:29 PM, Steven wrote:
> On Thu, Aug 16, 2012 at 1:00 PM, Max Filippov wrote:
>> On Thu, Aug 16, 2012 at 8:36 PM, Steven wrote:
>>> On Thu, Aug 16, 2012 at 4:02 AM, 陳韋任 (Wei-Ren Chen)
>>> wrote:
>>>>> I would like to is ther
On Thu, Aug 16, 2012 at 9:37 PM, Max Filippov wrote:
> On Thu, Aug 16, 2012 at 9:29 PM, Steven wrote:
>> On Thu, Aug 16, 2012 at 1:00 PM, Max Filippov wrote:
>>> On Thu, Aug 16, 2012 at 8:36 PM, Steven wrote:
>>>> On Thu, Aug 16, 2012 at 4:02 AM, 陳韋任 (Wei-Ren Che
On Thu, Aug 16, 2012 at 9:49 PM, Steven wrote:
> On Thu, Aug 16, 2012 at 1:43 PM, Max Filippov wrote:
>> On Thu, Aug 16, 2012 at 9:37 PM, Max Filippov wrote:
>>> On Thu, Aug 16, 2012 at 9:29 PM, Steven wrote:
>>>> On Thu, Aug 16, 2012 at 1:00 PM, Max Filippov wro
On Thu, Aug 16, 2012 at 10:31 PM, Max Filippov wrote:
> On Thu, Aug 16, 2012 at 9:49 PM, Steven wrote:
>> On Thu, Aug 16, 2012 at 1:43 PM, Max Filippov wrote:
>>> On Thu, Aug 16, 2012 at 9:37 PM, Max Filippov wrote:
>>>> On Thu, Aug 16, 2012 at 9:29 PM, Steve
On Fri, Aug 17, 2012 at 9:38 AM, Steven wrote:
> Hi, Max,
> I appreciate your help and got some results using your patch. But I
> still have two questions as blow.
>
>>> I see that with the following patch
>>>
>>> diff --git a/softmmu_template.h b/softmm
7;ll have to generate code. Look at how helpers work.
>> Hi, Laurent,
>> do you mean the target-i386/op_helper.c/helper.c or the tcg helper? Thanks.
>
> What do you mean by "resolve the memory access address"? Do you want
> to get guest virtual address for each gue
On Tue, Aug 21, 2012 at 9:40 AM, Steven wrote:
> Hi, Max,
> I wrote a small program to verify your patch could catch all the load
> instructions from the guest. However, I found some problem from the
> results.
>
> The guest OS and the emulated machine are both 32bit x86. My s
> MMIO. Using cpu_get_phys_page_debug() may help.
>
Maybe you just need to avoid accessing unsuitable physical addresses?
Or maybe 'if (env->cr[0] & CR0_PG_MASK)' is not strong enough, may
(CR0_PG_MASK | CR0_PE_MASK) be better?
At what stage does it hang? What CR3 value changes are observed before
the hang?
--
Thanks.
-- Max
This prevents guest from proceeding with uninitialised garbage returned
from unimplemented simcalls.
Signed-off-by: Max Filippov
---
target-xtensa/xtensa-semi.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
On Wed, Aug 22, 2012 at 9:15 PM, Max Filippov wrote:
> This prevents guest from proceeding with uninitialised garbage returned
> from unimplemented simcalls.
Oops, looks like ENOSYS is the right errno for that.
--
Thanks.
-- Max
This prevents guest from proceeding with uninitialised garbage returned
from unimplemented simcalls.
Signed-off-by: Max Filippov
---
target-xtensa/xtensa-semi.c |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/xtensa-semi.c b/target-xtensa/xtensa-semi.c
ig (type=2, func=0x556264b0
) at qemu/vl.c:2048
#6 0x555973f5 in main (argc=, argv=,
envp=) at qemu/vl.c:3588
The command line is the following:
qemu-system-xtensa -M sim -cpu dc232b -nographic -semihosting -kernel
./test_b.tst
> QLIST_INSERT_HEAD(&mon_list, mon, entry);
> if (!default_mon || (flags & MONITOR_IS_DEFAULT))
> default_mon = mon;
> --
> 1.7.5.4
>
>
--
Thanks.
-- Max
On Fri, Aug 24, 2012 at 2:06 AM, Max Filippov wrote:
> On Thu, Aug 23, 2012 at 5:22 PM, Anthony Liguori wrote:
>> At some point in the past, the OPEN event was changed to be issued from a
>> bottom half. This creates a small window whereas a data callback registered
>&
On Sat, Aug 25, 2012 at 9:20 PM, Steven wrote:
> On Tue, Aug 21, 2012 at 3:18 AM, Max Filippov wrote:
>> On Tue, Aug 21, 2012 at 9:40 AM, Steven wrote:
>>> Hi, Max,
>>> I wrote a small program to verify your patch could catch all the load
>>> instructions f
al is to obtain the memory access trace for a particular
> process in the guest, so your patch really helps, except for too many
> kernel _mmu events.
Wouldn't it be easier to use qemu-user for that?
--
Thanks.
-- Max
counter into a global variable.
--
Thanks.
-- Max
According to ISA, 3.5.4, third opcode byte should not be fetched for
2-byte instructions.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
index c81450d
performed in the tlb_set_page,
but it is not called in case of guest TLB miss. Any idea on how to resolve it
is welcome.
Max Filippov (9):
target-xtensa: add DEBUGCAUSE SR and configuration
target-xtensa: implement instruction breakpoints
target-xtensa: add ICOUNT SR and debug exception
exec
Signed-off-by: Max Filippov
---
exec.c | 12 +---
1 files changed, 9 insertions(+), 3 deletions(-)
diff --git a/exec.c b/exec.c
index 5b9eb9a..0e93e0e 100644
--- a/exec.c
+++ b/exec.c
@@ -3279,9 +3279,15 @@ static void watch_mem_write(void *opaque,
target_phys_addr_t addr
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/test_break.S | 223 +
2 files changed, 224 insertions(+), 0 deletions(-)
create mode 100644 tests/tcg/xtensa/test_break.S
diff --git a/tests/tcg/xtensa/Makefile b
.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |6 +
target-xtensa/translate.c | 49 -
2 files changed, 54 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h
index 2875197..fbe5d15 100644
--- a/target
DEBUGCAUSE SR holds information about the most recent debug exception.
See ISA, 4.7.7 for more details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 15 +++
target-xtensa/translate.c |6 ++
2 files changed, 21 insertions(+), 0 deletions(-)
diff --git a
Make cpu_watchpoint_insert accept watchpoints of any power-of-two size
up to the target page size.
Signed-off-by: Max Filippov
---
exec.c |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/exec.c b/exec.c
index bc6c185..39a5497 100644
--- a/exec.c
+++ b/exec.c
@@ -1443,7
Fill debug configuration from overlay definitions in the DEBUG_SECTION.
Add DEBUG_SECTION to DC232B and FSF cores.
Signed-off-by: Max Filippov
---
target-xtensa/core-dc232b.c |1 +
target-xtensa/core-fsf.c |1 +
target-xtensa/overlay_tool.h |5 +
3 files changed, 7
for more details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h | 12
target-xtensa/helper.c| 41 +
target-xtensa/helpers.h |2 +
target-xtensa/op_helper.c | 62 +
target-xtensa
Add IBREAKA/IBREAKENABLE SRs and implement debug exception, BREAK and
BREAK.N instructions and IBREAK breakpoints.
IBREAK breakpoint address is considered constant for TB lifetime.
On IBREAKA/IBREAKENABLE change corresponding TBs are invalidated.
Signed-off-by: Max Filippov
---
target-xtensa
In case of BP_STOP_BEFORE_ACCESS watchpoint check_watchpoint intends to
signal EXCP_DEBUG exception on exit from cpu loop, but later overwrites
exception code by the cpu_resume_from_signal call.
Use cpu_loop_exit with BP_STOP_BEFORE_ACCESS watchpoints.
Signed-off-by: Max Filippov
---
exec.c
> Remove some include statements which are not needed.
>
> Cc: Max Filippov
> Signed-off-by: Stefan Weil
Acked-by: Max Filippov
Thanks.
-- Max
it the breakpoint in the desired process context.
--
Thanks.
-- Max
On Wed, Oct 10, 2012 at 7:15 PM, Andreas Färber wrote:
> Am 23.05.2012 05:08, schrieb Andreas Färber:
>> Needed for cpu_has_work().
>>
>> Signed-off-by: Andreas Färber
>
> Max, could you ack this trivial patch please? It still applies.
Well, it does but why do
On Wed, Oct 10, 2012 at 8:33 PM, Andreas Färber wrote:
> Am 10.10.2012 17:35, schrieb Max Filippov:
>> On Wed, Oct 10, 2012 at 7:15 PM, Andreas Färber wrote:
>>> Am 23.05.2012 05:08, schrieb Andreas Färber:
>>>> Needed for cpu_has_work().
>>>>
>&
Don't explode QEMUMachineInitArgs before passing it to lx_init.
Signed-off-by: Max Filippov
---
hw/xtensa_lx60.c | 25 ++---
1 files changed, 6 insertions(+), 19 deletions(-)
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 5dd2e08..b4d3b8e 100644
---
Max Filippov (2):
hw/xtensa_lx60: don't prematurely explode QEMUMachineInitArgs
hw/xtensa_sim: get rid of intermediate xtensa_sim_init
hw/xtensa_lx60.c | 25 ++---
hw/xtensa_sim.c | 27 ---
2 files changed, 14 insertions(+), 38 dele
Remove xtensa_sim_init that only explodes machine init args, rename
sim_init to xtensa_sim_init.
Signed-off-by: Max Filippov
---
hw/xtensa_sim.c | 27 ---
1 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index 2e846d8
On Thu, Oct 25, 2012 at 2:04 PM, Peter Maydell wrote:
> On 25 October 2012 09:47, Max Filippov wrote:
>> @@ -272,37 +273,23 @@ static void lx_init(const LxBoardDesc *board,
>> static void xtensa_lx60_init(QEMUMachineInitArgs *args)
>> {
>> ram_addr_
Remove xtensa_sim_init that only explodes machine init args, rename
sim_init to xtensa_sim_init.
Signed-off-by: Max Filippov
---
hw/xtensa_sim.c | 27 ---
1 files changed, 8 insertions(+), 19 deletions(-)
diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c
index 2e846d8
Don't explode QEMUMachineInitArgs before passing it to lx_init.
Signed-off-by: Max Filippov
---
hw/xtensa_lx60.c | 30 +++---
1 files changed, 7 insertions(+), 23 deletions(-)
diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c
index 5dd2e08..4c42edc 100644
---
Changes v1 -> v2:
- remove ram_size in xtensa_lx60 as well
Max Filippov (2):
hw/xtensa_lx60: don't prematurely explode QEMUMachineInitArgs
hw/xtensa_sim: get rid of intermediate xtensa_sim_init
hw/xtensa_lx60.c | 30 +++---
hw/xtensa_sim.c
On Sun, Oct 28, 2012 at 7:03 PM, Blue Swirl wrote:
> Pass around CPUState instead of using global cpu_single_env.
>
> Signed-off-by: Blue Swirl
> ---
> target-xtensa/translate.c | 10 +-
> 1 files changed, 5 insertions(+), 5 deletions(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
: expected ‘TCGv_i64’ but argument is of type
‘TCGv_i32’
...
--
Thanks.
-- Max
rnet device.
We have a model for it (: You can look at lx60_net_init() in the
hw/xtensa_lx60.c
to see how it may be connected.
--
Thanks.
-- Max
On Wed, Jun 20, 2012 at 1:42 PM, Jia Liu wrote:
> Hi Max,
>
> On Wed, Jun 20, 2012 at 2:29 PM, Max Filippov wrote:
>> On 06/18/2012 05:02 AM, Jia Liu wrote:
>>> Add a dummy board for IIS.
>>>
>>> Signed-off-by: Jia Liu
>&
On Wed, Jun 20, 2012 at 8:41 PM, Jia Liu wrote:
> Hi Max,
>
> On Wed, Jun 20, 2012 at 8:57 PM, Max Filippov wrote:
>> On Wed, Jun 20, 2012 at 1:42 PM, Jia Liu wrote:
>>> Hi Max,
>>>
>>> On Wed, Jun 20, 2012 at 2:29 PM, Max Filippov wrote:
>>>&
Signed-off-by: Max Filippov
---
default-configs/or32-softmmu.mak |2 +-
hw/openrisc_sim.c| 24 +++-
2 files changed, 24 insertions(+), 2 deletions(-)
diff --git a/default-configs/or32-softmmu.mak b/default-configs/or32-softmmu.mak
index 7590eed..d85b82b
On Thu, Jun 21, 2012 at 12:19 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> + * OpenRISC simulator for use as an ISS.
> ^^^
> Shoudld be IIS?
I guess it stands for Instruction Set Simulator, so rather the subject
should be changed.
--
Thanks.
-- Max
ond.
> + TCGv sr_f = tcg_temp_new();
> + tcg_gen_andi_tl(sr_f, cpu_sr, SR_F);
> + tcg_gen_mov_tl(res, cpu_R[rb]);
> + tcg_gen_brcondi_tl(TCG_COND_NE, sr_f, SR_F, lab);
> + tcg_gen_mov_tl(res, cpu_R[ra]);
> + gen_set_label(lab);
> + tcg_gen_mov_tl(cpu_R[rd], res);
> + tcg_temp_free(sr_f);
> + tcg_temp_free(res);
> + }
> + break;
[...]
--
Thanks.
-- Max
On Mon, Jun 25, 2012 at 6:50 AM, Jia Liu wrote:
> Hi Max,
>
> On Thu, Jun 21, 2012 at 6:24 PM, Max Filippov wrote:
>> On Thu, Jun 21, 2012 at 6:58 AM, Jia Liu wrote:
>>> Add OpenRISC instruction tanslation routines.
>>>
>>> Signed-off-by: Ji
arget-xtensa/helper.c | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
Acked-by: Max Filippov
--
Thanks.
-- Max
On Tue, Jun 26, 2012 at 5:37 AM, Jia Liu wrote:
> Hi Max,
>
> On Mon, Jun 25, 2012 at 5:00 PM, Max Filippov wrote:
>> On Mon, Jun 25, 2012 at 6:50 AM, Jia Liu wrote:
>>> Hi Max,
>>>
>>> On Thu, Jun 21, 2012 at 6:24 PM, Max Filippov wrote:
>>&g
On Tue, Jun 26, 2012 at 1:14 PM, 陳韋任 (Wei-Ren Chen)
wrote:
>> > 0x is -1, 0x80000000 is -MAX.
>> > -1/-MAX ?will raise a exception, and I've handle this.
-1 / -MAX equals 0, it's not the issue here.
>> > -MAX/-1 ?will get a MAX, for max value of
CY));
> + tcg_gen_andi_tl(sr_ove, cpu_sr, SR_OVE);
> + tcg_gen_brcondi_tl(TCG_COND_EQ, sr_ove, SR_OVE, lab2);
Same here.
> + gen_exception(dc, EXCP_RANGE);
> + gen_set_label(lab1);
> + tcg_gen_divu_tl(cpu_R[rd], cpu_R[ra], cpu_R[rb]);
> + gen_set_label(lab2);
> + }
> + tcg_temp_free_i32(sr_ove);
> + }
> + break;
--
Thanks.
-- Max
On Wed, Jun 27, 2012 at 4:40 PM, Jia Liu wrote:
> Hi Max,
>
> On Wed, Jun 27, 2012 at 7:03 PM, Max Filippov wrote:
>> On Wed, Jun 27, 2012 at 1:54 PM, Jia Liu wrote:
>>> Add OpenRISC instruction tanslation routines.
>>>
>>> Signed-off-by: Ji
; num_pages |= num_pages >> 4;
> num_pages |= num_pages >> 8;
> num_pages |= num_pages >> 16;
> num_pages |= num_pages >> 32;
> num_pages -= num_pages / 2;
> }
Or
if (!is_power_of_2(num_pages)) {
num_pages = 0x8000ULL >> clz64(num_pages);
}
[...]
--
Thanks.
-- Max
tcg_gen_andi_tl(cpu_A0, cpu_A0, 0x);
> #endif
> + tcg_gen_add_tl(cpu_A0, cpu_A0, cpu_tmp0);
> }
>
> #ifdef TARGET_X86_64
> --
> 1.7.4.1
>
>
--
Thanks.
-- Max
base + (uint32_t)(ebx * 4 + 0x260)
>
> Signed-off-by: Vitaly Chipounov
Reviewed-by: Max Filippov
--
Thanks.
-- Max
On Sun, Nov 18, 2012 at 12:52 AM, Max Filippov wrote:
> cpu_get_phys_page_debug is not in sync with cpu_x86_handle_mmu_fault:
> the latter first checks CR0_PG_MASK and only after CR4_PAE_MASK.
>
> This fixes odd gdb code display with PAE enabled.
>
> Signed-off-by: Max Filippo
opcodes more efficiently.
Please review/apply.
Max Filippov (8):
target-xtensa: implement ATOMCTL SR
target-xtensa: implement CACHEATTR SR
target-xtensa: restrict available SRs by enabled options
target-xtensa: better control rsr/wsr/xsr access to SRs
target-xtensa: implement MISC SR
Use movcond for all sorts of conditional moves, ABS, CLAMPS, MIN/MAX
opcodes.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 92
1 files changed, 42 insertions(+), 50 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/test_s32c1i.S | 39 +++
2 files changed, 40 insertions(+), 0 deletions(-)
create mode 100644 tests/tcg/xtensa/test_s32c1i.S
diff --git a/tests/tcg/xtensa/Makefile b
In XEA1, the Options for Memory Protection and Translation and the
corresponding TLB management instructions are not available. Instead,
functionality similar to the Region Protection Option is available
through the cache attribute register. See ISA, A.2.14 for details.
Signed-off-by: Max
There are read-only (DEBUGCAUSE, PRID) and write-only (INTCLEAR) SRs,
and INTERRUPT/INTSET SR allows rsr/wsr, but not xsr. Raise illeagal
opcode exception on illegal access to these SRs.
Signed-off-by: Max Filippov
---
target-xtensa/translate.c | 49
registers are undefined after reset.
See ISA, 4.7.3 for details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa/overlay_tool.h |1 +
target-xtensa/translate.c|4
3 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/target-xtensa/cpu.h b
ATOMCTL SR controls s32c1i opcode behavior depending on targeted memory
type. See ISA, 4.3.12.4 for details.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.c |2 +
target-xtensa/cpu.h | 10 +++
target-xtensa/helper.c | 56
Signed-off-by: Max Filippov
---
tests/tcg/xtensa/Makefile |1 +
tests/tcg/xtensa/macros.inc |2 +-
tests/tcg/xtensa/test_sr.S | 90 +++
3 files changed, 92 insertions(+), 1 deletions(-)
create mode 100644 tests/tcg/xtensa/test_sr.S
diff
Beginning with the RA-2004.1 release, SR access instructions (rsr, wsr,
xsr) are associated with their corresponding SR and raise illegal opcode
exception in case the register is not configured for the core.
Signed-off-by: Max Filippov
---
target-xtensa/cpu.h |1 +
target-xtensa
On Wed, Dec 5, 2012 at 3:15 PM, Andreas Färber wrote:
> Am 17.11.2012 21:52, schrieb Max Filippov:
>> cpu_get_phys_page_debug is not in sync with cpu_x86_handle_mmu_fault:
>> the latter first checks CR0_PG_MASK and only after CR4_PAE_MASK.
>>
>> This fixes odd gdb co
ss occured), not from the point where DTLB miss occured, which is
wrong.
With that fix the above scenario causes ITLB miss exception (that used
to be step 7) at step 3, right at the beginning of the TB.
Signed-off-by: Max Filippov
Cc: qemu-sta...@nongnu.org
---
target-xtensa/helper.c |3 ++
Zero out tcg_ctx.gen_opc_instr_start for instructions representing the
last guest opcode in the TB.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
target-xtensa/translate.c |8 +++-
1 files changed, 7 insertions(+), 1 deletions(-)
diff --git a/target-xtensa/translate.c b
On Wed, Dec 19, 2012 at 11:45 PM, Blue Swirl wrote:
> On Tue, Dec 18, 2012 at 7:21 AM, Max Filippov wrote:
>> Zero out tcg_ctx.gen_opc_instr_start for instructions representing the
>> last guest opcode in the TB.
>>
>> Cc: qemu-sta...@nongnu.org
>> Signed-off-by
Zero out tcg_ctx.gen_opc_instr_start for instructions representing the
last guest opcode in the TB.
Cc: qemu-sta...@nongnu.org
Signed-off-by: Max Filippov
---
Changes v1 -> v2:
- replace while loop with memset
target-xtensa/translate.c |6 +-
1 files changed, 5 insertions(+)
he standard '0/0 cover letter + each patch mail
> as a followup to the cover letter' format, please? git
There's also a lot of coding standard violations, can you run
your patches through scripts/checkpatch.pl and fix its findings?
--
Thanks.
-- Max
Hello.
Do I understand it right that there's no dedicated mechanism
other than icount that would switch current CPU in emulated
SMP system and that in the absence of icount such scheduling
is a side effect of interrupt delivery to the current CPU?
--
Thanks.
-- Max
On Thu, Sep 20, 2012 at 1:59 AM, Richard Henderson wrote:
> On 09/18/2012 05:23 PM, Max Filippov wrote:
>> +uint32_t HELPER(ftoi)(float32 v, uint32_t rounding_mode, uint32_t scale)
>> +{
>> +float_status fp_status = {0};
>> +
>> +set_float_roundi
his code is generated when TB ends on LEND
(zero-overhead loop ending) with branching instruction.
So, in addition to 3 way branch there's extra looping code
generated by unconditional gen_check_loop_end(dc, 0);
at the end of disas_xtensa_insn. I was pretty sure that this
dead code would mak
On Thu, Sep 20, 2012 at 6:03 PM, Richard Henderson wrote:
> On 09/19/2012 05:29 PM, Max Filippov wrote:
>> Not all tcg backends can handle that.
>
> *No* tcg backends can handle that.
>
> If we fix the bug wherein i386 clobbers the goto_tb target
> during re-translation yo
Max Filippov (2):
target-xtensa: fix extui shift amount
target-xtensa: don't emit extra tcg_gen_goto_tb
target-xtensa/translate.c | 28
1 files changed, 24 insertions(+), 4 deletions(-)
--
1.7.7.6
extui opcode only uses lowermost op1 bit for sa4.
Reported-by: malc
Signed-off-by: Max Filippov
Cc: qemu-stable
---
target-xtensa/translate.c | 24 +---
1 files changed, 21 insertions(+), 3 deletions(-)
diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c
Unconditional gen_check_loop_end at the end of disas_xtensa_insn
can emit tcg_gen_goto_tb with slot id already used in the TB (e.g. when
TB ends at LEND with a branch).
Signed-off-by: Max Filippov
Cc: qemu-stable
---
target-xtensa/translate.c |4 +++-
1 files changed, 3 insertions(+), 1
Does this look sane or should it better be merged with e.g. tcg_dump_ops?
Max Filippov (2):
tcg/README: document tcg_gen_goto_tb restrictions
tcg: add TB sanity checking
tcg/README |3 +-
tcg/tcg.c | 69
2 files changed, 71
Do a sanity checking pass on the intermediate code.
Check that goto_tb indices are either 0 or 1 and used at most once per
TB.
Signed-off-by: Max Filippov
---
tcg/tcg.c | 69 +
1 files changed, 69 insertions(+), 0 deletions(-)
diff
See
http://lists.nongnu.org/archive/html/qemu-devel/2012-09/msg03196.html
for the whole story.
Signed-off-by: Max Filippov
---
tcg/README |3 ++-
1 files changed, 2 insertions(+), 1 deletions(-)
diff --git a/tcg/README b/tcg/README
index cfdfd96..86b43f1 100644
--- a/tcg/README
+++ b/tcg
On 09/22/2012 04:18 AM, Richard Henderson wrote:
> Checking that we don't try for idx != [01] is trivial. Checking
> that we don't issue more than one of any index requires a tad
> more data and some ifdefs protecting that new variable.
>
> Signed-off-by: Richard Hend
On Wed, Sep 26, 2012 at 2:57 AM, Aurelien Jarno wrote:
> Now that and with 0xff, 0x and 0x is optimized in
> tcg/tcg-op.h, there is no need to do it in target-xtensa/translate.c.
>
> Cc: Max Filippov
> Signed-off-by: Aurelien Jarno
> ---
> target-xten
On Mon, Oct 1, 2012 at 10:54 PM, Aurelien Jarno wrote:
> Now that "and" with 0xff, 0x and 0x and "shr" with 0 shift
> are optimized in tcg/tcg-op.h there is no need to do it in
> target-xtensa/translate.c.
>
> Cc: Max Filippov
> Signed-off-by:
nly once, with
> target_phys_addr_t unconditionally typedefed to uint64_t.
>
> Signed-off-by: Avi Kivity
> ---
>
> v2: no changes, but copied the maintainers of architectures that will
> see their target_phys_addr_t changed as a result. Please view and/or
> test.
Xtensa on x86_64 host: OK.
--
Thanks.
-- Max
kernel_cmdline = kernel_cmdline,
> + initrd_filename = initrd_filename,
Missing dot?
> + .cpu_model = cpu_model };
> +machine->init(&args);
>
> cpu_synchronize_all_post_init();
--
Thanks.
-- Max
On Wed, Aug 22, 2012 at 10:03 PM, Max Filippov wrote:
> This prevents guest from proceeding with uninitialised garbage returned
> from unimplemented simcalls.
>
> Signed-off-by: Max Filippov
> ---
> target-xtensa/xtensa-semi.c |2 ++
> 1 files changed, 2 insertions(+),
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