Hi. This is my current patch queue for xtensa: - add support for a number of Special Registers: ATOMCTL, CACHEATTR, MISC; - raise exceptions on access to unconfigured SRs/invalid access to configured SRs; - add unit tests for SR access and for s32c1i opcode; - use movcond to re-implement some opcodes more efficiently.
Please review/apply. Max Filippov (8): target-xtensa: implement ATOMCTL SR target-xtensa: implement CACHEATTR SR target-xtensa: restrict available SRs by enabled options target-xtensa: better control rsr/wsr/xsr access to SRs target-xtensa: implement MISC SR target-xtensa: add SR accessibility unit tests target-xtensa: add s32c1i unit tests target-xtensa: use movcond where possible target-xtensa/cpu.c | 3 + target-xtensa/cpu.h | 14 ++ target-xtensa/helper.c | 75 +++++++-- target-xtensa/helper.h | 1 + target-xtensa/op_helper.c | 57 ++++++ target-xtensa/overlay_tool.h | 12 ++- target-xtensa/translate.c | 367 ++++++++++++++++++++++------------------ tests/tcg/xtensa/Makefile | 2 + tests/tcg/xtensa/macros.inc | 2 +- tests/tcg/xtensa/test_s32c1i.S | 39 +++++ tests/tcg/xtensa/test_sr.S | 90 ++++++++++ 11 files changed, 484 insertions(+), 178 deletions(-) create mode 100644 tests/tcg/xtensa/test_s32c1i.S create mode 100644 tests/tcg/xtensa/test_sr.S -- 1.7.7.6
