RE: [PATCH 2/9] Hexagon (target/hexagon) Mark new_read_idx in trans functions

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Tuesday, February 27, 2024 8:20 AM > To: Taylor Simpson > Cc: qemu-devel@nongnu.org; bc...@quicinc.com; > quic_mathb...@quicinc.com; sidn...@quicinc.com; > quic_mlie...@quicinc.com; richard.hender...@linaro.org; > phi...@l

RE: [PATCH 4/9] Hexagon (target/hexagon) Mark has_pred_dest in trans functions

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Tuesday, February 27, 2024 8:21 AM > To: Taylor Simpson > Cc: qemu-devel@nongnu.org; bc...@quicinc.com; > quic_mathb...@quicinc.com; sidn...@quicinc.com; > quic_mlie...@quicinc.com; richard.hender...@linaro.org; > phi...@l

RE: [PATCH] Hexagon: add PC alignment check and exception

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Friday, April 26, 2024 1:16 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; sidn...@quicinc.com; a...@rev.ng; a...@rev.ng; > ltaylorsimp...@gmail.com > Subject: [PATCH] Hexagon: add PC alignment check and exception

RE: [PATCH] Hexagon: add PC alignment check and exception

PS You should also update the pkt_raises_exception function in translate.c to return true for packets that contain these instructions. This will ensure that none of the machine state is changed before the check is complete. Taylor > -Original Message- > From: ltaylorsimp...@gmail.com

RE: [PATCH v3] Hexagon: add PC alignment check and exception

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Tuesday, April 30, 2024 9:25 AM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; sidn...@quicinc.com; a...@rev.ng; a...@rev.ng; > ltaylorsimp...@gmail.com; richard.hender...@linaro.org; Laurent Vivier > > Subject: [PAT

RE: [PATCH v4] Hexagon: add PC alignment check and exception

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, May 2, 2024 9:55 AM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; sidn...@quicinc.com; a...@rev.ng; a...@rev.ng; > ltaylorsimp...@gmail.com; richard.hender...@linaro.org; Laurent Vivier > > Subject: [PATCH

RE: [PATCH 1/4] target/hexagon: idef-parser remove unused defines

> -Original Message- > From: Anton Johansson > Sent: Monday, May 6, 2024 1:31 PM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH 1/4] target/hexagon: idef-parser remove unused defines > > Before switching to GArray/g_string_p

RE: [PATCH 4/4] target/hexagon: idef-parser simplify predicate init

> -Original Message- > From: Anton Johansson > Sent: Monday, May 6, 2024 1:31 PM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH 4/4] target/hexagon: idef-parser simplify predicate init > > Only predicate instruction argument

RE: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

> -Original Message- > From: Anton Johansson > Sent: Monday, May 6, 2024 1:31 PM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list > > gen_inst_init_args() is called for in

RE: [PATCH 2/4] target/hexagon: idef-parser remove undefined functions

> -Original Message- > From: Anton Johansson > Sent: Monday, May 6, 2024 1:31 PM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH 2/4] target/hexagon: idef-parser remove undefined > functions > > Signed-off-by: Anton Johansson

RE: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list

> -Original Message- > From: 'Anton Johansson' > Sent: Tuesday, May 7, 2024 4:47 AM > To: ltaylorsimp...@gmail.com > Cc: qemu-devel@nongnu.org; a...@rev.ng; bc...@quicinc.com > Subject: Re: [PATCH 3/4] target/hexagon: idef-parser fix leak of init_list > > On 06/05/24, ltaylorsimp...@gm

RE: [PATCH 1/3] target/hexagon: Rename HEX_EXCP_ => HEX_EVENT_

> -Original Message- > From: Brian Cain > Sent: Friday, August 16, 2024 1:06 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com; Laurent Vivier > Subject: [PATCH 1/3] target/hexa

RE: [PATCH 2/3] target/hexagon: rename HEX_EVENT_TRAP0=>HEX_CAUSE_TRAP0

> -Original Message- > From: Brian Cain > Sent: Friday, August 16, 2024 1:06 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com > Subject: [PATCH 2/3] target/hexagon: rename > HEX

RE: [PATCH 3/3] target/hexagon: add enums for event, cause

> -Original Message- > From: Brian Cain > Sent: Friday, August 16, 2024 1:06 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com > Subject: [PATCH 3/3] target/hexagon: add enums fo

RE: [PATCH v2 1/3] Hexagon (target/hexagon) Use QEMU decodetree (32-bit instructions)

> -Original Message- > From: Brian Cain > Sent: Sunday, January 14, 2024 5:21 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: Matheus Bernardino (QUIC) ; Sid > Manning ; Marco Liebel (QUIC) > ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng > Subject:

RE: [PATCH] Hexagon: fix HVX store new

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Monday, May 20, 2024 10:53 AM > To: qemu-devel@nongnu.org > Cc: ltaylorsimp...@gmail.com; sidn...@quicinc.com; bc...@quicinc.com; > richard.hender...@linaro.org; a...@rev.ng; a...@rev.ng > Subject: [PATCH] Hexagon: fix HVX

RE: [PATCH v2 4/4] target/hexagon: idef-parser simplify predicate init

> -Original Message- > From: Anton Johansson > Sent: Friday, May 10, 2024 9:53 AM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH v2 4/4] target/hexagon: idef-parser simplify predicate init > > Only predicate instruction argu

RE: [PATCH v2 3/4] target/hexagon: idef-parser fix leak of init_list

> -Original Message- > From: Anton Johansson > Sent: Friday, May 10, 2024 9:53 AM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; ltaylorsimp...@gmail.com; bc...@quicinc.com > Subject: [PATCH v2 3/4] target/hexagon: idef-parser fix leak of init_list > > gen_inst_init_args() is called fo

RE: [PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Wednesday, June 12, 2024 12:30 PM > To: ltaylorsimp...@gmail.com > Cc: qemu-devel@nongnu.org; bc...@quicinc.com; tedw...@quicinc.com; > alex.ben...@linaro.org; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@

RE: [PATCH] Hexagon: lldb read/write predicate registers p0/p1/p2/p3

> -Original Message- > From: Ted Woodward > Sent: Thursday, June 13, 2024 9:03 AM > To: ltaylorsimp...@gmail.com; Matheus Bernardino (QUIC) > > Cc: qemu-devel@nongnu.org; Brian Cain ; > alex.ben...@linaro.org; Sid Manning ; Marco > Liebel (QUIC) ; richard.hender...@linaro.org; > phi...

RE: [PATCH v2 1/2] target/hexagon: rename HEX_EXCP_*=>HEX_CAUSE_*

> -Original Message- > From: Brian Cain > Sent: Monday, August 26, 2024 6:27 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com; Laurent Vivier > Subject: [PATCH v2 1/2] target/h

RE: [PATCH v2 2/2] target/hexagon: add enums for event, cause

> -Original Message- > From: Brian Cain > Sent: Monday, August 26, 2024 6:27 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com > Subject: [PATCH v2 2/2] target/hexagon: add enums

RE: [PATCH v2 2/3] target/hexagon: fix some occurrences of -Wshadow=local

> -Original Message- > From: Brian Cain > Sent: Thursday, October 5, 2023 4:22 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; arm...@redhat.com; richard.hender...@linaro.org; > phi...@linaro.org; peter.mayd...@linaro.org; quic_mathb...@quicinc.com; > stefa...@redhat.com; a...@r

RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals

> -Original Message- > From: Brian Cain > Sent: Thursday, October 5, 2023 4:22 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; arm...@redhat.com; richard.hender...@linaro.org; > phi...@linaro.org; peter.mayd...@linaro.org; quic_mathb...@quicinc.com; > stefa...@redhat.com; a...@r

RE: [PATCH v2 3/3] target/hexagon: avoid shadowing globals

> -Original Message- > From: Brian Cain > Sent: Sunday, October 8, 2023 7:50 AM > To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org > Cc: arm...@redhat.com; richard.hender...@linaro.org; phi...@linaro.org; > peter.mayd...@linaro.org; Matheus Bernardino (QUIC) > ; stefa...@redhat.com;

RE: [PATCH v2] Hexagon: move GETPC() calls to top level helpers

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Wednesday, July 5, 2023 12:35 PM > To: qemu-devel@nongnu.org > Cc: quic_mathb...@quicinc.com; bc...@quicinc.com; > ltaylorsimp...@gmail.com; quic_mlie...@quicinc.com; > richard.hender...@linaro.org > Subject: [PATCH v2] Hex

RE: [PATCH v2] Hexagon: move GETPC() calls to top level helpers

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Thursday, July 6, 2023 5:23 AM > To: ltaylorsimp...@gmail.com > Cc: bc...@quicinc.com; qemu-devel@nongnu.org; > quic_mathb...@quicinc.com; quic_mlie...@quicinc.com; > richard.hender...@linaro.org > Subject: Re: [PATCH v2] H

RE: [PATCH] Hexagon: move GETPC() calls to top level helpers

-Original Message- From: Matheus Tavares Bernardino Sent: Monday, July 3, 2023 3:50 PM To: qemu-devel@nongnu.org Cc: bc...@quicinc.com; quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com Subject: [PATCH] Hexagon: move GETPC() calls to top level helpers As docs/devel/loads-stores.rst s

RE: [PATCH 3/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos

> -Original Message- > From: Brian Cain > Sent: Monday, December 4, 2023 9:46 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: Matheus Bernardino (QUIC) ; Sid > Manning ; Marco Liebel (QUIC) > ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng > Subject:

RE: [PATCH 3/9] Hexagon (target/hexagon) Make generators object oriented - gen_helper_protos

> -Original Message- > From: ltaylorsimp...@gmail.com > Sent: Tuesday, December 5, 2023 11:08 AM > To: 'Brian Cain' ; qemu-devel@nongnu.org > Cc: 'Matheus Bernardino (QUIC)' ; 'Sid > Manning' ; 'Marco Liebel (QUIC)' > ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a..

RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented

> -Original Message- > From: Brian Cain > Sent: Wednesday, November 15, 2023 1:51 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: Matheus Bernardino (QUIC) ; Sid > Manning ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng > Subject: RE: [RFC PATCH] Hexa

RE: [RFC PATCH] Hexagon (target/hexagon) Make generators object oriented

> -Original Message- > From: Brian Cain > Sent: Thursday, November 16, 2023 10:25 AM > To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org > Cc: Matheus Bernardino (QUIC) ; Sid > Manning ; richard.hender...@linaro.org; > phi...@linaro.org; a...@rev.ng; a...@rev.ng > Subject: RE: [RFC PA

RE: [PATCH 0/3] Hexagon (target/hexagon) Enable more short-circuit packets

Looks like a problem with git send-email ☹ I will troubleshoot ... > -Original Message- > From: Anton Johansson > Sent: Thursday, November 2, 2023 6:44 PM > To: Taylor Simpson > Cc: qemu-devel@nongnu.org > Subject: Re: [PATCH 0/3] Hexagon (target/hexagon) Enable more short- > circuit p

RE: [PATCH] Hexagon: fix F2_conv_* instructions for negative zero

> -Original Message- > From: Matheus Tavares Bernardino > Sent: Sunday, July 28, 2024 11:16 AM > To: qemu-devel@nongnu.org > Cc: ltaylorsimp...@gmail.com; bc...@quicinc.com; sidn...@quicinc.com; > a...@rev.ng; a...@rev.ng > Subject: [PATCH] Hexagon: fix F2_conv_* instructions for negati

RE: [PATCH] target/hexagon: define a v66 CPU

> -Original Message- > From: Brian Cain > Sent: Tuesday, July 30, 2024 7:10 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com > Subject: [PATCH] target/hexagon: define a v66 CPU

RE: [PATCH] target/hexagon: switch to dc set_props() list

> -Original Message- > From: Brian Cain > Sent: Tuesday, July 30, 2024 7:13 PM > To: qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com > Subject: [PATCH] target/hexagon: switch to dc set_

RE: [PATCH] Hexagon (target/hexagon) Remove HEX_DEBUG/HEX_DEBUG_LOG

> -Original Message- > From: Brian Cain > Sent: Monday, November 4, 2024 3:52 PM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: bc...@quicinc.com; quic_mathb...@quicinc.com; > sidn...@quicinc.com; quic_mlie...@quicinc.com; > richard.hender...@linaro.org; phi...@linaro.org; a...@rev.

RE: [RFC PATCH v1 36/43] target/hexagon: Add temporary vector storage

> -Original Message- > From: Brian Cain > Sent: Tuesday, December 3, 2024 1:28 PM > To: Anton Johansson ; Richard Henderson > > Cc: qemu-devel@nongnu.org; a...@rev.ng; ltaylorsimp...@gmail.com; > bc...@quicinc.com; phi...@linaro.org; alex.ben...@linaro.org > Subject: Re: [RFC PATCH v1

RE: [PATCH 15/38] target/hexagon: Add handlers for guest/sysreg r/w

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 12/38] target/hexagon: Add imported macro, attr defs for sysemu

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 14/38] target/hexagon: Add new macro definitions for sysemu

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 22/38] target/hexagon: Add sysemu TCG overrides

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 24/38] target/hexagon: Add TCG overrides for int handler insts

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 25/38] target/hexagon: Add TCG overrides for thread ctl

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 21/38] target/hexagon: Add system reg insns

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 13/38] target/hexagon: Define DCache states

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 18/38] target/hexagon: Make A_PRIV, "J2_trap*" insts need_env()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 17/38] target/hexagon: Add vmstate representation

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 19/38] target/hexagon: Define register fields for system regs

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 20/38] target/hexagon: Implement do_raise_exception()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 16/38] target/hexagon: Add placeholder greg/sreg r/w helpers

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 05/38] target/hexagon: Switch to tag_ignore(), generate via get_{user, sys}_tags()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock

> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Tuesday, March 4, 2025 6:19 PM > To: ltaylorsimp...@gmail.com; richard.hender...@linaro.org; 'Brian Cain' > ; qemu-devel@nongnu.org > Cc: quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; alex.ben

RE: [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock

> -Original Message- > From: Brian Cain > Sent: Monday, March 3, 2025 10:24 AM > To: qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; > quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com; > alex.ben...@li

RE: [PATCH 34/39] target/hexagon: Add TLB, k0 {un,}lock

> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Tuesday, March 4, 2025 5:58 PM > To: richard.hender...@linaro.org; ltaylorsimp...@gmail.com; 'Brian Cain' > ; qemu-devel@nongnu.org > Cc: quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; alex.ben

RE: [PATCH 03/38] target/hexagon: Add System/Guest register definitions

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 09/38] target/hexagon: Add guest, system reg number state

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 11/38] target/hexagon: Add guest/sys reg writes to DisasContext

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 08/38] target/hexagon: Add guest, system reg number defs

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 04/38] target/hexagon: Make gen_exception_end_tb non-static

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 06/38] target/hexagon: Add privilege check, use tag_ignore()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 07/38] target/hexagon: Add a placeholder fp exception

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 31/38] target/hexagon: Add {TLB, k0}lock, cause code, wait_next_pc

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 32/38] target/hexagon: Add stubs for modify_ssr/get_exe_mode

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 30/38] target/hexagon: Add a TLB count property

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 27/38] target/hexagon: Add sreg_{read,write} helpers

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 29/38] target/hexagon: Add locks, id, next_PC to state

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 23/38] target/hexagon: Add implicit attributes to sysemu macros

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 28/38] target/hexagon: Initialize htid, modectl regs

> -Original Message- > From: Philippe Mathieu-Daudé > Sent: Wednesday, March 12, 2025 6:40 PM > To: Brian Cain ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; quic_mathb...@quicinc.com; > a...@rev.ng; a...@rev.ng; quic_mlie...@quicinc.com; > ltaylorsimp...@gmail.com; alex.be

RE: [PATCH 01/38] docs: Add hexagon sysemu docs

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 02/38] docs/system: Add hexagon CPU emulation

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 02/38] docs/system: Add hexagon CPU emulation

> -Original Message- > From: Brian Cain > Sent: Wednesday, March 5, 2025 2:13 PM > To: ltaylorsimp...@gmail.com; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; > quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; alex.ben...@li

RE: [PATCH 33/38] target/hexagon: Add gdb support for sys regs

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 26/38] target/hexagon: Add TCG overrides for rte, nmi

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 38/38] target/hexagon: Add hex_interrupts support

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 37/38] target/hexagon: Define f{S,G}ET_FIELD macros

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 34/38] target/hexagon: Add initial MMU model

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 35/38] target/hexagon: Add IRQ events

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 36/38] target/hexagon: Add clear_wait_mode() definition

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 10/38] target/hexagon: Add TCG values for sreg, greg

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:26 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 04/39] target/hexagon: Implement start/stop helpers

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 05/39] target/hexagon: Implement modify SSR

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 06/39] target/hexagon: Implement {g,s}etimask helpers

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 03/39] target/hexagon: Implement iassign{r,w} helpers

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 01/39] target/hexagon: Implement ciad helper

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 07/39] target/hexagon: Implement wait helper

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 19/39] target/hexagon: Implement hexagon_tlb_fill()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 20/39] target/hexagon: Implement siad inst

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 24/39] target/hexagon: Add exec-start-addr prop

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 25/39] target/hexagon: Add hexagon_cpu_mmu_index()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 26/39] target/hexagon: Decode trap1, rte as COF

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 28/39] target/hexagon: Implement modify_ssr, resched, pending_interrupt

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 29/39] target/hexagon: Add pkt_ends_tb to translation

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:29 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 09/39] target/hexagon: Implement arch_get_system_reg()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 15/39] target/hexagon: Implement hex_tlb_entry_get_perm()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 14/39] target/hexagon: Add system event, cause codes

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 08/39] target/hexagon: Implement get_exe_mode()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 10/39] target/hexagon: Implement arch_{s, g}et_{thread, system}_reg()

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

RE: [PATCH 11/39] target/hexagon: Add representation to count cycles

> -Original Message- > From: Brian Cain > Sent: Friday, February 28, 2025 11:28 PM > To: qemu-devel@nongnu.org > Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org; > phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng; > quic_mlie...@quicinc.com; ltaylorsi

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