> -----Original Message-----
> From: Brian Cain <brian.c...@oss.qualcomm.com>
> Sent: Friday, February 28, 2025 11:28 PM
> To: qemu-devel@nongnu.org
> Cc: brian.c...@oss.qualcomm.com; richard.hender...@linaro.org;
> phi...@linaro.org; quic_mathb...@quicinc.com; a...@rev.ng; a...@rev.ng;
> quic_mlie...@quicinc.com; ltaylorsimp...@gmail.com;
> alex.ben...@linaro.org; quic_mbur...@quicinc.com;
> sidn...@quicinc.com; Brian Cain <bc...@quicinc.com>
> Subject: [PATCH 04/39] target/hexagon: Implement start/stop helpers
>
> From: Brian Cain <bc...@quicinc.com>
>
> Signed-off-by: Brian Cain <brian.c...@oss.qualcomm.com>
> ---
> target/hexagon/cpu.h | 3 ++
> target/hexagon/cpu_bits.h | 1 +
> target/hexagon/cpu_helper.h | 3 ++
> target/hexagon/cpu.c | 14 +++++-
> target/hexagon/cpu_helper.c | 94
> +++++++++++++++++++++++++++++++++++++
> target/hexagon/op_helper.c | 4 +-
> 6 files changed, 116 insertions(+), 3 deletions(-)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index
> 894219fd20..1549c4f1f0 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -41,6 +41,7 @@ typedef struct CPUHexagonTLBContext
> CPUHexagonTLBContext; #define REG_WRITES_MAX 32
> #define PRED_WRITES_MAX 5 /* 4 insns + endloop */
> #define VSTORES_MAX 2
> +#define VECTOR_UNIT_MAX 8
Not related to start/stop and not used in this patch.
>
> #ifndef CONFIG_USER_ONLY
> #define CPU_INTERRUPT_SWI CPU_INTERRUPT_TGT_INT_0
> @@ -178,6 +179,7 @@ struct ArchCPU {
> #ifndef CONFIG_USER_ONLY
> uint32_t num_tlbs;
> uint32_t l2vic_base_addr;
> + uint32_t hvx_contexts;
Not related to start/stop.
> #endif
> };
>
> @@ -194,6 +196,7 @@ G_NORETURN void
> hexagon_raise_exception_err(CPUHexagonState *env, uint32_t
> hexagon_greg_read(CPUHexagonState *env, uint32_t reg); uint32_t
> hexagon_sreg_read(CPUHexagonState *env, uint32_t reg); void
> hexagon_gdb_sreg_write(CPUHexagonState *env, uint32_t reg, uint32_t
> val);
> +void hexagon_cpu_soft_reset(CPUHexagonState *env);
> #endif
>
> #include "exec/cpu-all.h"
> diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index
> b559a7ba88..610094a759 100644
> --- a/target/hexagon/cpu_bits.h
> +++ b/target/hexagon/cpu_bits.h
> @@ -52,6 +52,7 @@ enum hex_event {
>
> enum hex_cause {
> HEX_CAUSE_NONE = -1,
> + HEX_CAUSE_RESET = 0x000,
> HEX_CAUSE_TRAP0 = 0x172,
> HEX_CAUSE_FETCH_NO_UPAGE = 0x012,
> HEX_CAUSE_INVALID_PACKET = 0x015,
> diff --git a/target/hexagon/cpu_helper.h b/target/hexagon/cpu_helper.h
> index 6f0c6697ad..95a0cc0788 100644
> --- a/target/hexagon/cpu_helper.h
> +++ b/target/hexagon/cpu_helper.h
> @@ -17,6 +17,9 @@ void
> hexagon_set_sys_pcycle_count_high(CPUHexagonState *env, uint32_t);
> void hexagon_modify_ssr(CPUHexagonState *env, uint32_t new, uint32_t
> old); int get_exe_mode(CPUHexagonState *env); void
> clear_wait_mode(CPUHexagonState *env);
> +void hexagon_ssr_set_cause(CPUHexagonState *env, uint32_t cause); void
> +hexagon_start_threads(CPUHexagonState *env, uint32_t mask); void
> +hexagon_stop_thread(CPUHexagonState *env);
>
> static inline void arch_set_thread_reg(CPUHexagonState *env, uint32_t reg,
> uint32_t val) diff --git
> a/target/hexagon/cpu.c
> b/target/hexagon/cpu.c index cb56b929cf..84a96a194b 100644
> --- a/target/hexagon/cpu.c
> +++ b/target/hexagon/cpu.c
> @@ -32,6 +32,7 @@
>
> #ifndef CONFIG_USER_ONLY
> #include "sys_macros.h"
> +#include "qemu/main-loop.h"
> #endif
>
> static void hexagon_v66_cpu_init(Object *obj) { } @@ -61,6 +62,7 @@ static
> const Property hexagon_cpu_properties[] = {
> DEFINE_PROP_UINT32("jtlb-entries", HexagonCPU, num_tlbs,
> MAX_TLB_ENTRIES),
> DEFINE_PROP_UINT32("l2vic-base-addr", HexagonCPU, l2vic_base_addr,
> 0xffffffffULL),
> + DEFINE_PROP_UINT32("hvx-contexts", HexagonCPU, hvx_contexts, 0),
Not related to start/stop.
> #endif
> DEFINE_PROP_BOOL("lldb-compat", HexagonCPU, lldb_compat, false),
