Property
in maximum priority level.
Signed-off-by: Emmanuel Blot
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/intc/sifive_plic.c | 6 --
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c
index af4ae3630e..f864efa761 100644
hange
each bit of interrupt priority register to WARL field when the number of
supported priority is power-of-2.
[1]
https://github.com/riscv/riscv-plic-spec/blob/master/riscv-plic.adoc#interrupt-priorities
Signed-off-by: Jim Shu
---
hw/intc/sifive_plic.c | 21 +++--
1 file change
This patchset fixes hard-coded maximum priority of interrupt priority
register and also changes this register to WARL field to align the PLIC
spec.
Changelog:
v3:
* fix opposite of power-of-2 max priority checking expression.
v2:
* change interrupt priority register to WARL field.
Jim Shu
On Thu, Aug 8, 2024 at 9:34 PM Peter Maydell wrote:
>
> On Thu, 1 Aug 2024 at 15:08, Jim Shu wrote:
> >
> > The memory transactions from DMA could have bus-error in some cases. If
> > it is failed, DMA device should send error IRQs.
> >
> > Signed-off-by
f-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/translate.c | 45 ++--
1 file changed, 34 insertions(+), 11 deletions(-)
diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index 0569224e53..2be8ef63e6 100644
--- a/target/riscv/transla
supported in virDomainMigrate* APIs, but obviously those
APIs don't accept --bypass-cache.
Regards,
Jim
Another option which would be for libvirt to keep using multifd, but
make it 1 channel only if --parallel is not specified. That might be
enough to solve the interface issues. Of cour
11: Add WG global device and CPU extensions
4. Commit 12 ~ 15: Add WG checker device
5. Commit 16: Add WG support to the virt machine
Jim Shu (16):
accel/tcg: Store section pointer in CPUTLBEntryFull
accel/tcg: memory access from CPU will pass access_type to IOMMU
exec: Add RISC-V WorldGu
tion so that IOMMU could return the correct section
of specified access_type.
Signed-off-by: Jim Shu
---
accel/tcg/cputlb.c | 15 +--
include/exec/exec-all.h | 11 +++
system/physmem.c | 16 +++-
target/alpha/help
signal.
Signed-off-by: Jim Shu
---
include/exec/memattrs.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/include/exec/memattrs.h b/include/exec/memattrs.h
index 14cdd8d582..d00f3c5500 100644
--- a/include/exec/memattrs.h
+++ b/include/exec/memattrs.h
@@ -52,6 +52,11 @@ typedef struct
OMMU devices don't have this issue since they are only in the
path of DMA access. Currently, the bug only occurs when ARM MPC device
(hw/misc/tz-mpc.c) returns 'blocked_io_as' to emulate blocked access
handling. Upcoming RISC-V wgChecker device is also affected by this bug.
Some WG CPU functions depend on global WG config (like num-of-world), so
we let the global WG config device to set callbacks of a RISC-V HART.
Signed-off-by: Jim Shu
---
target/riscv/cpu.h | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index
ansactions
Signed-off-by: Jim Shu
---
hw/misc/meson.build| 2 +-
hw/misc/riscv_wgchecker.c | 604 +
hw/misc/trace-events | 8 +
include/hw/misc/riscv_worldguard.h | 63 +++
4 files changed, 676 insertions(+), 1 deletion(-)
c
that point.
One tricky part here is that the perm of 'blocked_io_as' is the
condition of deny access. For example, if wgChecker only permits RO
access, the perm of 'downstream_as' will be IOMMU_RO and the perm of
'blocked_io_as' will be IOMMU_WO.
Signed
The WG v0.4 specification adds 3 CSRs to configure S/U/HS/VS-mode WIDs
of CPUs in the higher privileged modes.
The Smwg extension at least requires a RISC-V HART to have M/U-mode, and
the Sswg/Smwgd extension at least requires a RISC-V HART to have
M/S/U-mode.
Signed-off-by: Jim Shu
---
target
The wgChecker is configurable for whether blocked accesses:
* should cause a bus error or just read return zero and write ignore
* should generate the interrupt or not
Signed-off-by: Jim Shu
---
hw/misc/riscv_wgchecker.c | 169 +-
1 file changed, 167
Add CSRs for 3 WG extensions: Smwg, Smwgd, and Sswg.
Signed-off-by: Jim Shu
---
target/riscv/cpu_bits.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h
index 74318a925c..3ea8a8e9a0 100644
--- a/target/riscv/cpu_bits.h
+++ b/target/riscv
* Add 'wg=on' option to enable RISC-V WorldGuard
* Add wgChecker to protect several resources:
DRAM, FLASH, UART.
Signed-off-by: Jim Shu
---
docs/system/riscv/virt.rst | 10 +++
hw/riscv/Kconfig | 1 +
hw/riscv/virt.c
wgChecker slot is similar to PMP region. SW could program each slot to
configure the permission of address range.
Signed-off-by: Jim Shu
---
hw/misc/riscv_wgchecker.c | 330 +
hw/misc/riscv_worldguard.c | 3 +
include/hw/misc/riscv_worldguard.h
When a RISC-V HART has WG extension, their memory transactions will
contain WID. Support MemTxAttrs in RISC-V target and add WID inside if
a HART has WG extension.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c| 2 +-
target/riscv/cpu.h| 1 +
target/riscv/cpu_helper.c | 51
riscv_worldguard_apply_cpu() could enable WG CPU extension and set WG
callback to CPUs. It is used by machine code after realizing global WG
device.
Signed-off-by: Jim Shu
---
hw/misc/riscv_worldguard.c | 87 ++
include/hw/misc/riscv_worldguard.h | 1 +
2
We define CPU options for WG CSR support in RISC-V CPUs which
can be set by machine/device emulation. The RISC-V CSR emulation
will also check this feature for emulating WG CSRs.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c | 8
target/riscv/cpu_cfg.h | 3 +++
target
Add a device for RISCV WG global config, which contains the number of
worlds, reset value, and trusted WID ... etc.
This global config is used by both CPU WG extension and wgChecker devices.
Signed-off-by: Jim Shu
---
hw/misc/Kconfig| 3 +
hw/misc/meson.build
s, we should
set it by machine code.
Signed-off-by: Jim Shu
---
target/riscv/cpu.c| 2 ++
target/riscv/cpu.h| 2 ++
target/riscv/cpu_cfg.h| 2 ++
target/riscv/cpu_helper.c | 18 ++
4 files changed, 24 insertions(+)
diff --git a/target/riscv/cpu.c b/targe
permission. At least this mechanism has the
correct behavior.
Thanks,
Jim
On Thu, Jun 13, 2024 at 1:34 PM Ethan Chen wrote:
>
> On Wed, Jun 12, 2024 at 04:14:02PM +0800, Jim Shu wrote:
> > [EXTERNAL MAIL]
> >
> > It is the preparation patch for upcoming RISC-V wgChecker de
t supported in QEMU, which is similar to MPC
or wgChecker device.)
Thanks,
Jim Shu
On Thu, Jun 13, 2024 at 2:23 PM LIU Zhiwei wrote:
>
> On 2024/6/12 16:14, Jim Shu wrote:
> > 'CPUTLBEntryFull.xlat_section' stores section_index in last 12 bits to
> >
pci_dev_realize() use the local error variable, which requires
`error_setg()` API to allocate the error object at first.
Signed-off-by: Jim Shu
---
hw/vfio/pci.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c
index 0a99e55247..d994ad8bb9 100644
Hi Cédric,
Thank you very much for the quick response!
I have checked the error API again. It seems to be my porting issue of
set_iommu_device() callback.
I think "pci_device_set_iommu_device(..., *errp)" should set 'errp' if
this function returns false, right?
Thanks,
Jim
On Thu, Sep 12, 2024 at 5:56 PM Cédric Le Goater wrote:
>
> Hello Jim,
>
> On 9/12/24 08:36, Jim Shu wrote:
> > Hi Cédric,
> >
> > Thank you very much for the quick response!
> >
> > I have checked the error API again. It seems to be my porting issue o
ion is based on priv spec v1.12:
"When a virtual page is accessed and the A bit is clear, or is written
and the D bit is clear, a page-fault exception (corresponding to the
original access type) is raised."
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/cpu.c
in RISC-V priv spec,
so I think it's reasonable to implement them in QEMU. The only issue here is
to choose a proper CPU option name to turn on/off HW update of A/D bits.
Regards,
Jim Shu
On Mon, Jul 18, 2022 at 12:02 PM Anup Patel wrote:
> +Atish
>
> On Mon, Jul 18, 2022 at 9
Hi all,
Thanks for the work!
I'm from SiFive and we are very interested in this feature.
QMP/QAPI configurable QEMU machine is a useful feature in our use case.
With this feature, we can both model our versatile FPGA-based platforms
more easily and model a new platform without modification of sou
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_get() returns the current phase, we'll use it in next
> commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> ---
> include/hw/qdev-core.h | 19 +++
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> From: Mirela Grujic
>
> This commit allows to use the QMP command to add a cold-plugged
> device like we can do with the CLI option -device.
>
> Note: for device_add command in qdev.json adding th
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:37 PM Damien Hedde
wrote:
> Instead of checking the phase everytime, just store the result
> in a flag. We will use more of it in the following commit.
>
> Signed-off-by: Damien Hedde
> Reviewed-by: Philippe Mathieu-Daudé
> -
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:41 PM Damien Hedde
wrote:
> phase_until() is implemented in vl.c and is meant to be used
> to make startup progress up to a specified phase being reached().
> At this point, no behavior change is introduced: phase_until()
> only suppo
Tested-by: Jim Shu
On Thu, May 19, 2022 at 11:36 PM Damien Hedde
wrote:
> phase_until() now supports the following transitions:
> + accel-created -> machine-initialized
> + machine-initialized -> machine-ready
>
> As a consequence we can now support the use of qmp_ex
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:18 PM Damien Hedde
wrote:
> rom_set_order_override() and rom_reset_order_override() were called
> in qemu_create_cli_devices() to set the rom_order_override value
> once and for all when creating the devices added on CLI.
>
> Unf
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:59 PM Damien Hedde
wrote:
> The none machine was using the parent state structure.
> We'll need a custom state to add a field in the following commit.
>
> Signed-off-by: Damien Hedde
> ---
> hw/c
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:37 PM Damien Hedde
wrote:
> This command allows to map an mmio region of sysbus device onto
> the system memory. Its behavior mimics the sysbus_mmio_map()
> function apart from the automatic unmap (the C function unmaps
> the region if i
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 12:36 AM Damien Hedde
wrote:
>
>
> On 3/3/22 15:41, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:07, Damien Hedde wrote:
> >> Add the property to configure a the base address of the ram.
> >> The default value remai
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 11:23 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > The devices are:
> > + ibex-timer
> > + ibex-uart
> > + riscv.aclint.swi
> > + ris
Tested-by: Jim Shu
On Wed, Feb 23, 2022 at 5:14 PM Damien Hedde
wrote:
> This device can be used to create a memory wrapped into a
> sysbus device.
> This device has one property 'readonly' which allows
> to choose between a ram or a rom.
>
> The purpose for this de
Tested-by: Jim Shu
On Thu, Mar 3, 2022 at 10:46 PM Philippe Mathieu-Daudé <
philippe.mathieu.da...@gmail.com> wrote:
> On 23/2/22 10:07, Damien Hedde wrote:
> > Allow plugging any sysbus device on this machine (the sysbus
> > devices still need to be 'user-creatable
Tested-by: Jim Shu
On Fri, Mar 4, 2022 at 7:00 PM Damien Hedde
wrote:
>
>
>
> On 3/3/22 14:32, Philippe Mathieu-Daudé wrote:
> > On 23/2/22 10:12, Damien Hedde wrote:
> >> Hi Philippe,
> >>
> >> I suppose it is ok if I change your mail in the rev
Gentle ping.
It's a patch for fix and spec alignment of PLIC.
On Mon, Oct 3, 2022 at 12:14 PM Jim Shu wrote:
>
> This patchset fixes hard-coded maximum priority of interrupt priority
> register and also changes this register to WARL field to align the PLIC
> spec.
>
This patch also enables debugger to set current privilege mode to
VU/VS-mode.
Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
support H-extension.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
target/riscv/gdbstub.c | 18 --
1 file changed, 16
This patch enables a debugger to read current virtualization mode via
virtual "virt" register. After it, we could get full current privilege
mode via both "priv" and "virt" register.
Extend previous commit ab9056ff9bdb3f95db6e7a666d10522d289f14ec to
support H-exte
HiFive Unmatched PDMA supports high/low 32-bit access of 64-bit
register, but QEMU emulation support low part access now. Enhance QEMU
emulation to support high 32-bit access.
Also, permit 4/8-byte valid access in PDMA as we have verified 32/64-bit
accesses of PDMA registers are supported.
Jim
It's obvious that PDMA support 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA support 32-bit access of both
32/64-bit registers. Thus, we configure 32/64-bit memory access of
PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by: Frank
2 80001000 0002
=> md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
28000: 12345678 xV4.
280001000: 12345678 xV4.
Signed-off-by: Jim Shu
Reviewed-by: Frank Chang
---
hw/dma/sifiv
Hi Bin,
Thanks for the review.
I will fix the commit log and the behavior of writing high 32-bit of RO
registers in v2 patch.
Thanks,
Jim Shu
On Tue, Jan 4, 2022 at 10:55 AM Bin Meng wrote:
> Hi Jim,
>
> On Tue, Dec 28, 2021 at 8:53 AM Jim Shu wrote:
> >
> > Real PDM
It's obvious that PDMA supports 64-bit access of 64-bit registers, and
in previous commit, we confirm that PDMA supports 32-bit access of
both 32/64-bit registers. Thus, we configure 32/64-bit memory access
of PDMA registers as valid in general.
Signed-off-by: Jim Shu
Reviewed-by: Frank
2 80001000 0002
=> md.l 0x28000 1; md.l 0x280001000 1 <= Dump src/dst memory contents
28000: 12345678 xV4.
280001000: 12345678 xV4.
Signed-off-by: Jim Shu
Reviewed
.
Changelog:
v2:
* Fix high 32-bit write access of 64-bit RO registers
* Fix commit log
Jim Shu (2):
hw/dma: sifive_pdma: support high 32-bit access of 64-bit register
hw/dma: sifive_pdma: permit 4/8-byte access size of PDMA registers
hw/dma/sifive_pdma.c | 181
behavior on
signaling-NaN inputs to conform to the minimumNumber and maximumNumber
operations
in the proposed IEEE 754-201x specification.
But if qemu doesn't have minimumNumber support yet, then yes minNum is correct.
This is discussed a bit here
https://github.com/riscv/riscv-isa-manual/issues/65
Jim
hardware does. This could take a little time to sort
out.
Jim
On Wed, Jan 24, 2018 at 3:47 PM, Richard Henderson
wrote:
> On 01/24/2018 10:58 AM, Jim Wilson wrote:
>> Although, looking at this again, I see another statement in a
>> different place that says:
>>
>> Except when otherwise stated, if the result of a floating-point ope
figure out what the problem is.
Reviewed-by: Liam Merwick
Signed-off-by: Jim Quigley
---
Cc: qemu-triv...@nongnu.org
Cc: m...@tls.msk.ru
Cc: laur...@vivier.eu
Cc: alex.william...@redhat.com
---
hw/vfio/pci.c | 35 ---
1 file changed, 24 insertions(+), 11 deletions
The gdb CSR xml file has registers in documentation order, not numerical
order, so we need a table to map the register numbers. This also adds
some missing CSR_* register macros.
Signed-off-by: Jim Wilson
---
target/riscv/cpu_bits.h | 35 ++-
target/riscv/csr-map.h | 248
Signed-off-by: Jim Wilson
---
target/riscv/cpu.c | 9 ++-
target/riscv/gdbstub.c | 73 --
2 files changed, 73 insertions(+), 9 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a025a0a..b248e3e 100644
--- a/target
Signed-off-by: Jim Wilson
---
configure | 1 +
gdb-xml/riscv-64bit-cpu.xml | 43
gdb-xml/riscv-64bit-csr.xml | 250
gdb-xml/riscv-64bit-fpu.xml | 52 +
4 files changed, 346 insertions(+)
create mode 100644 gdb
Adds a debugger parameter to csr_read_helper and csr_write_helper. When
this is true, we disable illegal instruction checks.
Signed-off-by: Jim Wilson
---
linux-user/riscv/signal.c | 5 ++-
target/riscv/cpu.h| 7 +++-
target/riscv/cpu_helper.c | 4 +-
target/riscv/gdbstub.c| 4
Signed-off-by: Jim Wilson
---
configure | 1 +
gdb-xml/riscv-32bit-cpu.xml | 43
gdb-xml/riscv-32bit-csr.xml | 250
gdb-xml/riscv-32bit-fpu.xml | 46
4 files changed, 340 insertions(+)
create mode 100644 gdb
h there is an unanswered question in there about what to do with
the FP registers. Should we try to configure them based on the
target? Right now I just always enable them which is the simple
solution. I'm not sure if enabling them based on the target will even
work with gdb or not.
Jim
On Sat, Dec 29, 2018 at 2:23 PM Richard Henderson
wrote:
> On 12/29/18 9:09 AM, Jim Wilson wrote:
> > +int csr_register_map[] = {
>
> static const?
If I add static const here, then I get a build error if this patch is
applied to the tree but the following patch #5 that uses the
On Sat, Dec 29, 2018 at 2:20 PM Richard Henderson
wrote:
> On 12/29/18 9:07 AM, Jim Wilson wrote:
> Don't the csr's vary between priv-1.9.1 and priv-1.10?
There are a few csr's that disappear in 1.10, but there is no known
hardware that implements them. There are a few csr
Public bug reported:
Running the following leads to a qemu crash on startup:
jwhite@laptop:~/os$ qemu-system-i386 -overcommit cpu-pm=on
qemu-system-i386: -overcommit cpu-pm=on: There is no option group 'overcommit'
Segmentation fault (core dumped)
jwhite@laptop:~/os$
This fixes the issue:
---
Public bug reported:
I run old DOS programs under FreeDOS using QEMU.
It's common when running/testing DOS applications to use the function
keys. Some of these (such as F10) are intercepted by the window system.
For example, some DOS program installers use F10 to install the
software, but F10 is
On 16/10/2017 19:07, Michael Tokarev wrote:
10.10.2017 13:22, Jim Quigley wrote:
More information is required to assist trouble-shooting when
QEMU fails to initialise the event notifications for devices
assigned with VFIO-PCI. Instead of supplying the user with a cryptic
error number only
Reviewed-by: Jim Shu
On Tue, Jul 9, 2024 at 7:39 PM LIU Zhiwei
wrote:
> Zimop extension defines an encoding space for 40 MOPs.The Zimop
> extension defines 32 MOP instructions named MOP.R.n, where n is
> an integer between 0 and 31, inclusive. The Zimop extension
> additionally d
On Tue, Jul 9, 2024 at 7:41 PM LIU Zhiwei
wrote:
> Signed-off-by: LIU Zhiwei
> Acked-by: Alistair Francis
> Reviewed-by: Deepak Gupta
>
Reviewed-by: Jim Shu
cpu.c | 5
> target/riscv/translate.c| 1 +
> 6 files changed, 39 insertions(+)
> create mode 100644 target/riscv/insn_trans/trans_rvzcmop.c.inc
>
Reviewed-by: Jim Shu
an be redefined by later extension.
>
> Signed-off-by: LIU Zhiwei
> Acked-by: Alistair Francis
> Reviewed-by: Deepak Gupta
> ---
> disas/riscv.c | 23 +++
> 1 file changed, 23 insertions(+)
Reviewed-by: Jim Shu
Rename DT_BINDNOW to DT_BIND_NOW to align with glibc header: "elf/elf.h"
Signed-off-by: Jim Shu
---
include/elf.h | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/include/elf.h b/include/elf.h
index e7259ec366..ef47b5e2ad 100644
--- a/include/elf.h
+++ b/inc
Let gen-vdso tool to use QEMU's internal ELF header. It could avoid
compatibility issue of glibc version in the environment. QEMU RISC-V
zicfiss/lp extension patchset will add "EM_RISCV" symbol to it. This
symbol is not supported in the legacy glibc.
Jim Shu (2):
include/elf.h:
Add include path to 'gen-vdso.c' to get ELF header in QEMU source.
Signed-off-by: Jim Shu
---
linux-user/meson.build | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/linux-user/meson.build b/linux-user/meson.build
index bc41e8c3bc..ccce4f7e70 100644
--- a/
Currently, txlen is always decremented to 0 before filling to the
descriptor. Keep the origin txlen value to have the correct value of
descriptor status field.
It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver.
Signed-off-by: Jim Shu
---
hw/dma/xilinx_ax
ckets when enabling it.
Signed-off-by: Jim Shu
---
hw/net/xilinx_axienet.c | 71 -
1 file changed, 42 insertions(+), 29 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 05d41bd548..8428f10946 100644
--- a/hw/net/xilinx_axie
Current DMA/Stream reset will clear interrupt pending bit of DMA device.
The qemu_irq of device should be updated at the same time.
Signed-off-by: Jim Shu
---
hw/dma/xilinx_axidma.c | 25 +
1 file changed, 13 insertions(+), 12 deletions(-)
diff --git a/hw/dma
The memory transactions from DMA could have bus-error in some cases. If
it is failed, DMA device should send error IRQs.
Signed-off-by: Jim Shu
---
hw/dma/trace-events| 1 +
hw/dma/xilinx_axidma.c | 69 ++
2 files changed, 50 insertions(+), 20
Fix txlen value in the descriptor status field, DMA error handling,
and ethernet/DMA reset flow.
*** BLURB HERE ***
Jim Shu (4):
hw/dma: xilinx_axidma: Correct the txlen value in the descriptor
hw/dma: xilinx_axidma: Send DMA error IRQ if any memory access is
failed
hw/dma
Hi Richard,
Thanks for your feedback.
I think it is reasonable. I will drop this patchset.
Regards,
Jim Shu
On Fri, Jul 26, 2024 at 1:28 PM Richard Henderson
wrote:
>
> On 7/26/24 14:32, Jim Shu wrote:
> > Let gen-vdso tool to use QEMU's internal ELF header. It could avoid
Hi Peter,
Thanks for the suggestion.
axienet_eth_rx_notify() is also called by axidma_write() as a notify()
callback, so we need to check RCW1_RX in the function.
I think I could remove RCW1_RX checking in the enet_write() to avoid
double checking.
I will fix it in the v2 patchset.
Thanks,
JIm
Hi Peter,
Except DeviceState::reset(), stream_reset() is only used in
axidma_write() and axidma_write() has qemu_set_irq() at the end of
function.
I think this commit could be dropped. I will remove it in the v2 patchset.
Thanks,
Jim Shu
On Mon, Jul 29, 2024 at 11:23 PM Peter Maydell wrote
The memory transactions from DMA could have bus-error in some cases. If
it is failed, DMA device should send error IRQs.
Signed-off-by: Jim Shu
---
hw/dma/trace-events| 1 +
hw/dma/xilinx_axidma.c | 69 ++
2 files changed, 50 insertions(+), 20
Currently, txlen is always decremented to 0 before filling to the
descriptor. Keep the origin txlen value to have the correct value of
descriptor status field.
It will fix the 'tx_bytes' statistic value in linux axi-ethernet driver.
Signed-off-by: Jim Shu
---
hw/dma/xilinx_ax
v2:
- Remove redundant RCW1_RX checking in enet_write()
- Remove qemu_set_irq() in DeviceState::reset()
Fix txlen value in the descriptor status field, DMA error handling,
and ethernet/DMA reset flow.
Jim Shu (3):
hw/dma: xilinx_axidma: Correct the txlen value in the descriptor
hw/dma
ckets when enabling it.
Signed-off-by: Jim Shu
---
hw/net/xilinx_axienet.c | 71 -
1 file changed, 42 insertions(+), 29 deletions(-)
diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c
index 05d41bd548..0ecdc30be6 100644
--- a/hw/net/xilinx_axie
On Thu, Jul 9, 2020 at 2:44 AM Gerd Hoffmann wrote:
> (2) GUEST_MAXPHYADDR < HOST_MAXPHYADDR
>
> Mostly fine. Some edge cases, like different page fault errors for
> addresses above GUEST_MAXPHYADDR and below HOST_MAXPHYADDR. Which I
> think Mohammed fixed in the kernel recently.
D
On Mon, Sep 30, 2019 at 10:54 AM Eduardo Habkost wrote:
>
> CCing qemu-devel.
>
> On Tue, Sep 24, 2019 at 01:30:04PM -0700, Jim Mattson wrote:
> > On Wed, Dec 19, 2018 at 1:02 PM Paolo Bonzini wrote:
> > >
> > > On 19/12/18 18:39, Jim Mattson wrote:
> >
On Mon, Sep 30, 2019 at 5:45 PM Huang, Kai wrote:
>
> On Mon, 2019-09-30 at 12:23 -0700, Jim Mattson wrote:
> > On Mon, Sep 30, 2019 at 10:54 AM Eduardo Habkost
> > wrote:
> > > CCing qemu-devel.
> > >
> > > On Tue, Sep 24, 2019 at 01:30:04PM -07
On Tue, Oct 1, 2019 at 10:06 AM Sean Christopherson
wrote:
>
> On Tue, Oct 01, 2019 at 07:20:17AM -0700, Jim Mattson wrote:
> > On Mon, Sep 30, 2019 at 5:45 PM Huang, Kai wrote:
> > >
> > > On Mon, 2019-09-30 at 12:23 -0700, Jim Mattson wrote:
> > > >
On Tue, Oct 1, 2019 at 10:54 AM Sean Christopherson
wrote:
>
> On Tue, Oct 01, 2019 at 10:23:31AM -0700, Jim Mattson wrote:
> > On Tue, Oct 1, 2019 at 10:06 AM Sean Christopherson
> > wrote:
> > >
> > > On Tue, Oct 01, 2019 at 07:20:17AM -0700, Jim Mattson wr
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f6ac63bf0e..c1ecb8a710 100644
--- a
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu
---
target/riscv/pmp.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ebd874cde3
If PMP permission of any address has been changed by updating PMP entry,
flush all TLB pages to prevent from getting old permission.
Signed-off-by: Jim Shu
---
target/riscv/pmp.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index ebd874cde3
Like MMU translation, add qemu log of PMP permission checking for
debugging.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 12
1 file changed, 12 insertions(+)
diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
index f6ac63bf0e..c1ecb8a710 100644
--- a
PMP permission.
To fix this issue, this patch set addes the feature to propagate PMP
permission to the TLB page and flush TLB pages if PMP permission has
been changed.
The patch set is tested on Zephyr RTOS userspace testsuite on QEMU riscv32
virt machine.
Jim Shu (3):
target/riscv: propagate PM
Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.
PMP permission checking also use MMU-style API to change TLB permission
and size.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 84
Currently, PMP permission checking of TLB page is bypassed if TLB hits
Fix it by propagating PMP permission to TLB page permission.
PMP permission checking also use MMU-style API to change TLB permission
and size.
Signed-off-by: Jim Shu
---
target/riscv/cpu_helper.c | 84
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